DS2152L ,Enhanced T1 Single-Chip TransceiverFEATURES PIN ASSIGNMENT§ Complete DS1/ISDN-PRI transceiverfunctionality§ Line interface can handle ..
DS2153Q ,E1 Single Chip TransceiverTABLE OF CONTENTS 1 DETAILED DESCRIPTION.4 1.1 INTRODUCTION..4 1.2 READER’S NOTE4 2
DS2153Q-A7 ,E1 Single Chip TransceiverApplications ALE(AS) 7 TSER 39 Fully Independent Transmit and Receive 8 38WR (R/W) TCLK Functiona ..
DS2154L ,Enhanced E1 Single Chip TransceiverTABLE OF CONTENTS1.0 INTRODUCTION.4New
DS2154L+ ,Enhanced E1 Single Chip TransceiverTABLE OF CONTENTS 1 DETAILED DESCRIPTION.6 1.1 INTRODUCTION ........6 1.1.1 New
DS2154LA2 ,Enhanced E1 Single Chip TransceiverApplications Fully Independent Transmit and Receive Functionality ORDERING INFORMATION Full Acce ..
DS2152L
Enhanced T1 Single-Chip Transceiver
FEATURESComplete DS1/ISDN-PRI transceiver
functionality§ Line interface can handle both long and short haul
trunks§ 32-bit or 128-bit crystal-less jitter attenuatorGenerates DSX-1 and CSU line build outsFrames to D4, ESF, and SLC-96R formats§ Dual onboard two-frame elastic store slip buffers
that can connect to asynchronous backplanes up to
8.192 MHz§ 8-bit parallel control port that can be used directly
on either multiplexed or non-multiplexed buses
(Intel or Motorola)§ Extracts and inserts robbed-bit signalingDetects and generates yellow (RAI) and blue
(AIS) alarms§ Programmable output clocks for Fractional T1Fully independent transmit and receive
functionality§ Integral HDLC controller with 16-byte buffers for
the FDL§ Generates and detects in-band loop codes from 1
to 8 bits in length including CSU loop codesContains ANSI 1's density monitor and enforcer§ Large path and line error counters including BPV,
CV, CRC6, and framing bit errorsPin compatible with DS2154 E1 Enhanced Single-Chip Transceiver5V supply; low power CMOS100-pin 14mm2 body LQFP package
PIN ASSIGNMENT
ORDERING INFORMATIONDS2152L (0°C to 70°C)DS2152LN (-40°C to +85°C)
DESCRIPTIONThe DS2152 T1 Enhanced Single-Chip Transceiver contains all of the necessary functions for connection
to T1 lines, whether they be DS-1 long haul or DSX-1 short haul. The clock recovery circuitry
automatically adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both
DSX-1 line build outs as well as CSU line build outs of -7.5 dB, -15 dB, and -22.5 dB. The onboard jitter
attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive datapaths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It
is also used for extracting and inserting robbed-bit signaling data and FDL data. The device contains a set
of internal registers which the user can access and control the operation of the unit. Quick access via the
parallel control port allows a single controller to handle many T1 lines. The device fully meets all of the
latest T1 specifications including ANSI T1.403-1995, ANSI T1.231-1993, AT&T TR 62411 (12-90),
DS2152DS2152
TABLE OF CONTENTS
1.0 INTRODUCTION..................................................................................... 4Block Diagram............................................................................................................................... 6
Pin List........................................................................................................................................... 7
Pin Description.............................................................................................................................. 9Register Map.................................................................................................................................. 13
2.0 PARALLEL PORT................................................................................... 17
3.0CONTROL, ID, AND TEST REGISTERS................................................ 18Payload Loopback......................................................................................................................... 23
Framer Loopback........................................................................................................................... 23
Pulse Density Enforcer.................................................................................................................. 25Local Loopback............................................................................................................................. 27
Power-up Sequence....................................................................................................................... 29
Remote Loopback.......................................................................................................................... 29
4.0STATUS AND INFORMATION REGISTERS.......................................... 30
5.0ERROR COUNT REGISTERS................................................................ 38Line Code Violation Count Register............................................................................................. 39Path Code Violation Count Register.............................................................................................. 39
Multiframes Out of SYNC Count Register................................................................................... 40
6.0 DSO MONITORING FUNCTION............................................................. 41
7.0SIGNALING OPERATION....................................................................... 44Processor Based Signaling.......................................................................................................... 44
Hardware Based Signaling.......................................................................................................... 46
8.0 PER-CHANNEL CODE (IDLE) GENERATION AND LOOPBACK.......... 47Transmit Side Code Generation..................................................................................................... 47
Receive Side Code Generation...................................................................................................... 49
9.0CLOCK BLOCKING REGISTERS.......................................................... 51
10.0ELASTIC STORES OPERATION............................................................ 52
11.0FDL/FS EXTRACTION AND INSERTION................................................ 53HDLC and BOC Controller for the FDL....................................................................................... 53Legacy FDL Support..................................................................................................................... 63
D4/SLC-96 Operation.................................................................................................................... 64
12.0 PROGRAMMABLE IN-BAND CODE GENERATION AND DETECTION 65
DS2152
14.0 LINE INTERFACE FUNCTION................................................................ 69
15.0 TIMING DIAGRAMS................................................................................ 74Transmit Data Flow Diagram........................................................................................................ 80
16.0 CHARACTERISTICS.............................................................................. 81Absolute Maximum Rating............................................................................................................ 81
DC Parameters............................................................................................................................... 81
AC Parameters............................................................................................................................... 82Timing............................................................................................................................................ 85
Package Description...................................................................................................................... 93
DS2152
1.0 INTRODUCTIONThe DS2152 is a superset version of the popular DS2151 T1 Single-Chip Transceiver offering the new
features listed below. All of the original features of the DS2151 have been retained and software created
for the original devices is transferable into the DS2152.
New Featuresoption for non-multiplexed bus operationcrystal-less jitter attenuation§ additional hardware signaling capability including:receive signaling reinsertion to a backplane multiframe syncavailability of signaling in a separate PCM data streamsignaling freezinginterrupt generated on change of signaling data§ per-channel code insertion in both transmit and receive pathsfull HDLC controller for the FDL with 16-byte buffers in both transmit and receive pathsRCL, RLOS, RRA, and RAIS alarms now interrupt on change of state8.192 MHz clock synthesizer§ per-channel loopbackaddition of hardware pins to indicate carrier loss & signaling freezeline interface function can be completely decoupled from the framer/formatter to allow:interface to optical, HDSL, and other NRZ interfacesability to “tap” the transmit and receive bipolar data streams for monitoring purposes– ability to corrupt data and insert framing errors, CRC errors, etc.transmit and receive elastic stores now have independent backplane clocksability to monitor one DS0 channel in both the transmit and receive pathsaccess to the data streams in between the framer/formatter and the elastic storesAIS generation in the line interface that is independent of loopbacks§ ability to calculate and check CRC6 according to the Japanese standardability to pass the F-bit position through the elastic stores in the 2.048 MHz backplane modeprogrammable in-band loop code generator and detector
Functional DescriptionThe analog AMI/B8ZS waveform off the T1 line is transformer-coupled into the RRING and RTIP pinsof the DS2152. The device recovers clock and data from the analog signal and passes it through the jitter
attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the
framing/multi-frame pattern. The DS2152 contains an active filter that reconstructs the analog received
signal for the non-linear losses that occur in transmission. The device has a usable receive sensitivity of 0
dB to -36 dB, which allows the device to operate on cables up to 6000 feet in length. The receive sideframer locates D4 (SLC-96) or ESF multiframe boundaries as well as detects incoming alarms, including
carrier loss, loss of synchronization, blue (AIS) and yellow alarms. If needed, the receive side elastic store
can be enabled in order to absorb the phase and frequency differences between the recovered T1 data
stream and an asynchronous backplane clock which is provided at the RSYSCLK input. The clock
applied at the RSYSCLK input can be either a 2.048 MHz clock or a 1.544 MHz clock. The RSYSCLKcan be a bursty clock with speeds up to 8.192 MHz.
The transmit side of the DS2152 is totally independent from the receive side in both the clock
requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic
DS2152
TTIP and TRING pins via a coupling transformer. The line driver can handle both long (CSU) and short
haul (DSX-1) lines.
Reader’s NoteThis data sheet assumes a particular nomenclature of the T1 operating environment. In each 125 us frame,
there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent first followed bychannel 1. Each channel is made up of 8 bits which are numbered 1 to 8. Bit number 1 is the MSB and is
transmitted first. Bit number 8 is the LSB and is transmitted last. Throughout this data sheet, the
following abbreviations will be used:
D4 Superframe (12 frames per multiframe) Multiframe StructureSLC-96 Subscriber Loop Carrier - 96 Channels (SLC-96 is an AT&T registered trademark)
ESF Extended Superframe (24 frames per multiframe) Multiframe Structure
B8ZS Bipolar with 8 0 Subsitution
CRC Cyclical Redundancy Check
Ft Terminal Framing Pattern in D4Fs Signaling Framing Pattern in D4
FPS Framing Pattern in ESF
MF Multiframe
BOC Bit Oriented Code
HDLC High Level Data Link ControlFDLFacility Data Link
