DS2151QB+ ,T1 Single Chip TransceiverFEATURES PIN ASSIGNMENT§ Complete DS1/ISDN-PRI transceiverFUNCTIONAL BLOCKSfunctionality§ Line inte ..
DS2151QBX2 ,T1 Single Chip TransceiverDS2151QT1 Single-Chip Transceiverwww.dalsemi.com
DS2151QNB ,T1 Single Chip TransceiverTABLE OF CONTENTS1. Introduction2. Parallel Control Port3. Control Registers4. Status and Informati ..
DS2152L ,Enhanced T1 Single-Chip TransceiverFEATURES PIN ASSIGNMENT§ Complete DS1/ISDN-PRI transceiverfunctionality§ Line interface can handle ..
DS2153Q ,E1 Single Chip TransceiverTABLE OF CONTENTS 1 DETAILED DESCRIPTION.4 1.1 INTRODUCTION..4 1.2 READER’S NOTE4 2
DS2153Q-A7 ,E1 Single Chip TransceiverApplications ALE(AS) 7 TSER 39 Fully Independent Transmit and Receive 8 38WR (R/W) TCLK Functiona ..
DS2151QB+-DS2151QBX2-DS2151QNB
T1 Single Chip Transceiver
FEATURESComplete DS1/ISDN-PRI transceiver
functionalityLine interface can handle both long- and
short-haul trunks§ 32-bit or 128-bit jitter attenuatorGenerates DSX-1 and CSU line build outsFrames to D4, ESF, and SLC-96R formatsDual onboard two-frame elastic store slip
buffers that connect to backplanes up to 8.192MHz8-bit parallel control port that can be used on
either multiplexed or non-multiplexed busesExtracts and inserts Robbed-Bit signalingDetects and generates yellow and blue alarms§ Programmable output clocks for Fractional T1Fully independent transmit and receive
functionalityOnboard FDL support circuitryGenerates and detects CSU loop codes§ Contains ANSI one’s density monitor and
enforcerLarge path and line error counters including
BPV, CV, CRC6, and framing bit errorsPin compatible with DS2153Q E1 Single-Chip Transceiver5V supply; low power CMOSIndustrial grade version (-40°C to +85°C)
available (DS2151QN)
PIN ASSIGNMENT
DESCRIPTIONThe DS2151Q T1 Single-Chip Transceiver (SCT) contains all of the necessary functions for connection
to T1 lines whether they be DS-1 long haul or DSX-1 short haul. The clock recovery circuitry
automatically adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both
DSX-1 line build outs as well as CSU build outs of -7.5 dB, -15 dB, and -22.5 dB. The onboard jitterattenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data
paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms.
It is also used for extracting and inserting Robbed-Bit signaling data and FDL data. The device contains
a set of 64 8-bit internal registers which the user can access to control the operation of the unit. Quick
access via the parallel control port allows a single micro to handle many T1 lines. The device fully meets
ALE
RLINK
RLCLK
DVSS
RCLK
RCHCLK
RSER
RSYNC
RLOS/LOTC
SYSCLK
TSER
TCLK
DVDD
TSYNC
TLINK
TLCLK
TCHBLK
TRING
TVDD
TVSS
TTIP
RCHBLK
ACLKI
BTS
RTIP
RRING
RVDD
RVSS
XTAL1XTAL2
INT1INT2
ACTUAL SIZE OF 44-PIN PLCC
FUNCTIONAL BLOCKS
DS2151Q
TABLE OF CONTENTS1. Introduction
2. Parallel Control Port
3. Control Registers
4. Status and Information Registers
5. Error Count Registers
6. FDL/Fs Extraction/Insertion
7. Signaling Operation
8. Transmit Transparency and Idle Registers
9. Clock Blocking Registers
10. Elastic Stores Operation
11. Receive Mark Registers
12. Line Interface Functions
13. Timing Diagrams and Transmit Flow Diagram
14. DC and AC Characteristics
1.0INTRODUCTIONThe analog AMI waveform off of the T1 line is transformer coupled into the RRING and RTIP pins of
the DS2151Q. The device recovers clock and data from the analog signal and passes it through the jitterattenuation mux to the receive side framer where the digital serial stream is analyzed to locate the framing
pattern. If needed, the receive side elastic store can be enabled in order to absorb the phase and frequency
differences between the recovered T1 data stream and an asynchronous backplane clock which is
provided at the SYSCLK input.
The transmit side of the DS2151Q is totally independent from the receive side in both the clock
requirements and characteristics. Data can be either provided directly to the transmit formatter or via an
elastic store. The transmit formatter will provide the necessary data overhead for T1 transmission. Once
the data stream has been prepared for transmission, it is sent via the jitter attenuation mux to the
waveshaping and line driver functions. The DS2151Q will drive the T1 line from the TTIP and TRINGpins via a coupling transformer.
DS2151Q
DS2151Q BLOCK DIAGRAM Figure 1-1
DS2151Q
PIN DESCRIPTION Table 1-1
DS2151Q
