DS2149Q ,5 V T1/J1 line interface unitTABLE OF CONTENTS 1. DETAILED DESCRIPTION.......4 2. OPERATING MODES......5 3. INITIALIZATION AND R ..
DS2149Q+ ,5V T1/J1 Line Interface UnitTABLE OF CONTENTS 1. DETAILED DESCRIPTION.......4 2. OPERATING MODES......5 3. INITIALIZATION AND R ..
DS2149QN ,5 V T1/J1 line interface unitAPPLICATIONS Four CSU Filters from 0dB to -22.5dB Routers Transmit/Receive Performance Monitor ..
DS2149QN+ ,5V T1/J1 Line Interface UnitAPPLICATIONS Four CSU Filters from 0dB to -22.5dB Routers Transmit/Receive Performance Monitor ..
DS2151Q ,T1 Single Chip TransceiverTABLE OF CONTENTS1. Introduction2. Parallel Control Port3. Control Registers4. Status and Informati ..
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DS2149Q-DS2149QN
5 V T1/J1 line interface unit
GENERAL DESCRIPTION The DS2149 is a fully integrated LIU for long-
haul or short-haul T1 applications over twisted-
pair installations. It interfaces to two twisted-pair
lines—one pair for transmit and one pair for receive through an appropriate network
interface. The device can be configured for
control through software or hardware mode.
Software control is accomplished over a serial
port, in hardware mode; individual pin settings allow standalone operation. The device provides
a precise, crystal-less jitter attenuator that can be
placed in either the transmit or receive path.
APPLICATIONS Routers
Data Service Units (DSUs)
Channel Service Units (CSUs) Muxes
Switches
Channel Banks
T1/E1 Test Equipment
PIN CONFIGURATION
FEATURES ��Fully Integrated Line Interface Unit (LIU)
��Pin Compatible with LevelOne LXT362
��Supports Both Long Haul and Short Haul
��Crystal-Less Jitter Attenuator
��Jitter Attenuator Programmable for Transmit
or Receive Path
��Meets ANSI T1.102, T1.403, T1.408, and
AT&T 62411
��Usable Receive Sensitivity of 0dB to -36dB That Allows the Device to Operate on
0.63mm (22AWG) Cables Up to 6k Feet in
Length
��Five Line Build-Out Settings for Short-Haul
Applications
��Four CSU Filters from 0dB to -22.5dB
��Transmit/Receive Performance Monitors
with Driver-Fail, Monitor-Open, and Loss-
of-Signal Outputs
��Bipolar or NRZ Interface
��Programmable B8ZS Encoder/Decoder
��QRSS Generator/Detector
��Local, Remote, and Analog Loopbacks
��Generates and Detects In-Band Loop-Up and
Loop-Down Codes
��Serial Interface Provides Access to Control
Registers
ORDERING INFORMATION
DS2149
5V T1/J1 Line Interface Unit
DS2149
TABLE OF CONTENTS
1. DETAILED DESCRIPTION.................................................................................................4
2. OPERATING MODES.........................................................................................................5
3. INITIALIZATION AND RESET............................................................................................9
4. REGISTER DEFINITIONS..................................................................................................9
5. TRANSMITTER...................................................................................................................15 5.1 TRANSMIT DIGITAL DATA INTERFACE...................................................................................15
5.2 TRANSMIT MONITORING......................................................................................................15
5.3 TRANSMIT IDLE MODE.........................................................................................................15
5.4 TRANSMIT PULSE SHAPE....................................................................................................15
6. RECEIVER..........................................................................................................................15 6.1 RECEIVE EQUALIZER..........................................................................................................15
6.2 RECEIVE DATA RECOVERY..................................................................................................15
6.3 RECEIVE DIGITAL-DATA INTERFACE.....................................................................................16
6.4 RECEIVE MONITOR MODE...................................................................................................16
7. JITTER ATTENUATION.....................................................................................................16
8. HARDWARE MODE...........................................................................................................16
9. SOFTWARE MODE............................................................................................................17 9.1 INTERRUPT HANDLING........................................................................................................17
10. DIAGNOSTIC MODE OPERATION....................................................................................19 10.1 LOOPBACK MODES.............................................................................................................20
10.1.1 Local Loopback (LLB).................................................................................................................20
10.1.2 Analog Loopback (ALB)..............................................................................................................20
10.1.3 Remote Loopback (RLB)............................................................................................................20
10.1.4 Network Loopback......................................................................................................................20
10.1.5 Dual Loopback...........................................................................................................................20
10.2 INTERNAL PATTERN GENERATION AND DETECTION...............................................................21
10.2.1 Transmit Alarm-Indication Signal (TAIS).....................................................................................21
10.2.2 Quasirandom Signal Source (QRSS).........................................................................................21
10.2.3 In-Band Network Loop-Up or Loop-Down Code Generator.........................................................22
10.3 ERROR INSERTION AND DETECTION.....................................................................................22
10.3.1 Bipolar Violation Insertion (INSBPV)...........................................................................................22
10.3.2 Logic Error Insertion (INSLE)......................................................................................................22
10.3.3 Logic Error Detection (QPD).......................................................................................................22
10.3.4 Bipolar Violation Detection (BPV)...............................................................................................22
10.4 ALARM MONITORING...........................................................................................................23
10.4.1 Receive-Carrier Loss (RCL).......................................................................................................23
10.4.2 Alarm-Indication-Signal Detection (AIS)......................................................................................23
10.4.3 Driver-Fail Monitor-Open (DFMO)..............................................................................................23
10.4.4 Jitter Attenuator Limit Trip (JALT)...............................................................................................23
10.5 OTHER DIAGNOSTIC REPORTS............................................................................................23
10.5.1 Receive Line-Attenuation Indication...........................................................................................23
11. NETWORK INTERFACE....................................................................................................24
DS2149
LIST OF FIGURES Figure 1-1. Block Diagram.......................................................................................................................................4
Figure 2-1. Hardware Mode Pinout........................................................................................................................6
Figure 2-2. Serial Port Mode Pinout.......................................................................................................................6
Figure 9-1. Serial Data Port Operation for Read Access..................................................................................18
Figure 9-2. Serial Data Port Operation for Write Access..................................................................................18
Figure 10-1. Loopbacks in the DS2149 Block Diagram....................................................................................21
Figure 11-1. Basic Network Interface..................................................................................................................25
Figure 11-2. T1 Transmit Pulse Template..........................................................................................................26
Figure 11-3. Jitter Tolerance.................................................................................................................................27
Figure 11-4. Jitter Attenuation...............................................................................................................................27
Figure 12-1. Serial Bus Read Timing (MODE1 = 1)..........................................................................................29
Figure 12-2. Serial Bus Write Timing (MODE1 = 1)..........................................................................................29
Figure 12-3. AC Characteristics for Receive Side.............................................................................................30
Figure 12-4. AC Characteristics for Transmit Side............................................................................................31
LIST OF TABLES Table 2-A. Operating Modes...................................................................................................................................5
Table 2-B. Control Pins for Hardware and Software Modes..............................................................................5
Table 2-C. Signal Descriptions...............................................................................................................................7
Table 4-A. Register Map..........................................................................................................................................9
Table 4-B. Register Bit Positions............................................................................................................................9
Table 4-C. Jitter Attenuator Selection..................................................................................................................10
Table 4-D. Line Code and Interface Selection...................................................................................................10
Table 4-E. Line Build-out Selection......................................................................................................................10
Table 4-F. Data Pattern Selection........................................................................................................................11
Table 9-A. CLKE Pin Selection.............................................................................................................................17
Table 9-B. Control and Operation Mode Selection............................................................................................19
Table 10-A. Diagnostic Modes..............................................................................................................................19
Table 11-A. Specifications for Receive Transformer.........................................................................................24
Table 11-B. Specifications for Transmit Transformer........................................................................................24
Table 11-C. Transformer Turns Ratio vs. Series Resistance..........................................................................24
DS2149
1. DETAILED DESCRIPTION The DS2149 is a complete T1 line interface unit (LIU) for short-haul and long-haul applications. Receive
sensitivity adjusts automatically to the incoming signal and can be limited to -18dB, -26dB, or -36dB. The device can generate the necessary DSX-1 line build-outs or CSU line build-outs of 0dB,
-7.5dB, -15dB, and -22.5dB. The on-board crystal-less jitter attenuator requires a 1.544MHz reference
clock. The jitter attenuator FIFO is selectable to either 32 bits or 128 bits in depth and can be placed in
either the transmit or receive data paths. The DS2149 has diagnostic capabilities such as loopbacks and
QRSS pattern generation and detection. The device can also generate and detect the in-band loop-up and loop-down codes specified in AT&T 62411. The device can be configured for control using a serial
interface, or for hardware mode. The device fully meets all of the latest T1 specifications including ANSI
T1.102-1999, ANSI T1.403-1999, ANSI T1.408, and AT&T 62411.
Figure 1-1. Block Diagram
DS2149
2. OPERATING MODES The DS2149 has several pins with multiple functions and names according to the selected operating
mode. These operating modes are summarized in the tables below.
Table 2-A. Operating Modes Control pins are affected by serial port and hardware modes.
Table 2-B. Control Pins for Hardware and Software Modes DS2149
Figure 2-1. Hardware Mode Pinout
Figure 2-2. Serial Port Mode Pinout
DS2149
Table 2-C. Signal Descriptions
DS2149
Note 1: G.703 requires an accuracy of ±50ppm for T1. TR62411 and ANSI specifications require an accuracy of ±32ppm for T1 interfaces.
Note 2: Input pins have three operating modes.
DS2149
3. INITIALIZATION AND RESET During power-up, all control registers are cleared, disabling the transmitter outputs. The device requires a
master clock supplied to the MCLK input pin to operate the PLL. This master clock must be independent, free-running, and jitter free.
A reset initializes the status and state machines for the RCL, AIS, NLOOP, and QRSS blocks. Under
software control, setting the RESET bit (CR2.7) clears all registers. Allow up to 100ms for the receiver to
recover from initialization.
4. REGISTER DEFINITIONS The DS2149 contains eight registers for configuring the device and reading status. These are accessible
using the serial port. Table 4-A lists the register names and addresses.
Reading or writing to the internal registers requires writing one address/command byte prior to
transferring register data. The first bit written (LSb) of the address/command byte specifies whether the access is a read (1) or a write (0). The next 6 bits identify the register address.
The last bit (MSb) of the address/command byte is the burst mode bit. When the burst bit is enabled (set
to 1) and a READ operation is performed, addresses 10h through 17h are read sequentially, starting at
address 10h. And when the burst bit is enabled and a WRITE operation is performed, addresses 10h through 17h are written sequentially, starting at address 10h. Burst operation is stopped once address 17h
is read. All data transfers are initiated by driving the CS input low. All data transfers are terminated if the
CS input transitions high. Port control logic is disabled and SDO is tri-stated when CS is high.
Table 4-A. Register Map
Table 4-B. Register Bit Positions
Note: Set unused bits to 0 for normal operation.
DS2149
CR1 (B010000): Control Register 1
MSb LSb
Table 4-C. Jitter Attenuator Selection
Table 4-D. Line Code and Interface Selection
Table 4-E. Line Build-out Selection
DS2149
CR2 (B010001): Control Register 2
MSb LSb
Table 4-F. Data Pattern Selection
CR3 (B010010): Control Register 3
MSb LSb DS2149
IMR (B010011): Interrupt Mask Register
MSb LSb
TSR (B010100): Transition Status Register
MSb LSb DS2149
SR (B010101): Status Register
MSb LSb
IR (B010110): Information Register
MSb LSb Receive Level Indication: RL0 is the LSB and RL3 is the MSB of a 4-bit nibble that is used to indicate the inbound signal strength. Convert the binary to decimal and multiply by -2.5dB. The result indicates the approximate
attenuation seen at the receiver inputs.
DS2149
CR4 (B010111): Control Register 4
MSb LSb DS2149
5. TRANSMITTER 5.1 Transmit Digital Data Interface Data is clocked into the device at the TCLK rate. In bipolar mode, TPOS and TNEG are the data inputs;
in NRZ mode, TDATA is the data input. Input data can pass through either the jitter attenuator or the
B8ZS encoder or both. In software mode, setting ENCENB enables B8ZS encoding. In hardware mode,
floating the MODE1 pin enables B8ZS encoding. With B8ZS encoding enabled, the L0 through L3 inputs determine the coding and is listed in Table 4-E. TCLK supplies input synchronization. See Section 12 for
the TCLK and MCLK timing requirements.
5.2 Transmit Monitoring In software mode, the DFMO bit in the status register is set when an open circuit in the transmitter path is
detected. A transition on this bit can provide an interrupt, and a transition sets the DFMO bit in the
transition status register. Setting CDFMO in the interrupt mask register, leaving a 1 in that bit location
masks the interrupt.
5.3 Transmit Idle Mode Transmit idle mode allows multiple transceivers to be connected to a single line for redundant
applications. When TCLK is not present, transmit idle mode becomes active, and TTIP and TRING change to high-impedance state. Remote loopback, dual loopback, TAIS, or detection of network loop-up
code in the receive direction temporarily disable the high-impedance state.
5.4 Transmit Pulse Shape As shown in Table 4-E, line build-out control inputs (L0 through L3) determine the transmit pulse shape.
In software mode, these control inputs are located in control register 1; in hardware mode, these control
inputs are the L0 through L3 pins. Shaped pulses meeting the various T1, DS1, and DSX-1 specifications are applied to the AMI line driver
for transmission onto the line at TTIP and TRING. The transceiver produces DSX-1 pulses for short-haul T1 applications (settings from 0dB to 6dB of cable) and DS1 pulses for long-haul T1 applications
(settings from 0dB to -22.5dB). Refer to Table 4-E for pulse mask specifications.
6. RECEIVER A 1:1 transformer provides the interface between the twisted pair and receiver inputs RTIP and RRING.
Recovered data is output at RPOS and RNEG (or RDATA in NRZ mode), and the recovered clock is
output at RCLK. See Section 12 for receiver timing specifications.
6.1 Receive Equalizer The receiver can apply up to 36dB of gain. Control of the equalizer is accomplished by the L0 through L3 control inputs. These control signals are detailed in Table 4-E and determine the maximum gain that is
applied. In software mode, these control signals are in Control Register 1; in hardware mode, these
control inputs are the L0 through L3 pins. With L0 low, up to 36dB of gain can be applied; when L0 is
high, 26dB can be applied in the gain limit to provide better noise immunity in shorter loop operations.
6.2 Receive Data Recovery The clock and data recovery engine provides input jitter tolerance that exceeds the requirements of AT&T
DS2149
6.3 Receive Digital-Data Interface Recovered data is routed to the RCL monitor. In software mode, data also goes through the alarm
indication signal (AIS) monitor. The jitter attenuator can be enabled or disabled in the receive path or transmit path. Received data can be routed to the B8ZS decoder or bypassed. Finally, the device can send
the digital data to the framer as either bipolar or NRZ data.
6.4 Receive Monitor Mode The receive equalizer can be used in monitor-mode applications. Monitor-mode applications require
20dB of resistive attenuation of the signal, plus an allowance for cable attenuation (less than 20dB). In
software mode, setting CR3.4 (EQZMON20) enables the device to operate in monitor-mode applications
that require 20dB of resistive attenuation of the signal. Setting CR3.3 (EQZMON26) enables the device
to operate in monitor-mode applications that require 26dB of resistve attenuation. Setting both CR3.3 and CR3.4 enables the device to operate in monitor-mode applications that require 32dB of resistive
attenuation. The monitor mode feature is not available in hardware mode.
7. JITTER ATTENUATION The jitter attenuator only requires a jitter-free clock at 1.544MHz applied to the MCLK input. In
hardware mode, the jitter attenuator is a 32-bit FIFO buffer. Pulling the JASEL pin high places the jitter attenuator in the receive path. Pulling the JASEL pin low places the jitter attenuator in the transmit path,
floating the JASEL pin disables the jitter attenuator. In software mode, clearing CR1.6 (JASEL0) disables
the jitter attenuator, setting CR1.6 enables the jitter attenuator. If enabled, clearing CR1.7 (JASEL1)
places the jitter attenuator in the transmit path, setting CR1.7 places the jitter attenuator in the receive
path. The jitter attenuator FIFO is 32 bits in length if CR3.2 (JA128) is cleared, 128 bits if set. The device clocks data in the jitter attenuator using TCLK if placed in the transmit path, and RCLK if placed in the
receive path. Data is clocked out of the jitter attenuator using the dejittered clock produced by the internal
PLL. When the jitter attenuator is within two bits of overflowing or underflowing, the jitter attenuator
will adjust the output clock by one-eighth of a clock cycle. The jitter attenuator adds an average delay of
16 bits if the buffer depth is 32 bits in length, 64 bits if the buffer depth is 128 bits in length. In the event of an RCL condition, if the jitter attenuator is in the receive path then RCLK is derived from MCLK.
Transition Status register bit TSR.6 (JALT) indicates that the jitter attenuator has adjusted the output
clock. This bit is latched, when set it remains set until the software reads the bit. The JALT can also
produce a hardware interrupt.
8. HARDWARE MODE The DS2149 operates in hardware mode when the MODE1 pin is pulled low or floated. In hardware mode, configuration of the device is under control of various input pins. RPOS, RNEG, and RDATA are
valid on the rising edge of RCLK only. Some functions such as INT, clock edge select, and some
diagnostic modes are not available.
