DS2148GN ,5V E1/T1/J1 Line Interfaceapplications. The crystal-less onboard jitter attenuator requires only a 2.048MHz MCLK for both E1 ..
DS2148T ,5V E1/T1/J1 Line InterfaceTABLE OF CONTENTS 1. LIST OF FIGURES. 4 2. LIST OF TABLES .. 5 3. INTRODUCTION... 6 3.1 DOCUMENT R ..
DS2148TN ,5V E1/T1/J1 Line Interfaceapplications. Throughout the data sheet, J1 is represented wherever T1 exists. Receive sensitivity ..
DS2148TN+ ,5V E1/T1/J1 Line InterfaceFEATURES Complete E1, T1, or J1 Line Interface Unit TOP VIEW 44(LIU) Supports Both Long- and ..
DS2149DK ,T1/J1 Line Interface Unit Design Kit DS2149DK/DS21349DK T1/J1 Line Interface Unit Design Kit
DS2149Q ,5 V T1/J1 line interface unitTABLE OF CONTENTS 1. DETAILED DESCRIPTION.......4 2. OPERATING MODES......5 3. INITIALIZATION AND R ..
DS2148GN-DS2148T-DS2148TN
5V E1/T1/J1 Line Interface
FEATURES ��Complete E1, T1, or J1 line interface unit (LIU)
��Supports both long- and short-haul trunks
��Internal software-selectable receive-side
termination for 75Ω/100Ω/120�
��5V power supply
��32-bit or 128-bit crystal-less jitter attenuator
requires only a 2.048MHz master clock for
both E1 and T1 with option to use 1.544MHz
for T1
��Generates the appropriate line build outs,
with and without return loss, for E1 and
DSX-1 and CSU line build outs for T1
��AMI, HDB3, and B8ZS, encoding/decoding
��16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz clock output synthesized to
recovered clock
��Programmable monitor mode for receiver
��Loopbacks and PRBS pattern generation/
detection with output for received errors
��Generates/detects in-band loop codes, 1 to 16
bits including CSU loop codes
��8-bit parallel or serial interface with optional
hardware mode
��Multiplexed and nonmultiplexed parallel bus supports Intel or Motorola
��Detects/generates blue (AIS) alarms
��NRZ/bipolar interface for TX/RX data I/O
��Transmit open-circuit detection
��Receive Carrier Loss (RCL) indication (G.775)
��High-Z State for TTIP and TRING
��50mA (rms) current limiter
PIN DESCRIPTION
ORDERING INFORMATION
Single-Channel Devices: DS2148TN 44-Pin TQFP (-40�C to +85�C)
DS2148T 44-Pin TQFP (0� C to +70� C)
DS2148GN 7mm CABGA (-40�C to +85�C)
DS2148G 7mm CABGA (0� C to +70� C)
Four-Channel Devices: DS21Q48N (Quad) BGA (-40�C to +85�C)
DS21Q48 (Quad) BGA (0� C to +70�C)
44 TQFP
DS2148/DS21Q48
5V E1/T1/J1 Line Interface
DS2148/Q48
DESCRIPTION The DS2148 is a complete selectable E1 or T1 Line Interface Unit (LIU) for short- and long-haul
applications. Throughout the data sheet, J1 is represented wherever T1 exists. Receive sensitivity adjusts
automatically to the incoming signal and can be programmed for 0dB to 12dB or 0dB to 43dB for E1
applications and 0dB to 30dB or 0dB to 36dB for T1 applications. The device can generate the necessary
G.703 E1 waveshapes in 75Ω or 120Ω applications and DSX-1 line build outs or CSU line build outs of 0dB, -7.5dB, -15dB, and -22.5dB for T1 applications. The crystal-less onboard jitter attenuator requires
only a 2.048MHz MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK
in T1 applications). The jitter attenuator FIFO is selectable to either 32 bits or 128 bits in depth and can
be placed in either the transmit or receive data paths. An X 2.048MHz output clock synthesized to RCLK
is available for use as a backplane system clock (where n = 1, 2, 4, or 8). The DS2148 has diagnostic capabilities such as loopbacks and PRBS pattern generation/detection. 16-bit loop-up and loop-down
codes can be generated and detected. The device can be controlled via an 8-bit parallel muxed or
nonmuxed port, serial port or used in hardware mode. The device fully meets all of the latest E1 and T1
specifications including ANSI T1.403-1999, ANSI T1.408, AT&T TR 62411, ITU G.703, G.704, G.706,
G.736, G.775, G.823, I.431, O.151, O.161, ETSI ETS 300 166, JTG.703, JTI.431, JJ-20.1, TBR12, TBR13, and CTR4.
DS2148/Q48
TABLE OF CONTENTS 1. LIST OF FIGURES...............................................................................................................................4
2. LIST OF TABLES................................................................................................................................5
3. INTRODUCTION.................................................................................................................................6
3.1 DOCUMENT REVISION HISTORY............................................................................................6
4. PIN DESCRIPTION.............................................................................................................................9
5. HARDWARE MODE.........................................................................................................................22
5.1 REGISTER MAP..........................................................................................................................23
5.2 PARALLEL PORT OPERATION................................................................................................24
5.3 SERIAL PORT OPERATION......................................................................................................24
6. CONTROL REGISTERS....................................................................................................................28
6.1 DEVICE POWER-UP AND RESET............................................................................................31
7 STATUS REGISTERS.......................................................................................................................34
8. DIAGNOSTICS..................................................................................................................................39
8.1 IN-BAND LOOP CODE GENERATION AND DETECTION...................................................39
8.2 LOOPBACKS...............................................................................................................................43
8.2.1 Remote Loopback (RLB).........................................................................................................43
8.2.2 Local Loopback (LLB)............................................................................................................43
8.2.3 Analog Loopback (LLB).........................................................................................................44
8.2.4 Dual Loopback (DLB)............................................................................................................44
8.3 PRBS GENERATION AND DETECTION.................................................................................44
8.4 ERROR COUNTER......................................................................................................................44
8.4.1 Error Counter Update............................................................................................................45
8.5 ERROR INSERTION....................................................................................................................45
9. ANALOG INTERFACE.....................................................................................................................46
9.1 RECEIVER....................................................................................................................................46
9.2 TRANSMITTER...........................................................................................................................47
9.3 JITTER ATTENUATOR..............................................................................................................47
9.4 G.703 SYNCHRONIZATION SIGNAL......................................................................................48
10. DS21Q48 QUAD LIU.........................................................................................................................56
11. DC CHARACTERISTICS..................................................................................................................60
12. AC CHARACTERISTICS..................................................................................................................62
13. MECHANICAL DIMENSIONS.........................................................................................................71
13.1 MECHANICAL DIMENSIONSQUAD VERSION.................................................................73
DS2148/Q48
1. LIST OF FIGURES Figure 3-1 DS2148 BLOCK DIAGRAM.....................................................................................................7 Figure 3-2 RECEIVE LOGIC......................................................................................................................8
Figure 3-3 TRANSMIT LOGIC...................................................................................................................9
Figure 4-1 PARALLEL PORT MODE PINOUT (BIS1 = 0, BIS0 = 1 or 0)............................................21
Figure 4-2 SERIAL PORT MODE PINOUT (BIS1 = 1, BIS0 = 0)..........................................................21
Figure 4-3 HARDWARE MODE PINOUT (BIS1 = 1, BIS0 = 1)............................................................22 Figure 5-1 SERIAL PORT OPERATION FOR READ ACCESS (R=1) MODE 1..................................25
Figure 5-2 SERIAL PORT OPERATION FOR READ ACCESS MODE 2.............................................25
Figure 5-3 SERIAL PORT OPERATION FOR READ ACCESS MODE 3.............................................26
Figure 5-4 SERIAL PORT OPERATION FOR READ ACCESS MODE 4.............................................26
Figure 5-5 SERIAL PORT OPERATION FOR WRITE ACCESS (R=0) MODES 1&2 ...
27 Figure 5-6 SERIAL PORT OPERATION FOR WRITE ACCESS MODES 3&4
...
27
Figure 9-1 BASIC INTERFACE
..50
Figure 9-2 PROTECTED INTERFACE USING INTERNAL RECEIVE TERMINATION....................51
Figure 9-3 PROTECTED INTERFACE USING EXTERNAL RECEIVE TERMINATION..................52
Figure 9-4 E1 TRANSMIT PULSE TEMPLATE......................................................................................53 Figure 9-5 T1 TRANSMIT PULSE TEMPLATE......................................................................................54
Figure 9-6 JITTER TOLERANCE.............................................................................................................55
Figure 9-7 JITTER ATTENUATION........................................................................................................55
Figure 10-1 BGA 12 x 12 PIN LAYOUT..................................................................................................59
Figure 12-1 INTEL BUS READ TIMING (PBTS = 0, BIS1 = 0, BIS0 = 0)............................................63 Figure 12-2 INTEL BUS WRITE TIMING (PBTS = 0, BIS1 = 0, BIS0 = 0)...........................................63
Figure 12-3 MOTOROLA BUS TIMING (PBTS = 1, BIS1 = 0, BIS0 = 0) ............................................64
Figure 12-4 INTEL BUS READ TIMING (PBTS = 0, BIS1 = 0, BIS0 = 1)............................................66
Figure 12-5 INTEL BUS WRITE TIMING (PBTS = 0, BIS1 = 0, BIS0 = 1)...........................................66
Figure 12-6 MOTOROLA BUS READ TIMING (PBTS = 1, BIS1 = 0, BIS0 = 1).................................67 Figure 12-7 MOTOROLA BUS WRITE TIMING (PBTS = 1, BIS1 = 0, BIS0 = 1)................................67
Figure 12-8 SERIAL BUS TIMING (BIS1 = 1, BIS0 = 0)........................................................................68
Figure 12-9 RECEIVE SIDE TIMING......................................................................................................69
Figure 12-10 TRANSMIT SIDE TIMING.................................................................................................70
DS2148/Q48
2. LIST OF TABLES Table 4-1 BUS INTERFACE SELECTION................................................................................................9
Table 4-2a PIN ASSIGNMENT.................................................................................................................10
Table 4-2b PIN DESCRIPTIONS (Sorted by Pin Name, DS2148T Pin Numbering)...............................11
Table 4-3a PIN ASSIGNMENT IN SERIAL PORT MODE.....................................................................13 Table 4-3b PIN DESCRIPTIONS IN SERIAL PORT MODE (Sorted by Pin Name, DS2148T Pin
Numbering)..........................................................................................................................................14
Table 4-4a PIN ASSIGNMENT IN HARDWARE MODE.......................................................................16
Table 4-4b PIN DESCRIPTIONS IN HARDWARE MODE (Sorted by Pin Name, DS2148T Pin
Numbering)..........................................................................................................................................16 Table 4-5 LOOPBACK CONTROL IN HARDWARE MODE................................................................20
Table 4-6 TRANSMIT DATA CONTROL IN HARDWARE MODE.....................................................20
Table 4-7 RECEIVE SENSITIVITY SETTINGS......................................................................................20
Table 4-8 MONITOR GAIN SETTINGS..................................................................................................20
Table 4-9 INTERNAL RX TERMINATION SELECT.............................................................................20 Table 4-10 MCLK SELECTION................................................................................................................20
Table 5-1 REGISTER MAP.......................................................................................................................23
Table 6-1 MCLK SELECTION..................................................................................................................29
Table 6-2 RECEIVE SENSITIVITY SETTINGS......................................................................................31
Table 6-3 BACK PLANE CLOCK SELECT.............................................................................................32 Table 6-4 MONITOR GAIN SETTINGS..................................................................................................32
Table 6-5 INTERNAL RX TERMINATION SELECT.............................................................................33
Table 7-1 RECEIVED ALARM CRITERIA.............................................................................................35
Table 7-2 RECEIVE LEVEL INDICATION.............................................................................................38
Table 8-1 TRANSMIT CODE LENGTH...................................................................................................40 Table 8-2 RECEIVE CODE LENGTH......................................................................................................40
Table 8-3 DEFINITION OF RECEIVED ERRORS..................................................................................44
Table 8-4 FUNCTION OF ECRS BITS AND RNEG PIN........................................................................45
Table 9-1 LINE BUILD OUT SELECT FOR E1 IN REGISTER CCR4 (ETS = 0).................................48
Table 9-2 LINE BUILD OUT SELECT FOR T1 IN REGISTER CCR4 (ETS = 1).................................48 Table 9-3 TRANSFORMER SPECIFICATIONS FOR 5V OPERATION...............................................49
Table 10-1 DS21Q48 PIN ASSIGNMENT................................................................................................56
DS2148/Q48
3. INTRODUCTION The analog AMI/HDB3 waveform off the E1 line or the AMI/B8ZS waveform off the T1 line is
transformer coupled into the RTIP and RRING pins of the DS2148. The user has the option to use
internal software-selectable receive-side termination for 75Ω/100Ω/120� applications or external
termination. The device recovers clock and data from the analog signal and passes it through the jitter attenuation MUX outputting the received line clock at RCLK and bipolar or NRZ data at RPOS and
RNEG. The DS2148 contains an active filter that reconstructs the analog-received signal for the nonlinear
losses that occur in transmission. The receive circuitry also is configurable for various monitor
applications. The device has a usable receive sensitivity of 0dB to -43dB (E1) and 0dB to -36dB (T1),
which allows the device to operate on 0.63mm (22AWG) cables up to 2.5km (E1) and 6k feet (T1) in length. Data input at TPOS and TNEG is sent via the jitter attenuation MUX to the waveshaping circuitry
and line driver. The DS2148 will drive the E1 or T1 line from the TTIP and TRING pins via a coupling
transformer. The line driver can handle both CEPT 30/ISDN-PRI lines for E1 and long-haul (CSU) or
short-haul (DSX-1) lines for T1.
3.1 DOCUMENT REVISION HISTORY 1) 100�/60� termination reversed in Internal Rx Termination Select tables, 091799.
2) Add DS21Q48 pinout, 092899.
3) Correct VSM pin number in Q48 (12 x 12 BGA) from G5 to G4, 120699. 4) Add timing diagram for Status Register (write access mode); Add mechanical dimensions for the
quad version, 032900.
5) Timing diagram for Status Register (write access mode) added; elaboration on burst mode bit; add
mechanical dimensions for the quad version, 050300.
6) Changes to datasheet to indicate 5V only part, 011801. 7) Added supply current measurement; added thermal characteristics of quad package, 092001.
8) Corrected typos and removed instances of 3V operation, 082504.
DS2148/Q48
DS2148 BLOCK DIAGRAM Figure 3-1 TRING
TTIPRRING
RTIP
to
/
to
*(R
to
BIS0
BIS1
HRST*
TESTBPCLK
RPOS
RCLK
RNEG
TPOS
TCLK
TNEG
PBEORCL/LOTC
DS2148/Q48
RECEIVE LOGIC Figure 3-2 RPOS
RNEG
From
Remote
LoopbackRCLK
PBEO
DS2148/Q48
TRANSMIT LOGIC Figure 3-3
4. PIN DESCRIPTION The DS2148 can be controlled in a parallel port mode, a serial port mode, or a hardware mode (Table 4-1,
4-2, and 4-3). The parallel and serial port modes are described in Section 3, and the hardware mode is
described below.
BUS INTERFACE SELECTION Table 4-1 TPOS
TNEG
Remote
Loopback
TCLK
DS2148/Q48
PIN ASSIGNMENT IN PARALLEL PORT MODE Table 4-2a
DS2148/Q48
PIN DESCRIPTIONS IN PARALLEL PORT MODE (Sorted by Pin Name, DS2148T Pin Numbering) Table 4-2b
DS2148/Q48
DS2148/Q48
PIN ASSIGNMENT IN SERIAL PORT MODE Table 4-3a
DS2148/Q48
PIN DESCRIPTIONS IN SERIAL PORT MODE (Sorted by Pin Name, DS2148T Pin Numbering) Table 4-3b
DS2148/Q48
DS2148/Q48
PIN ASSIGNMENT IN HARDWARE MODE Table 4-4a
DS2148/Q48
PIN DESCRIPTIONS IN HARDWARE MODE (Sorted by Pin Name, DS2148T Pin Numbering) Table 4-4b
DS2148/Q48
DS2148/Q48
NOTES: 1) G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specs require an
accuracy of ±32ppm for T1 interfaces.
2) * Denotes active low.
DS2148/Q48
LOOP BACK CONTROL IN HARDWARE MODE Table 4-5
TRANSMIT DATA CONTROL IN HARDWARE MODE Table 4-6
RECEIVE SENSITIVITY SETTINGS Table 4-7
MONITOR GAIN SETTINGS Table 4-8
INTERNAL RX TERMINATION SELECT Table 4-9
MCLK SELECTION Table 4-10
DS2148/Q48
PARALLEL PORT MODE PINOUT (BIS1 = 0, BIS0 = 1 or 0) Figure 4-1
SERIAL PORT MODE PINOUT (BIS1 = 1, BIS0 = 0) Figure 4-2 tie high
tie low
e l
tie low
tie low (MUX) or high (non-MUX)
DS2148/Q48
HARDWARE MODE PINOUT (BIS1 = 1, BIS0 = 1) Figure 4-3
5. HARDWARE MODE In hardware mode (BIS1 = 1, BIS0 = 1), pins 1-19, 23, 25, 31, and 44 are redefined to be used for
initializing the DS2148. BPCLK (pin 31) defaults to a 16.384MHz output when in hardware mode. The RCL/LOTC (pin 25) is designated to RCL when in hardware mode. JABDS (CCR4.2) defaults to logic
0. The RHBE (CCR2.3) and THBE (CCR2.2) control bits are combined and controlled by HBE at pin 11
while the RSCLKE (CCR5.3) and TSCLKE (CCR5.2) bits are combined and controlled by SCLKE at
pin 4. TCES (CCR2.1) and RCES (CCR2.0) are combined and controlled by CES at pin 12. The
transmitter functions are combined and controlled by TX1 (pin 15) and TX0 (pin 14). LOOP1 (pin 17) and LOOP0 (pin 16) control the loopback functions. All other control bits default to the logic 0 setting.
tie high
tie high
DS2148/Q48
5.1 Register Map
REGISTER MAP Table 5-1
NOTES: 1) Register addresses 16h to 1Fh do not exist.
2) In the Serial Port Mode, the LSB is on the right hand side.
3) In the Serial Port Mode, data is read and written LSB first.
4) In the Serial Port Mode, the A bit (the LSB) determines whether the access is a read (A = 1) or a write
(A = 0).
5) In the Serial Port Mode, the B bit (the MSB) determines whether the access is a burst access (B = 1) or a single register access (B = 0).
DS2148/Q48
5.2 Parallel Port Operation When using the parallel interface on the DS2148 (BIS1 = 0) the user has the option for either multiplexed
bus operation (BIS1 = 0, BIS0 = 0) or nonmultiplexed bus operation (BIS1 = 0, BIS0 = 1). The DS2148
can operate with either Intel or Motorola bus timing configurations. If the PBTS pin is tied low, Intel
timing will be selected; if tied high, Motorola timing will be selected. All Motorola bus signals are listed
in parenthesis (). See the timing diagrams in Section 12 for more details.
5.3 Serial Port Operation Setting BIS1 = 1 and BIS0 = 0 enables the serial bus interface on the DS2148. Port read/write timing is
unrelated to the system transmit and receive timing, allowing asynchronous reads or writes by the host.
See Section 12 for the AC timing of the serial port. All serial port accesses are LSB first. See Figure 5-1, Figure 5-2, Figure 5-3, and Figure 5-4 for more details.
Reading or writing to the internal registers requires writing one address/command byte prior to
transferring register data. The first bit written (LSB) of the address/command byte specifies whether the
access is a read (1) or a write (0). The next 5 bits identify the register address. Bit 7 is reserved and must be set to 0 for proper operation.
The last bit (MSB) of the address/command byte is the burst mode bit. When the burst bit is enabled
(B = 1) and a READ operation is performed, addresses 0 through 15h are read sequentially, starting at
address 0h. And when the burst bit is enabled and a WRITE operation is performed, addresses 0 through 16h are written sequentially, starting at address 0h. Burst operation is stopped once address 15h is read.
See Figure 5-5 and Figure 5-6 for more details.
All data transfers are initiated by driving the CS* input low. When input clock-edge select (ICES) is low,
input data is latched on the rising edge of SCLK and when ICES is high, input data is latched on the falling edge of SCLK. When output clock-edge select (OCES) is low, data is output on the falling edge of
SCLK and when OCES is high, data is output on the rising edge of SCLK. Data is held until the next
falling or rising edge. All data transfers are terminated if the CS* input transitions high. Port control logic
is disabled and SDO is 3-stated when CS* is high.
DS2148/Q48
SERIAL PORT OPERATION FOR READ ACCESS (R=1) MODE 1 Figure 5-1
ICES = 1 (sample SDI on the falling edge of SCLK)
OCES = 1 (update SDO on rising edge of SCLK)
SERIAL PORT OPERATION FOR READ ACCESS MODE 2 Figure 5-2
ICES = 1 (sample SDI on the falling edge of SCLK) OCES = 0 (update SDO on falling edge of SCLK) 345678910111213141516
SDI
CS*
(lsb)
(msb)
READ ACCESS ENABLED 345678910111213141516
SCLK
SDI
CS*
(lsb)(msb)
(lsb)
(msb)
DS2148/Q48
SERIAL PORT OPERATION FOR READ ACCESS MODE 3 Figure 5-3
ICES = 0 (sample SDI on the rising edge of SCLK)
OCES = 0 (update SDO on falling edge of SCLK)
SERIAL PORT OPERATION FOR READ ACCESS MODE 4 Figure 5-4
ICES = 0 (sample SDI on the rising edge of SCLK)
OCES = 1 (update SDO on rising edge of SCLK) 345678910111213141516
SDI
CS*
(lsb)(msb)
(lsb)
(msb) 2345678910111213141516
CS*
(lsb)(msb)
(lsb)
(msb)
DS2148/Q48
SERIAL PORT OPERATION FOR WRITE ACCESS (R=0) Figure 5-5
MODES 1 and 2 ICES = 1 (sample SDI on the falling edge of SCLK)
SERIAL PORT OPERATION FOR WRITE ACCESS (R=0) Figure 5-6
MODES 3 and 4 ICES = 0 (sample SDI on the rising edge of SCLK) 345678910111213141516SCLK
CS*
(msb)
SDO
(lsb)(msb)
(lsb)
WRITE ACCESS ENABLED 345678910111213141516SCLK
CS*
(msb)
SDI
SDO
(lsb)(msb)
(lsb)
WRITE ACCESS ENABLED
DS2148/Q48
6. CONTROL REGISTERS
CCR1 (00H): COMMON CONTROL REGISTER 1
(MSB) (LSB)
SYMBOL POSITION DESCRIPTION ETS CCR1.7 E1/T1 Select. 0 = E1
1 = T1
NRZE CCR1.6 NRZ Enable.
0 = Bipolar data at RPOS/RNEG and TPOS/TNEG 1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a
positive going pulse when device receives a BPV, CV, or EXZ.
See figure 3-2 and figure 3-3.
RCLA CCR1.5 Receive Carrier Loss Alternate Criteria. 0 = RCL declared upon 255 (E1) or 192 (T1) consecutive zeros
1 = RCL declared upon 2048 (E1) or 1544 (T1) consecutive
zeros
ECUE CCR1.4 Error Counter Update Enable. A 0 to 1-transition forces the
next clock cycle to load the error counter registers with the latest counts and reset the counters. The user must wait a
minimum of two clocks cycles (976ns for E1 and 1296ns for
T1) before reading the error count registers to allow for a proper
update. See Section 6 and figure 3-2 for details.
JAMUX CCR1.3 Jitter Attenuator MUX. Controls the source for JACLK. See Figure 3-1.
0 = JACLK sourced from MCLK (2.048MHz or 1.544MHz at
MCLK)
1 = JACLK sourced from internal PLL (2.048MHz at MCLK)
TTOJ CCR1.2 TCLK to JACLK. Internally connects TCLK to JACLK. See figure 3-3.
0 = disabled
1 = enabled
TTOR CCR1.1 TCLK to RCLK. Internally connects TCLK to RCLK. See
figure 3-3. 0 = disabled
1 = enabled
LOTCMC CCR1.0 Loss Of Transmit Clock Mux Control. Determines whether
the transmit logic should switch to JACLK if the TCLK input
should fail to transition. See figure 3-3. 0 = do not switch to JACLK if TCLK stops
1 = switch to JACLK if TCLK stops
DS2148/Q48
MCLK SELECTION Table 6-1
CCR2 (01H): COMMON CONTROL REGISTER 2
(MSB) (LSB)
SYMBOL POSITION DESCRIPTION
P25S CCR2.7 Pin 25 Select. Forced to logic 0 in hardware mode.
0 = toggles high during a Receive Carrier Loss condition
1 = toggles high if TCLK does not transition for at least 5�s. - CCR2.6 Not Assigned. Should be set to zero when written to. SCLD CCR2.5 Short Circuit Limit Disable (ETS = 0). Controls the 50mA
(rms) current limiter.
0 = enable 50mA current limiter
1 = disable 50mA current limiter CLDS CCR2.4 Custom Line Driver Select. Setting this bit to a one will
redefine the operation of the transmit line driver. When this bit
is set to a one and CCR4.5 = CCR4.6 = CCR4.7 = 0, then the
device will generate a square wave at the TTIP and TRING outputs instead of a normal waveform. When this bit is set to a
one and CCR4.5 = CCR4.6 = CCR4.7 � 0, then the device will
force TTIP and TRING outputs to become open drain drivers
instead of their normal push-pull operation. This bit should be
set to zero for normal operation of the device. Contact the factory for more details on how to use this bit.
RHBE CCR2.3 Receive HDB3/B8ZS Enable. See figure 3-2.
0 = enable HDB3 (E1)/B8ZS (T1)
1 = disable HDB3 (E1)/B8ZS (T1)
THBE CCR2.2 Transmit HDB3/B8ZS Enable. See figure 3-3. 0 = enable HDB3 (E1)/B8ZS (T1)
1 = disable HDB3 (E1)/B8ZS (T1)
TCES CCR2.1 Transmit Clock Edge Select. Selects which TCLK edge to
sample TPOS and TNEG. See figure 3-3.
0 = sample TPOS and TNEG on falling edge of TCLK 1 = sample TPOS and TNEG on rising edge of TCLK
RCES CCR2.0 Receive Clock Edge Select. Selects which RCLK edge to
update RPOS and RNEG. See figure 3-2.
0 = update RPOS and RNEG on rising edge of RCLK
1 = update RPOS and RNEG on falling edge of RCLK
DS2148/Q48
CCR3 (02H): COMMON CONTROL REGISTER 3
(MSB) (LSB)
SYMBOL POSITION DESCRIPTION TUA1 CCR3.7 Transmit Unframed All Ones. The polarity of this bit is set
such that the device will transmit an all ones pattern on power-
up or device reset. This bit must be set to a one to allow the
device to transmit data. The transmission of this data pattern is
always timed off of the JACLK (See Figure 3-1). 0 = transmit all ones at TTIP and TRING
1 = transmit data normally
ATUA1 CCR3.6 Automatic Transmit Unframed All Ones. Automatically
transmit an unframed all ones pattern at TTIP and TRING
during a receive carrier loss (RCL) condition or a receive all ones condition.
0 = disabled
1 = enabled
TAOZ CCR3.5 Transmit Alternate Ones and Zeros. Transmit a
101010
pattern at TTIP and TRING. The transmission of this data pattern is always timed off of TCLK (Figure 3-1).
0 = disabled
1 = enabled
TPRBSE CCR3.4 Transmit PRBS Enable. Transmit a 215 - 1 (E1) or a 220 - 1
(T1) PRBS at TTIP and TRING. See figure 3-3.
0 = disabled
1 = enabled
TLCE CCR3.3 Transmit Loop Code Enable. Enables the transmit side to
transmit the loop up code in the Transmit Code Definition registers (TCD1 and TCD2). See Section 6 and figure 3-3 for
details.
0 = disabled
1 = enabled
LIRST CCR3.2 Line Interface Reset. Setting this bit from a zero to a one will initiate an internal reset that resets the clock recovery state
machine and re-centers the jitter attenuator. Normally this bit is
only toggled on power-up. Must be cleared and set again for a
subsequent reset.
IBPV CCR3.1 Insert BPV. A 0 to 1 transition on this bit will cause a single BiPolar Violation (BPV) to be inserted into the transmit data
stream. Once this bit has been toggled from a 0 to a 1, the
device waits for the next occurrence of three consecutive ones
to insert the BPV. This bit must be cleared and set again for a
subsequent error to be inserted. See figure 3-3. IBE CCR3.0 Insert Bit Error. A 0 to 1 transition on this bit will cause a
single logic error to be inserted into the transmit data stream.
DS2148/Q48
6.1 Device Power-Up And Reset
The DS2148 will reset itself upon power-up, setting all writeable registers to 00h and clearing the status
and information registers. CCR3.7 (TUA1) = 0 results in the LIU transmitting unframed all ones. After
the power supplies have settled following power-up, initialize all control registers to the desired settings,
then toggle the LIRST bit (CCR3.2). The DS2148 can be reset at anytime to the default settings by
bringing HRST* (pin 29) low (level triggered) or by powering down and powering up again.
CCR4 (03H): COMMON CONTROL REGISTER 4
(MSB) (LSB)
SYMBOL POSITION DESCRIPTION L2 CCR4.7 Line Build Out Select Bit 2. Sets the transmitter build out
(Table 9-1 for E1 and Table 9-2 for T1)
L1 CCR4.6 Line Build Out Select Bit 1. Sets the transmitter build out
(Table 9-1 for E1 and Table 9-2 for T1) L0 CCR4.5 Line Build Out Select Bit 0. Sets the transmitter build out
(Table 9-1 for E1 and Table 9-2 for T1)
EGL CCR4.4 Receive Equalizer Gain Limit. This bit controls the sensitivity
of the receive equalizer (Table 6-2)
JAS CCR4.3 Jitter Attenuator Select. 0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
JABDS CCR4.2 Jitter Attenuator Buffer Depth Select.
0 = 128 bits
1 = 32 bits (use for delay sensitive applications) DJA CCR4.1 Disable Jitter Attenuator. 0 = jitter attenuator enabled
1 = jitter attenuator disabled
TPD CCR4.0 Transmit Power-Down.
0 = normal transmitter operation 1 = powers down the transmitter and 3-states the TTIP and
TRING pins
RECEIVE SENSITIVITY SETTINGS Table 6-2
DS2148/Q48
CCR5 (04H): COMMON CONTROL REGISTER 5
(MSB) (LSB)
SYMBOL POSITION DESCRIPTION BPCS1 CCR5.7 Back Plane Clock Select 1. See Table 6-3 for details.
BPCS0 CCR5.6 Back Plane Clock Select 0. See Table 6-3 for details.
MM1 CCR5.5 Monitor Mode 1. See Table 6-4.
MM0 CCR5.4 Monitor Mode 0. See Table 6-4.
RSCLKE CCR5.3 Receive Synchronization Clock Enable. This control bit determines whether the line receiver should
handle normal T1/E1 signals or a synchronized signal.
E1 mode:
0 = receive normal E1 signal (Section 6 of G.703)
1 = receive 2.048 MHz synchronization signal (section 10 of G.703)
T1 mode:
0 = receive normal T1 signal
1 = receive 1.544 MHz synchronization signal
TSCLKE CCR5.2 Transmit Synchronization Clock Enable. This control bit determines whether the transmitter should
transmit normal T1/E1 signals or a synchronized signal.
E1 mode:
0 = transmit normal E1 signal (section 6 of G.703)
1 = transmit 2.048 MHz synchronization signal (section 10 of G.703)
T1 mode:
0 = transmit normal T1 signal
1 = transmit 1.544 MHz synchronization signal RT1 CCR5.1 Receive Termination 1. See Table 6-5 for details.
RT0 CCR5.0 Receive Termination 0. See Table 6-5 for details.
BACK PLANE CLOCK SELECT Table 6-3
DS2148/Q48
DS2148/Q48
INTERNAL RX TERMINATION SELECT Table 6-5
CCR6 (05H): COMMON CONTROL REGISTER 6
(MSB) (LSB)
SYMBOL POSITION DESCRIPTION LLB CCR6.7 Local Loopback. In Local Loopback (LLB), transmit data will
be looped back to the receive path passing through the jitter
attenuator if it is enabled. Data in the transmit path will act as
normal. See Figure 3-1 (DS2148 BLOCK DIAGRAM Figure 3-1 and section 8-2.2 for details.
0 = loopback disabled
1 = loopback enabled
RLB CCR6.6 Remote Loopback. In Remote Loopback (RLB), data output
from the clock/data recovery circuitry will be looped back to the transmit path passing through the jitter attenuator if it is
enabled. Data in the receive path will act as normal while data
presented at TPOS and TNEG will be ignored. See Figure 3-1
(DS2148 BLOCK DIAGRAM Figure 3-1 and section 8-2.1 for
details. 0 = loopback disabled
1 = loopback enabled
ARLBE CCR6.5 Automatic Remote Loopback Enable and Reset. When this
bit is set high, the device will automatically go into remote
loopback when it detects loop-up code programmed into the receive loop-up code definition registers (RUPCD1 and
RUPCD2) for a minimum of 5 seconds and it will also set the
RIR2.1 status bit. Once in a RLB state, it will remain in this
state until it has detected the loop code programmed into the
receive loop-down code definition registers (RDNCD1 and RDNCD2) for a minimum of 5 seconds at which point it will
force the device out of RLB and clear RIR2.1. Toggling this bit
from a 1 to a 0 can reset the automatic RLB circuitry. The
action of the automatic remote loopback circuitry is logically
ORed with the RLB (CCR6.6) control bit (i.e., either one can cause a RLB to occur).
ALB CCR6.4 Analog Loopback. In analog loopback (ALB), signals at TTIP
and TRING will be internally connected to RTIP and RRING.
DS2148/Q48
SYMBOL POSITION DESCRIPTION
Figure 3-1 and section 8-2.3 for more details.
0 = loopback disabled
1 = loopback enabled RJAB CCR6.3 RCLK Jitter Attenuator Bypass. This control bit allows the
recovered received clock and data to bypass the jitter
attenuation while still allowing the BPCLK output to use the
jitter attenuator. See Figure 3-1 and section 9-1 for details.
0 = disabled 1 = enabled
ECRS2 CCR6.2 Error Count Register Select 2. See Section 8.4 for details.
ECRS1 CCR6.1 Error Count Register Select 1. See Section 8.4 for details.
ECRS0 CCR6.0 Error Count Register Select 0. See Section 8.4 for details.
7. STATUS REGISTERS
There are three registers that contain information on the current real-time status of the device, status
register (SR), and receive information registers 1 and 2 (RIR1/RIR2). When a particular event has
occurred (or is occurring), the appropriate bit in one of these three registers will be set to a one. Some of
the bits in SR, RIR1, and RIR2 are latched bits and some are real-time bits. The register descriptions
below list which status bits are latched and which are real-time bits. For latched status bits, when an event or an alarm occurs the bit is set to a one and will remain set until the user reads that bit. The bit will be
cleared when it is read and it will not be set again until the event has occurred again. Two of the latched
status bits (RUA1 & RCL) will remain set after reading if the alarm is still present.
The user will always precede a read of any of the three status registers with a write. The byte written to the register will inform the DS2148 which bits the user wishes to read and have cleared. The user will
write a byte to one of these registers with a one in the bit positions to be read and a zero in the other bit
positions. When a one is written to a bit location, that location will be updated with the latest information.
When a zero is written to a bit position, that bit position will not be updated and the previous value will
be held. A write to the status and information registers will be immediately followed by a read of the same register. The read result should be logically ANDed with the mask byte that was just written and
this value should be written back into the same register to ensure that bit does indeed clear. This second
write step is necessary because the alarms and events in the status registers occur asynchronously with
respect to their access via the parallel port. This write-read-write scheme allows an external
microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. This operation is key in controlling the DS2148 with higher-order software languages.
The bits in the SR register have the unique ability to initiate a hardware interrupt via the INT* output pin.
Each of the alarms and events in the SR can be either masked or unmasked from the interrupt pin via the
interrupt mask register (IMR). The interrupts caused by the RCL, RUA1, and LOTC bits in SR act differently than the interrupts caused by the other status bits in SR. The RCL, RUA1 and LOTC bits will
force the INT* pin low whenever they change state (i.e., go active or inactive). The INT* pin will be
allowed to return high (if no other interrupts are present) when the user reads the alarm bit that caused the
interrupt to occur even if the alarm is still present. The other status bits in SR can force the INT* pin low
when they are set. The INT* pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur.
DS2148/Q48
RECEIVED ALARM CRITERIA Table 7-1
NOTES:
1) Receive carrier loss (RCL) is also known as loss-of-signal (LOS) or Red Alarm in T1.
2) See CCR1.5 for details.
SR (06H): STATUS REGISTER
(MSB) (LSB)
SYMBOL POSITION DESCRIPTION
LUP
(latched)
SR.7 Loop Up Code Detected. Set when the loop up code defined in
registers RUPCD1 and RUPCD2 is being received. See Section 6 for details.
LDN
(latched)
SR.6 Loop Down Code Detected. Set when the loop down code
defined in registers RDNCD1 and RDNCD2 is being received.
See Section 6 for details.
LOTC (real time) SR.5 Loss of Transmit Clock. Set when the TCLK pin has not
transitioned for 5�sec (�2�sec). Will force the LOTC pin high.
RUA1
(latched)
SR.4 Receive Unframed All Ones. Set when an unframed all ones
code is received at RRING and RTIP. See Table 7-1for details.
RCL (latched) SR.3 Receive Carrier Loss. Set when a receive carrier loss condition exists at RRING and RTIP. See Table 7-1for details.
TCLE
(real time)
SR.2 Transmit Current Limit Exceeded. Set when the 50mA (rms)
current limiter is activated whether the current limiter is enabled
or not.
TOCD (real time) SR.1 Transmit Open Circuit Detect. Set when the device detects that the TTIP and TRING outputs are open circuited.
PRBSD
(real time)
SR.0 PRBS Detect. Set when the receive-side detects a 215-1 (E1) or
a 220-1 (T1) Pseudo Random Bit Sequence (PRBS).
DS2148/Q48
IMR (07H): INTERRUPT MASK REGISTER
(MSB) (LSB)
SYMBOL POSITION DESCRIPTION
LUP IMR.7 Loop Up Code Detected.
0 = interrupt masked 1 = interrupt enabled
LDN IMR.6 Loop Down Code Detected. 0 = interrupt masked
1 = interrupt enabled
LOTC IMR.5 Loss of Transmit Clock. 0 = interrupt masked
1 = interrupt enabled
RUA1 IMR.4 Receive Unframed All Ones.
0 = interrupt masked
1 = interrupt enabled RCL IMR.3 Receive Carrier Loss. 0 = interrupt masked
1 = interrupt enabled
TCLE IMR.2 Transmit Current Limiter Exceeded.
0 = interrupt masked 1 = interrupt enabled
TOCD IMR.1 Transmit Open Circuit Detect. 0 = interrupt masked
1 = interrupt enabled
PRBSD IMR.0 PRBS Detection. 0 = interrupt masked
1 = interrupt enabled
DS2148/Q48
RIR1 (08H): RECEIVE INFORMATION REGISTER 1
(MSB) (LSB)
SYMBOL POSITION DESCRIPTION
ZD
(latched)
RIR1.7 Zero Detect. Set when a string of at least four (ETS = 0) or
eight (ETS = 1) consecutive zeros (regardless of the length of the string) have been received. Will be cleared when read.
16ZD
(latched)
RIR1.6 Sixteen Zero Detect. Set when at least 16 consecutive zeros
(regardless of the length of the string) have been received. Will
be cleared when read.
HBD (latched) RIR1.5 HDB3/B8ZS Word Detect. Set when an HDB3 (ETS = 0) or B8ZS (ETS = 1) code word is detected independent of whether
the receive HDB3/B8ZS mode (CCR4.6) is enabled. Will be
cleared when read. Useful for automatically setting the line
coding.
RCLC (latched) RIR1.4 Receive Carrier Loss Clear. Set when the RCL alarm has met the clear criteria defined in Table 7-1. Will be cleared when
read.
RUA1C
(latched)
RIR1.3 Receive Unframed All Ones Clear. Set when the unframed all
ones signal is no longer detected. Will be cleared when read.
See Table 7-1. JALT
(latched)
RIR1.2 Jitter Attenuator Limit Trip. Set when the jitter attenuator
FIFO reaches to within 4 bits of its useful limit. Will be cleared
when read. Useful for debugging jitter attenuation operation.
N/A RIR1.1 Not Assigned. Could be any value when read. N/A RIR1.0 Not Assigned. Could be any value when read.
