DS2148DK ,5V E1/T1/J1 Line InterfaceTABLE OF CONTENTS 1 DETAILED DESCRIPTION........ 5 1.1 FUNCTION DESCRIPTION......5 1.2 DOCUMENT REV ..
DS2148G+ ,5V E1/T1/J1 Line InterfacePIN DESCRIPTION 10 3 HARDWARE MODE ....... 23 3.1 REGISTER MAP ........23 3.2 PARALLEL PORT OPERATI ..
DS2148G+ ,5V E1/T1/J1 Line Interface DS2148/DS21Q48 5V E1/T1/J1 Line Interface Unit PIN CONFIGURATION
DS2148GN ,5V E1/T1/J1 Line Interfaceapplications. The crystal-less onboard jitter attenuator requires only a 2.048MHz MCLK for both E1 ..
DS2148T ,5V E1/T1/J1 Line InterfaceTABLE OF CONTENTS 1. LIST OF FIGURES. 4 2. LIST OF TABLES .. 5 3. INTRODUCTION... 6 3.1 DOCUMENT R ..
DS2148TN ,5V E1/T1/J1 Line Interfaceapplications. Throughout the data sheet, J1 is represented wherever T1 exists. Receive sensitivity ..
DS2148DK-DS2148G+-DS2148TN+-DS21Q48A3N
5V E1/T1/J1 Line Interface
FEATURES � Complete E1, T1, or J1 Line Interface Unit
(LIU) � Supports Both Long- and Short-Haul Trunks � Internal Software-Selectable Receive-Side
Termination for 75Ω/100Ω/120Ω � 5V Power Supply � 32-Bit or 128-Bit Crystal-Less Jitter
Attenuator Requires Only a 2.048MHz
Master Clock for Both E1 and T1 with
Option to Use 1.544MHz for T1 � Generates the Appropriate Line Build-Outs,
With and Without Return Loss, for E1 and
DSX-1 and CSU Line Build-Outs for T1 � AMI, HDB3, and B8ZS, Encoding/Decoding � 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz Clock Output Synthesized to
Recovered Clock � Programmable Monitor Mode for Receiver � Loopbacks and PRBS Pattern Generation/
Detection with Output for Received Errors � Generates/Detects In-Band Loop Codes, 1 to
16 Bits including CSU Loop Codes � 8-Bit Parallel or Serial Interface with
Optional Hardware Mode � Multiplexed and Nonmultiplexed Parallel
Bus Supports Intel or Motorola � Detects/Generates Blue (AIS) Alarms � NRZ/Bipolar Interface for Tx/Rx Data I/O � Transmit Open-Circuit Detection � Receive Carrier Loss (RCL) Indication
(G.775) � High-Z State for TTIP and TRING � 50mA (RMS) Current Limiter
PIN CONFIGURATION
ORDERING INFORMATION
PART CHANNEL TEMP
RANGE
PIN-
PACKAGE
DS2148TN Single -40°C to +85°C 44 TQFP
DS2148TN+ Single -40°C to +85°C 44 TQFP
DS2148T Single 0°C to +70°C 44 TQFP
DS2148T+ Single 0°C to +70°C 44 TQFP
DS2148GN Single -40°C to +85°C 49 CSBGA
DS2148GN Single -40°C to +85°C 49 CSBGA
DS2148G Single 0°C to +70°C 49 CSBGA
DS2148G+ Single 0°C to +70°C 49 CSBGA
DS21Q48N Four -40°C to +85°C 144 CSBGA
DS21Q48 Four 0°C to +70°C 144 CSBGA
+ Denotes lead-free/RoHS-compliant package.
DS2148/DS21Q48
5V E1/T1/J1 Line Interface Unit
DS2148
49 CSBGA
(7mm x 7mm)
44 TQFP
DS2148 TOP VIEW
See Section 8for 144-pin CSBGA pinout.
DS2148/DS21Q48
TABLE OF CONTENTS DETAILED DESCRIPTION..................................................................................................5 1.1 FUNCTION DESCRIPTION..................................................................................................................5
1.2 DOCUMENT REVISION HISTORY.......................................................................................................6
PIN DESCRIPTION............................................................................................................10 HARDWARE MODE..........................................................................................................23 3.1 REGISTER MAP.............................................................................................................................23
3.2 PARALLEL PORT OPERATION.........................................................................................................24
3.3 SERIAL PORT OPERATION..............................................................................................................24
CONTROL REGISTERS....................................................................................................28 4.1 DEVICE POWER-UP AND RESET.....................................................................................................31
STATUS REGISTERS.......................................................................................................34 DIAGNOSTICS..................................................................................................................39 6.1 IN-BAND LOOP CODE GENERATION AND DETECTION......................................................................39
6.2 LOOPBACKS..................................................................................................................................43
6.2.1 Remote Loopback (RLB)......................................................................................................43
6.2.2 Local Loopback (LLB)...........................................................................................................43
6.2.3 Analog Loopback (ALB)........................................................................................................44
6.2.4 Dual Loopback (DLB)............................................................................................................44
6.3 PRBS GENERATION AND DETECTION............................................................................................44
6.4 ERROR COUNTER..........................................................................................................................44
6.4.1 Error Counter Update............................................................................................................45
6.5 ERROR INSERTION........................................................................................................................45
ANALOG INTERFACE......................................................................................................46 7.1 RECEIVER.....................................................................................................................................46
7.2 TRANSMITTER...............................................................................................................................47
7.3 JITTER ATTENUATOR.....................................................................................................................47
7.4 G.703 SYNCHRONIZATION SIGNAL.................................................................................................48
DS21Q48 QUAD LIU.........................................................................................................55 DC CHARACTERISTICS...................................................................................................59 9.1 THERMAL CHARACTERISTICS................................................................................................60
10 AC CHARACTERISTICS...................................................................................................61
11 PACKAGE INFORMATION...............................................................................................70 11.1 44-PIN TQFP (56-G4012-001).....................................................................................................70
11.2 49-BALL CSGBA (7MM X 7MM) (56-G6006-001)...........................................................................71
11.3 144-BALL CSBGA (17MM X 17MM) (56-G6011-001).....................................................................72
DS2148/DS21Q48
LIST OF FIGURES Figure 1-1. DS2148 Block Diagram............................................................................................................7
Figure 1-2. Receive Logic...........................................................................................................................8
Figure 1-3. Transmit Logic..........................................................................................................................9
Figure 2-1. Parallel Port Mode Pinout (BIS1 = 0, BIS0 = 1 or 0) (TQFP Package)..................................21
Figure 2-2. Serial Port Mode Pinout (BIS1 = 1, BIS0 = 0) (TQFP Package)............................................21
Figure 2-3. Hardware Mode Pinout (BIS1 = 1, BIS0 = 1) (TQFP Package).............................................22
Figure 3-1. Serial Port Operation for Read Access (R = 1) Mode 1.........................................................25
Figure 3-2. Serial Port Operation for Read Access Mode 2.....................................................................25
Figure 3-3. Serial Port Operation for Read Access Mode 3.....................................................................26
Figure 3-4. Serial Port Operation for Read Access Mode 4.....................................................................26
Figure 3-5. Serial Port Operation for Write Access (R = 0) Modes 1 and 2..............................................27
Figure 3-6. Serial Port Operation for Write Access (R = 0) Modes 3 and 4..............................................27
Figure 7-1. Basic Interface.......................................................................................................................49
Figure 7-2. Protected Interface Using Internal Receive Termination........................................................50
Figure 7-3. Protected Interface Using External Receive Termination.......................................................51
Figure 7-4. E1 Transmit Pulse Template..................................................................................................52
Figure 7-5. T1 Transmit Pulse Template..................................................................................................53
Figure 7-6. Jitter Tolerance......................................................................................................................54
Figure 7-7. Jitter Attenuation....................................................................................................................54
Figure 8-1. 144-Pin CSBGA (17mm x 17mm) Pinout...............................................................................58
Figure 10-1. Intel Bus Read Timing (PBTS = 0, BIS1 = 0, BIS0 = 0).......................................................62
Figure 10-2. Intel Bus Write Timing (PBTS = 0, BIS1 = 0, BIS0 = 0).......................................................62
Figure 10-3. Motorola Bus Timing (PBTS = 1, BIS1 = 0, BIS0 = 0)..........................................................63
Figure 10-4. Intel Bus Read Timing (PBTS = 0, BIS1 = 0, BIS0 = 1).......................................................65
Figure 10-5. Intel Bus Write Timing (PBTS = 0, BIS1 = 0, BIS0 = 1).......................................................65
Figure 10-6. Motorola Bus Read Timing (PBTS = 1, BIS1 = 0, BIS0 = 1)................................................66
Figure 10-7. Motorola Bus Write Timing (PBTS = 1, BIS1 = 0, BIS0 = 1)................................................66
Figure 10-8. Serial Bus Timing (BIS1 = 1, BIS0 = 0)................................................................................67
Figure 10-9. Receive Side Timing............................................................................................................68
Figure 10-10. Transmit Side Timing.........................................................................................................69
DS2148/DS21Q48
LIST OF TABLES Table 2-1. Bus Interface Selection...........................................................................................................10
Table 2-2. Pin Assignment in Parallel Port Mode.....................................................................................10
Table 2-3. Pin Descriptions in Parallel Port Mode (Sorted by Pin Name, DS2148T)...............................12
Table 2-4. Pin Assignment in Serial Port Mode........................................................................................14
Table 2-5. Pin Descriptions in Serial Port Mode (Sorted by Pin Name, DS2148T)..................................15
Table 2-6. Pin Assignment in Hardware Mode.........................................................................................17
Table 2-7. Pin Description in Hardware Mode (Sorted by Pin Name, DS2148T).....................................18
Table 2-8. Loopback Control in Hardware Mode......................................................................................20
Table 2-9. Transmit Data Control in Hardware Mode...............................................................................20
Table 2-10. Receive Sensitivity Settings..................................................................................................20
Table 2-11. Monitor Gain Settings............................................................................................................20
Table 2-12. Internal Rx Termination Select..............................................................................................20
Table 2-13. MCLK Selection.....................................................................................................................20
Table 3-1. Register Map...........................................................................................................................23
Table 4-1. MCLK Selection.......................................................................................................................29
Table 4-2. Receive Sensitivity Settings....................................................................................................31
Table 4-3. Backplane Clock Select...........................................................................................................32
Table 4-4. Monitor Gain Settings..............................................................................................................32
Table 4-5. Internal Rx Termination Select................................................................................................33
Table 5-1. Received Alarm Criteria..........................................................................................................35
Table 5-2. Receive Level Indication.........................................................................................................38
Table 6-1. Transmit Code Length.............................................................................................................40
Table 6-2. Receive Code Length..............................................................................................................40
Table 6-3. Definition of Received Errors...................................................................................................44
Table 6-4. Function of ECRS Bits and RNEG Pin....................................................................................45
Table 7-1. Line Build-Out Select for E1 in Register CCR4 (ETS = 0).......................................................48
Table 7-2. Line Build-Out Select for T1 in Register CCR4 (ETS = 1).......................................................48
Table 7-3. Transformer Specifications for 5V Operation..........................................................................48
Table 8-1. DS21Q48 Pin Assignment.......................................................................................................55
Table 9-1. Recommended DC Operating Conditions...............................................................................59
Table 9-2. Capacitance............................................................................................................................59
Table 9-3. DC Characteristics..................................................................................................................59
Table 9-4. Thermal Characteristics—DS21Q48 CSBGA Package...........................................................60
Table 9-5. Theta-JA (θJA) vs. Airflow........................................................................................................60
Table 10-1. AC Characteristics—Multiplexed Parallel Port (BIS1 = 0, BIS0 = 0)....................................61
Table 10-2. AC Characteristics—Nonmultiplexed Parallel Port (BIS1 = 0, BIS0 = 1)..............................64
Table 10-3. AC Characteristics—Serial Port (BIS1 = 1, BIS0 = 0)...........................................................67
Table 10-4. AC Characteristics—Receive Side........................................................................................68
Table 10-5. AC Characteristics—Transmit Side.......................................................................................69
DS2148/DS21Q48
1 DETAILED DESCRIPTION The DS2148 is a complete selectable E1 or T1 Line Interface Unit (LIU) for short- and long-haul
applications. Throughout the data sheet, J1 is represented wherever T1 exists. Receive sensitivity adjusts
automatically to the incoming signal and can be programmed for 0dB to 12dB or 0dB to 43dB for E1
applications and 0dB to 30dB or 0dB to 36dB for T1 applications. The device can generate the necessary
G.703 E1 waveshapes in 75Ω or 120Ω applications and DSX-1 line built-outs or CSU line built-outs of
0dB, -7.5dB, -15dB, and -22.5dB for T1 applications. The crystal-less onboard jitter attenuator requires
only a 2.048MHz MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK
in T1 applications). The jitter attenuator FIFO is selectable to either 32 bits or 128 bits in depth and can
be placed in either the transmit or receive data paths. An X 2.048MHz output clock synthesized to RCLK
is available for use as a backplane system clock (where n = 1, 2, 4, or 8). The DS2148 has diagnostic
capabilities such as loopbacks and PRBS pattern generation/detection. 16-bit loop-up and loop-down
codes can be generated and detected. The device can be controlled via an 8-bit parallel muxed or
nonmuxed port, serial port or used in hardware mode. The device fully meets all of the latest E1 and T1
specifications including ANSI T1.403-1999, ANSI T1.408, AT&T TR 62411, ITU G.703, G.704, G.706,
G.736, G.775, G.823, I.431, O.151, O.161, ETSI ETS 300 166, JTG.703, JTI.431, JJ-20.1, TBR12,
TBR13, and CTR4.
1.1 Function Description The analog AMI/HDB3 waveform off the E1 line or the AMI/B8ZS waveform off the T1 line is
transformer coupled into the RTIP and RRING pins of the DS2148. The user has the option to use
internal software-selectable receive-side termination for 75Ω/100Ω/120Ω applications or external
termination. The device recovers clock and data from the analog signal and passes it through the jitter
attenuation MUX outputting the received line clock at RCLK and bipolar or NRZ data at RPOS and
RNEG. The DS2148 contains an active filter that reconstructs the analog-received signal for the nonlinear
losses that occur in transmission. The receive circuitry also is configurable for various monitor
applications. The device has a usable receive sensitivity of 0dB to -43dB (E1) and 0dB to -36dB (T1),
which allows the device to operate on 0.63mm (22AWG) cables up to 2.5km (E1) and 6k feet (T1) in
length. Data input at TPOS and TNEG is sent via the jitter attenuation MUX to the waveshaping circuitry
and line driver. The DS2148 will drive the E1 or T1 line from the TTIP and TRING pins via a coupling
transformer. The line driver can handle both CEPT 30/ISDN-PRI lines for E1 and long-haul (CSU) or
short-haul (DSX-1) lines for T1.
