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DS21455-DS21458
Quad T1/E1/J1 Transceivers
GENERAL DESCRIPTION The DS21455 and DS21458 are quad monolithic
devices featuring independent transceivers that
can be software configured for T1, E1, or J1
operation. Each is composed of a line interface unit (LIU), framer, HDLC controllers, and a
TDM backplane interface, and is controlled via
an 8-bit parallel port configured for Intel or
Motorola bus operations. The DS21455* is a
direct replacement for the older DS21Q55 quad MCM device. The DS21458, in a smaller
package (17mm CSBGA) and featuring an
improved controller interface, is software
compatible with the older DS21Q55.
*The JTAG function on the DS21455/DS21458 is a single
controller for all four transceivers, unlike the DS21Q55, which has
a JTAG controller-per-transceiver architecture.
APPLICATIONS Routers
Channel Service Units (CSUs)
Data Service Units (DSUs) Muxes
Switches
Channel Banks
T1/E1 Test Equipment
ORDERING INFORMATION FEATURES Four Independent Transceivers, Each Having
the Following Features:
��Complete T1 (DS1)/ISDN-PRI/J1
Transceiver Functionality
��Complete E1 (CEPT) PCM-30/ISDN-
PRI Transceiver Functionality
��Short- and Long-Haul Line Interface for
Clock/Data Recovery and Waveshaping
��CMI Coder/Decoder
��Crystal-Less Jitter Attenuator
��Fully Independent Transmit and Receive
Functionality
��Dual HDLC Controllers
��On-Chip Programmable BERT Generator and Detector
��Internal Software-Selectable Receive-
and Transmit-Side Termination Resistors
for 75Ω/100Ω/120Ω T1 and E1 Interfaces
��Dual Two-Frame Elastic-Store Slip
Buffers that can Connect to
Asynchronous Backplanes Up to
16.384MHz
��16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz Clock Output Synthesized to
Recovered Network Clock
��Programmable Output Clocks for
Fractional T1, E1, H0, and H12 Applications
��Interleaving PCM Bus Operation
��8-Bit Parallel Control Port, Multiplexed
or Nonmultiplexed, Intel or Motorola
��IEEE 1149.1 JTAG-Boundary Scan
��3.3V Supply with 5V Tolerant Inputs and
Outputs
��DS21455 Directly Replaces DS21Q55
��Signaling System 7 (SS7) Support
��RAI-CI, AIS-CI Support
DS21455/DS21458
Quad T1/E1/J1 Transceivers
DS21455/DS21458 Quad T1/E1/J1 Transceivers
DOCUMENT REVISION HISTORY DS21455/DS21458 Quad T1/E1/J1 Transceivers
TABLE OF CONTENTS
1. DESCRIPTION................................................................................................................................................9 1.1 STANDARDS......................................................................................................................10
2. FEATURE HIGHLIGHTS...............................................................................................................................11 2.1 GENERAL..........................................................................................................................11 2.2 LINE INTERFACE................................................................................................................11
2.3 CLOCK SYNTHESIZER........................................................................................................11 2.4 JITTER ATTENUATOR.........................................................................................................12
2.5 FRAMER/FORMATTER........................................................................................................12 2.6 SYSTEM INTERFACE...........................................................................................................13
2.7 HDLC CONTROLLERS.......................................................................................................13 2.8 TEST AND DIAGNOSTICS....................................................................................................13
2.9 EXTENDED SYSTEM INFORMATION BUS..............................................................................14 2.10 CONTROL PORT................................................................................................................14
3. BLOCK DIAGRAM........................................................................................................................................15
4. DS21455/DS21458 DELTA...........................................................................................................................17 4.1 PACKAGE..........................................................................................................................17 4.2 CONTROLLER INTERFACE...................................................................................................17
4.3 ESIB FUNCTION................................................................................................................17 4.4 FRAMER/LIU INTERIM SIGNALS..........................................................................................17
5. PIN FUNCTION DESCRIPTION....................................................................................................................20 5.1 TRANSMIT SIDE PINS.........................................................................................................20
5.2 RECEIVE SIDE PINS...........................................................................................................22 5.3 PARALLEL CONTROL PORT PINS........................................................................................24
5.4 EXTENDED SYSTEM INFORMATION BUS..............................................................................26 5.5 JTAG TEST ACCESS PORT PINS........................................................................................26
5.6 LINE INTERFACE PINS........................................................................................................27 5.7 SUPPLY PINS....................................................................................................................28
5.8 PIN DESCRIPTIONS............................................................................................................29 5.9 PACKAGES........................................................................................................................39
6. PARALLEL PORT.........................................................................................................................................41 6.1 REGISTER MAP.................................................................................................................41
7. SPECIAL PER-CHANNEL REGISTER OPERATION..................................................................................46
8. PROGRAMMING MODEL.............................................................................................................................48 8.1 POWER-UP SEQUENCE......................................................................................................49 8.1.1 Master Mode Register........................................................................................................49
8.2 INTERRUPT HANDLING.......................................................................................................50 8.3 STATUS REGISTERS..........................................................................................................50
8.4 INFORMATION REGISTERS..................................................................................................51 8.5 INTERRUPT INFORMATION REGISTERS................................................................................51
9. CLOCK MAP.................................................................................................................................................52
10. T1 FRAMER/FORMATTER CONTROL REGISTERS.................................................................................53 10.1 T1 CONTROL REGISTERS..................................................................................................53 10.2 T1 TRANSMIT TRANSPARENCY...........................................................................................58
10.3 AIS-CI AND RAI-CI GENERATION AND DETECTION.............................................................59 10.4 T1 RECEIVE-SIDE DIGITAL-MILLIWATT CODE GENERATION.................................................60
10.5 T1 INFORMATION REGISTER...............................................................................................62
11. E1 FRAMER/FORMATTER CONTROL REGISTERS.................................................................................64 11.1 E1 CONTROL REGISTERS..................................................................................................64 11.2 AUTOMATIC ALARM GENERATION.......................................................................................68
11.2.1 Auto AIS...........................................................................................................................68 11.2.2 Auto RAI...........................................................................................................................68
11.2.3 Auto E-Bit.........................................................................................................................68 11.2.4 G.706 CRC-4 Interworking............................................................................................68
DS21455/DS21458 Quad T1/E1/J1 Transceivers
13. I/O PIN CONFIGURATION OPTIONS..........................................................................................................78
14. LOOPBACK CONFIGURATIONS................................................................................................................80 14.1 PER-CHANNEL PAYLOAD LOOPBACK..................................................................................83
15. ERROR COUNT REGISTERS......................................................................................................................85 15.1 LINE CODE VIOLATION COUNT REGISTER (LCVCR)............................................................86
15.1.1 T1 Operation....................................................................................................................86 15.1.2 E1 Operation....................................................................................................................86
15.2 PATH CODE VIOLATION COUNT REGISTER (PCVCR)..........................................................88 15.2.1 T1 Operation....................................................................................................................88
15.2.2 E1 Operation....................................................................................................................88 15.3 FRAMES OUT OF SYNC COUNT REGISTER (FOSCR)..........................................................89
15.3.1 T1 Operation....................................................................................................................89 15.3.2 E1 Operation....................................................................................................................89
15.4 E-BIT COUNTER REGISTER (EBCR)...................................................................................90
16. DS0 MONITORING FUNCTION...................................................................................................................91 16.1 TRANSMIT DS0 MONITOR REGISTERS................................................................................91 16.2 RECEIVE DS0 MONITOR REGISTERS..................................................................................92
17. SIGNALING OPERATION............................................................................................................................93 17.1 RECEIVE SIGNALING..........................................................................................................93 17.1.1 Processor-Based Receive Signaling............................................................................94 17.1.2 Hardware-Based Receive Signaling............................................................................94
17.2 TRANSMIT SIGNALING......................................................................................................100
17.2.1 Processor-Based Transmit Signaling........................................................................100 17.2.2 Software Signaling Insertion Enable Registers, E1 CAS Mode.............................104
17.2.3 Software Signaling Insertion Enable Registers, T1 Mode......................................106
18. PER-CHANNEL IDLE CODE GENERATION............................................................................................108 18.1 IDLE CODE PROGRAMMING EXAMPLES.............................................................................109
19. CHANNEL BLOCKING REGISTERS.........................................................................................................113
20. ELASTIC STORES OPERATION...............................................................................................................116 20.1 RECEIVE SIDE.................................................................................................................119
20.1.1 T1 Mode.........................................................................................................................119 20.1.2 E1 Mode.........................................................................................................................119
20.2 TRANSMIT SIDE...............................................................................................................120 20.2.1 T1 Mode.........................................................................................................................120
20.2.2 E1 Mode.........................................................................................................................120 20.3 ELASTIC STORES INITIALIZATION......................................................................................120
20.4 MINIMUM-DELAY MODE...................................................................................................121
21. G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)................................................................122
22. T1 BIT ORIENTED CODE (BOC) CONTROLLER.....................................................................................123 22.1 TRANSMIT BOC...............................................................................................................123
22.2 RECEIVE BOC.................................................................................................................123
23. ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION (E1 ONLY)........................................127 23.1 HARDWARE SCHEME (METHOD 1)....................................................................................127 23.2 INTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME (METHOD 2).............................127
23.3 INTERNAL REGISTER SCHEME BASED ON CRC-4 MULTIFRAME (METHOD 3)......................130
24. HDLC CONTROLLERS..............................................................................................................................141 24.1 BASIC OPERATION DETAILS.............................................................................................141 24.2 HDLC CONFIGURATION...................................................................................................143
24.2.1 FIFO Control..................................................................................................................145 24.3 HDLC MAPPING..............................................................................................................146
24.3.1 Receive...........................................................................................................................146 24.3.2 Transmit.........................................................................................................................148
24.3.3 FIFO Information...........................................................................................................153 24.3.4 Receive Packet Bytes Available.................................................................................153
DS21455/DS21458 Quad T1/E1/J1 Transceivers
24.5.1 Receive Section............................................................................................................155
24.5.2 Transmit Section...........................................................................................................157 24.6 D4/SLC96 OPERATION.................................................................................................157
25. LINE INTERFACE UNIT (LIU)....................................................................................................................158 25.1 LIU OPERATION..............................................................................................................159
25.2 LIU RECEIVER................................................................................................................159 25.2.1 Receive Level Indicator................................................................................................160
25.2.2 Receive G.703 Section 10 Synchronization Signal.................................................160 25.2.3 Monitor Mode.................................................................................................................160
25.3 LIU TRANSMITTER...........................................................................................................161 25.3.1 Transmit Short-Circuit Detector/Limiter.....................................................................161
25.3.2 Transmit Open-Circuit Detector..................................................................................161 25.3.3 Transmit BPV Error Insertion......................................................................................162
25.3.4 Transmit G.703 Section 10 Synchronization Signal (E1 Mode).............................162
25.4 MCLK PRESCALER.........................................................................................................162 25.5 JITTER ATTENUATOR.......................................................................................................162
25.6 CMI (CODE MARK INVERSION) OPTION............................................................................163 25.7 LIU CONTROL REGISTERS...............................................................................................164
25.8 RECOMMENDED CIRCUITS................................................................................................173 25.9 COMPONENT SPECIFICATIONS..........................................................................................175
26. PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION......................................179
27. BERT FUNCTION.......................................................................................................................................186 27.1 BERT REGISTER DESCRIPTION.......................................................................................187 27.2 BERT REPETITIVE PATTERN SET.....................................................................................192
27.3 BERT BIT COUNTER.......................................................................................................193 27.4 BERT ERROR COUNTER.................................................................................................194
28. PAYLOAD ERROR INSERTION FUNCTION............................................................................................195 28.1 NUMBER OF ERROR REGISTERS......................................................................................197 28.1.1 Number Of Errors Left Register..................................................................................198
29. INTERLEAVED PCM BUS OPERATION...................................................................................................199 29.1 CHANNEL INTERLEAVE MODE...........................................................................................199 29.2 FRAME INTERLEAVE MODE...............................................................................................199
30. EXTENDED SYSTEM INFORMATION BUS (ESIB)..................................................................................202
31. PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER.....................................................................208
32. FRACTIONAL T1/E1 SUPPORT................................................................................................................209
33. USER-PROGRAMMABLE OUTPUT PINS................................................................................................210
34. TRANSMIT FLOW DIAGRAMS..................................................................................................................211
35. JTAG-BOUNDARY-SCAN ARCHITECTURE AND TEST-ACCESS PORT.............................................216 35.1 INSTRUCTION REGISTER..................................................................................................220 35.2 TEST REGISTERS.............................................................................................................222
35.3 BOUNDARY SCAN REGISTER............................................................................................222 35.4 BYPASS REGISTER..........................................................................................................222
35.5 IDENTIFICATION REGISTER...............................................................................................222
36. FUNCTIONAL TIMING DIAGRAMS...........................................................................................................228 36.1 T1 MODE........................................................................................................................228 36.2 E1 MODE........................................................................................................................238
37. OPERATING PARAMETERS.....................................................................................................................251
38. AC TIMING PARAMETERS AND DIAGRAMS..........................................................................................253 38.1 MULTIPLEXED BUS AC CHARACTERISTICS........................................................................253 38.2 NONMULTIPLEXED BUS AC CHARACTERISTICS.................................................................256
38.3 RECEIVE SIDE AC CHARACTERISTICS..............................................................................259 38.4 TRANSMIT AC CHARACTERISTICS....................................................................................265
39. PACKAGE INFORMATION........................................................................................................................269
