DS21448L ,3.3V E1/T1/J1 Quad Line Interfaceapplications). Intel or Motorola Detects/Generates Blue (AIS) Alarms The DS21448 has diagnostic ..
DS21448L+ ,3.3V E1/T1/J1 Quad Line InterfacePIN DESCRIPTION .....7 3. DETAILED DESCRIPTION 13 3.1 DS21448 AND DS21Q348 DIFFERENCES.....13 4. PO ..
DS21448L+W ,3.3V E1/T1/J1 Quad Line InterfaceAPPLICATIONS CSU Line Build-Outs for T1 Integrated Multiservice Access Platforms AMI, HDB3, and B ..
DS21448LN ,3.3V E1/T1/J1 Quad Line InterfaceBlock Diagram.. 5 Figure 1-2. Receive Logic Detail.. 6 Figure 1-3. Transmit Logic Detail. 6 Figure ..
DS21448LN ,3.3V E1/T1/J1 Quad Line InterfacePIN DESCRIPTION .. 7 3. DETAILED DESCRIPTION........13 3.1 DS21448 AND DS21Q348 DIFFERENCES ...13 4 ..
DS21448LN+ ,3.3V E1/T1/J1 Quad Line InterfaceFEATURES The DS21448 is a quad-port E1 or T1 line interface Four Complete E1, T1, or J1 LIUs unit ..
DS21448L-DS21448LN
3.3V E1/T1/J1 Quad Line Interface
GENERAL DESCRIPTION The DS21448 is a quad-port E1 or T1 line interface
unit (LIU) for short-haul and long-haul applications. It incorporates four independent transmitters and four
independent receivers in a single 144-pin PBGA or 128-pin LQFP package.
The transmit drivers generate the necessary G.703
E1 waveshapes in 75� or 120� applications and the DSX-1 or CSU line build-outs of 0dB, -7.5dB, -15dB,
and -22.5dB for T1 applications.
The DS21448 has a usable receiver sensitivity of
0 to -43dB for E1 applications and 0 to -36dB for T1 that allows it to operate on 0.63mm (22AWG) cables
up to 2.5km (E1) and 6000ft (T1) in length. The user has the option to use internal receive termination,
software selectable for 75�, 100�, and 120� applications, or external termination.
The on-board crystal-less jitter attenuator can be placed in either the transmit or the receive data path,
and requires only a 2.048MHz MCLK for both E1 and T1 applications (with the option of using a 1.544MHz
MCLK in T1 applications).
The DS21448 has diagnostic capabilities such as
loopbacks and PRBS pattern generation and detection. 16-bit loop-up and loop-down codes can
be generated and detected. A single input pin can power down all transmitters to allow the
implementation of hitless protection switching (HPS) for 1+1 redundancy without the use of relays.
The device can be controlled through an 8-bit parallel port (muxed or nonmuxed) or a serial port, and it can
be used in hardware mode. A standard boundary scan interface supports board-level testing.
APPLICATIONS Integrated Multiservice Access Platforms
T1/E1 Cross-Connects, Multiplexers, and Channel Banks
Central-Office Switches and PBX Interfaces T1/E1 LAN/WAN Routers Wireless Base Stations
FEATURES Four Complete E1, T1, or J1 LIUs Supports Long- and Short-Haul Trunks Internal Software-Selectable Receive-Side
Termination for 75�/100�/120� 3.3V Power Supply 32-Bit or 128-Bit Crystal-Less Jitter Attenuator Requires Only a 2.048MHz Master Clock for E1
and T1, with the Option to Use 1.544MHz for T1 Generates the Appropriate Line Build-Outs With and Without Return Loss for E1, and DSX-1 and
CSU Line Build-Outs for T1 AMI, HDB3, and B8ZS Encoding/Decoding 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz Clock Output Synthesized to Recovered Clock Programmable Monitor Mode for Receiver Loopbacks and PRBS Pattern Generation/ Detection with Output for Received Errors Generates/Detects In-Band Loop Codes, 1 to 16
Bits, Including CSU Loop Codes ��8-Bit Parallel or Serial Interface with Optional
Hardware Mode Muxed and Nonmuxed Parallel Bus Supports Intel or Motorola Detects/Generates Blue (AIS) Alarms NRZ/Bipolar Interface for Tx/Rx Data I/O Transmit Open-Circuit Detection Receive Carrier Loss (RCL) Indication (G.775) High-Z State for TTIP and TRING 50mARMS Transmit Current Limiter JTAG Boundary Scan Test Port per IEEE 1149.1 Meets Latest E1 and T1 Specifications Including ANSI.403-1999, ANSI T1.408, AT&T TR 62411,
ITU G.703, G.704, G.706, G.736, G.775, G.823, I.431, O.151, O.161, ETSI ETS 300 166, JTG.703, JTI.431, TBR12, TBR13, and CTR4
ORDERING INFORMATION Pin Configurations appear in Section 11.
DS21448
3.3V E1/T1/J1 Quad Line Interface
DS21448 3.3V T1/E1/J1 Quad Line Interface
TABLE OF CONTENTS
1. BLOCK DIAGRAMS......................................................................................................................5
2. PIN DESCRIPTION.......................................................................................................................7
3. DETAILED DESCRIPTION...........................................................................................................13 3.1 DS21448 AND DS21Q348 DIFFERENCES....................................................................................13
4. PORT OPERATION......................................................................................................................13 4.1 HARDWARE MODE.......................................................................................................................13
4.2 SERIAL PORT OPERATION............................................................................................................15
4.3 PARALLEL PORT OPERATION.......................................................................................................17
4.3.1 Device Power-Up and Reset.................................................................................................................17
4.3.2 Register Map.........................................................................................................................................18
4.3.3 Control Registers..................................................................................................................................19
5. STATUS REGISTERS..................................................................................................................23
6. DIAGNOSTICS ............................................................................................................................27 6.1 IN-BAND LOOP-CODE GENERATION AND DETECTION.....................................................................27
6.2 LOOPBACKS................................................................................................................................31
6.2.1 Remote Loopback (RLB)......................................................................................................................31
6.2.2 Local Loopback (LLB)...........................................................................................................................31
6.2.3 Analog Loopback (LLB)........................................................................................................................31
6.2.4 Dual Loopback (DLB)............................................................................................................................31
6.3 PRBS GENERATION AND DETECTION...........................................................................................31
6.4 ERROR COUNTER........................................................................................................................31
6.5 ERROR COUNTER UPDATE...........................................................................................................32
6.6 ERROR INSERTION.......................................................................................................................32
7. ANALOG INTERFACE.................................................................................................................33 7.1 RECEIVER...................................................................................................................................33
7.2 TRANSMITTER.............................................................................................................................33
7.3 JITTER ATTENUATOR...................................................................................................................34
7.4 G.703 SYNCHRONIZATION SIGNAL...............................................................................................34
8. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT..................................43 8.1 JTAG TAP CONTROLLER STATE MACHINE...................................................................................43
8.2 INSTRUCTION REGISTER..............................................................................................................45
8.3 TEST REGISTERS........................................................................................................................46
9. OPERATING PARAMETERS.......................................................................................................48
10. AC TIMING PARAMETERS AND DIAGRAMS............................................................................49
11. PIN CONFIGURATIONS..............................................................................................................56 11.1 144-PIN BGA..........................................................................................................................56
11.2 128-PIN LQFP.........................................................................................................................57
12. PACKAGE INFORMATION..........................................................................................................58
13. THERMAL INFORMATION..........................................................................................................60
DS21448 3.3V T1/E1/J1 Quad Line Interface
LIST OF FIGURES Figure 1-1. Block Diagram.......................................................................................................................5
Figure 1-2. Receive Logic Detail..............................................................................................................6
Figure 1-3. Transmit Logic Detail.............................................................................................................6
Figure 4-1. Serial Port Operation for Read Access (R = 1) Mode 1........................................................15
Figure 4-2. Serial Port Operation for Read Access (R = 1) Mode 2........................................................16
Figure 4-3. Serial Port Operation for Read Access (R = 1) Mode 3........................................................16
Figure 4-4. Serial Port Operation for Read Access (R = 1) Mode 4........................................................16
Figure 4-5. Serial Port Operation for Write Access (R = 0) Modes 1 and 2.............................................17
Figure 4-6. Serial Port Operation for Write Access (R = 0) Modes 3 and 4.............................................17
Figure 7-1. Basic Interface......................................................................................................................36
Figure 7-2. Protected Interface Using Internal Receive Termination.......................................................37
Figure 7-3. Protected Interface Using External Receive Termination......................................................38
Figure 7-4. Dual Connector-Protected Interface Using Receive Termination..........................................39
Figure 8-5. E1 Transmit Pulse Template................................................................................................40
Figure 8-6. T1 Transmit Pulse Template.................................................................................................41
Figure 7-7. Jitter Tolerance.....................................................................................................................42
Figure 7-8. Jitter Attenuation..................................................................................................................42
Figure 8-1. JTAG Block Diagram............................................................................................................43
Figure 8-2. TAP Controller State Diagram..............................................................................................44
Figure 10-1. Intel Bus Read Timing (PBTS = 0, BIS0 = 0)......................................................................49
Figure 10-2. Intel Bus Write Timing (PBTS = 0, BIS0 = 0)......................................................................50
Figure 10-3. Motorola Bus Timing (PBTS = 1, BIS0 = 0)........................................................................50
Figure 10-4. Intel Bus Read Timing (PBTS = 0, BIS0 = 1)......................................................................51
Figure 10-5. Intel Bus Write Timing (PBTS = 0, BIS0 = 1)......................................................................52
Figure 10-6. Motorola Bus Read Timing (PBTS = 1, BIS0 = 1)...............................................................52
Figure 10-7. Motorola Bus Write Timing (PBTS = 1, BIS0 = 1)...............................................................52
Figure 10-8. Serial Bus Timing (BIS1 = 1, BIS0 = 0)...............................................................................53
Figure 10-9. Receive-Side Timing..........................................................................................................54
Figure 10-10. Transmit-Side Timing.......................................................................................................55
DS21448 3.3V T1/E1/J1 Quad Line Interface
LIST OF TABLES Table 2-A. Bus Interface Selection..........................................................................................................7
Table 2-B. Pin Assignments....................................................................................................................7
Table 2-C. Parallel Interface Mode Pin Description.................................................................................9
Table 2-D. Serial Interface Mode Pin Description...................................................................................10
Table 2-E. Hardware Interface Mode Pin Description.............................................................................11
Table 3-A. DS21448 vs. DS21Q348 Pin Differences..............................................................................13
Table 4-A. Loopback Control in Hardware Mode....................................................................................14
Table 4-B. Transmit Data Control in Hardware Mode.............................................................................14
Table 4-C. Receive Sensitivity Settings in Hardware Mode....................................................................14
Table 4-D. Monitor Gain Settings in Hardware Mode..............................................................................14
Table 4-E. Internal Rx Termination Select in Hardware Mode................................................................14
Table 4-F. MCLK Selection in Hardware Mode.......................................................................................14
Table 4-G. Parallel Port Mode Selection.................................................................................................18
Table 4-H. Register Map........................................................................................................................18
Table 4-I. Receive Sensitivity Settings....................................................................................................22
Table 4-J. Backplane Clock Select.........................................................................................................22
Table 4-K. Monitor Gain Settings............................................................................................................22
Table 4-L. Internal Rx Termination Select...............................................................................................22
Table 5-A. Received Alarm Criteria........................................................................................................25
Table 5-B. Receive Level Indication.......................................................................................................27
Table 6-A. Transmit Code Length...........................................................................................................29
Table 6-B. Receive Code Length............................................................................................................29
Table 6-C. Definition of Received Errors.................................................................................................32
Table 6-D. Function of ECRS Bits and RNEG Pin..................................................................................32
Table 7-A. Line Build-Out Select for E1 in Register CCR4 (ETS = 0)......................................................34
Table 7-B. Line Build-Out Select for T1 in Register CCR4 (ETS = 1)......................................................34
Table 7-C. Line Build-Out Select for E1 in Register CCR4 (ETS = 0) Using Alternate Transformer
Configuration...................................................................................................................................35
Table 7-D. Transformer Specifications (3.3V Operation)........................................................................35
Table 8-A. Instruction Codes for IEEE 1149.1 Architecture.....................................................................45
Table 8-B. ID Code Structure.................................................................................................................46
Table 8-C. Device ID Codes...................................................................................................................46
Table 8-D. Boundary Scan Control Bits..................................................................................................47
Table 10-A. AC CharacteristicsMultiplexed Parallel Port (BIS0 = 0)....................................................49
Table 10-B. AC CharacteristicsNonmultiplexed Parallel Port (BIS0 = 1).............................................51
Table 10-C. AC CharacteristicsSerial Port (BIS1 = 1, BIS0 = 0)..........................................................53
Table 10-D. AC CharacteristicsReceive Side......................................................................................54
Table 10-E. AC CharacteristicsTransmit Side.....................................................................................55
Table 13-A. Thermal CharacteristicsBGA...........................................................................................60
Table 13-B. Theta-JA (�JA) vs. AirflowBGA..........................................................................................60
Table 13-C. Thermal CharacteristicsLQFP..........................................................................................60
Table 13-D. Theta-JA (�JA) vs. AirflowLQFP........................................................................................60
DS21448 3.3V T1/E1/J1 Quad Line Interface
1. BLOCK DIAGRAMS
Figure 1-1. Block Diagram
