DS21448DK ,3.3V E1/T1/J1 Line Interface Design Kit Daughter CardFEATURES The DS21448DK is an easy-to-use evaluation board Demonstrates Key Functions of the DS214 ..
DS21448L ,3.3V E1/T1/J1 Quad Line Interfaceapplications). Intel or Motorola Detects/Generates Blue (AIS) Alarms The DS21448 has diagnostic ..
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DS21448DK
3.3V E1/T1/J1 Line Interface Design Kit Daughter Card
GENERAL DESCRIPTION The DS21448DK is an easy-to-use evaluation board
for the DS21448 quad E1/T1/J1 LIU. It is intended to be used as a daughter card with the DK101
motherboard or the DK2000 motherboard. A surface-mounted DS21448 and careful layout of the analog
signal traces provide maximum signal integrity to demonstrate the transmit and receive capabilities of
the DS21448. The DK101/DK2000 motherboard and Dallas’ ChipView software give point-and-click
access to configuration and status registers from a
Windows�-based PC. On-board LEDs indicate
interrupt status and receive-carrier loss for all four ports. The evaluation board provides both RJ45 and
BNC connectors for the line-side transmit and receive differential pairs on all four ports.
Each DS21448DK is shipped with a free DK101 motherboard. For complex applications, the DK2000
high-performance demo kit motherboard can be purchased separately.
Windows is a registered trademark of Microsoft Corp.
ORDERING INFORMATION
FEATURES ��Demonstrates Key Functions of the DS21448
Quad LIU ��Includes Transformers, BNC, and RJ45
Network Connectors and Termination Passives ��Compatible with DK101 and DK2000 Demo Kit
Motherboards ��DK101/DK2000 and ChipView Software
Provide Point-and-Click Access to the DS21448 Register Set ��Memory-Mapped FPGA Provides Flexible
Clock and Signal Routing ��LEDs for Receive-Carrier Loss and Interrupt
��Easy-to-Read Silk-Screen Labels Identify the
Signals Associated with All Connectors,
Jumpers, and LEDs
DESIGN KIT CONTENTS DS21448DK Design Kit Daughter Card
DK101 Demo Kit Motherboard CD-ROM
ChipView Software DS21448DK Data Sheet
DS21448 Data Sheet DK101 Data Sheet
DS21448 Errata Sheet
3.3V E1/T1/J1 Line Interface Design Kit
Daughter Card
DS21448DK 3.3V E1/T1/J1 Line Interface Design Kit
COMPONENT LIST
BASIC OPERATION
Hardware Configuration Using the DK101 Processor Board Connect the daughter card to the DK101 processor board. Supply 3.3V to the banana-plug receptacles marked GND and VCC_3.3V. (The external 5V connector is unused. Additionally, the TIM 5V supply headers are unused.) All processor-board DIP switch settings should be in the ON position with the exception of the flash-programming switch, which should be OFF. From the Programs menu, launch the host application named ChipView.EXE. Run the ChipView application. If
the default installation options were used, click the Start button on the Windows toolbar and select Programs �
ChipView � ChipView.
Using the DK2000 Processor Board Connect the daughter card to the DK2000 processor board. Connect J1 to the power supply that is delivered with the kit. Alternately, a PC power supply can be connected
to connector J2. From the Programs menu, launch the host application named ChipView.EXE. Run the ChipView application. If
the default installation options were used, click the Start button on the Windows toolbar and select Programs �
ChipView � ChipView.
DS21448DK 3.3V E1/T1/J1 Line Interface Design Kit
General Upon power-up, the RCL LEDs are lit, and the INT LED is off. After power-up, the RCL LEDs extinguish upon external loopback. Due to the dual winding transformer, only the 120� line build-out (LBO) configuration setting is needed to cover
both 75� E1 and 120� E1.
Miscellaneous Clock frequencies are provided by a register-mapped CPLD, which is on the DS21448 daughter card. The definition file for this CPLD is named DS21448DK02A0_CPLD.def. See the CPLD Register Map
definitions.
Quick Setup (Register View) The PC loads the program, offering a choice between DEMO MODE, REGISTER VIEW, and TERMINAL
MODE. Select Register View. The program requests a definition file. Select DS21448DK02A0_CPLD.DEF. The Register View Screen appears, showing the register names, acronyms, and values. Note the CPLD def file contains a link such that the def file for the DS21448 is also loaded. Selection among the def files is
accomplished using the drop-down box on the right-hand side of the program window. From the drop-down box, select the DS21448 def file and configure register CCR3 of ports 1 through 4 with a
90h. The device begins transmitting a pseudo-random bit sequence. Upon external loopback, the RCL LED extinguishes, denoting that the device has found a carrier and has successfully decoded the
pseudorandom bit sequence. For more advanced configurations, please refer to the DS21448 data sheet.
DS21448DK 3.3V E1/T1/J1 Line Interface Design Kit
ADDRESS MAP The DK101 daughter card address space begins at 0x81000000.
The DK2000 daughter card address space begins at: 0x30000000 for slot 0
0x40000000 for slot 1 0x50000000 for slot 2
0x60000000 for slot 3 All offsets in the Daughter Card Address Map table are relative to the beginning of the Daughter Card address
space.
Daughter Card Address Map Registers in the CPLD can be easily modified using ChipView, a host-based user-interface software with the
definition file named DS21448DK02A0_CPLD.DEF. This file is included as part of the design kit documentation download (accessed through the DS21448s quick view data sheet) or the included CD-ROM. The definition file for
the LIU is named DS21448.def.
CPLD Register Map
ID Registers
DS21448DK 3.3V E1/T1/J1 Line Interface Design Kit
Control Registers The control registers are used set the clock frequency on the MCLK and TCLK pins. Options are 1.544MHz,
2.048MHz, external source (through AUX CLK BNC), and tri-state.
MCLK_SRC: MCLK SOURCE (OFFSET = 0x0011) INITIAL VALUE = 0x1 (MSB) (LSB)
TCLK1_SRC: TCLK SOURCE (OFFSET = 0x0012) INITIAL VALUE = 0x1
(MSB) (LSB)
TCLK2_SRC: TCLK SOURCE (OFFSET = 0x0013) INITIAL VALUE = 0x1
(MSB) (LSB)
TCLK3_SRC: TCLK SOURCE (OFFSET = 0x0014) INITIAL VALUE = 0x1 (MSB) (LSB)
