DS2143Q Fast Delivery |IC PHOENIX CO.,LIMITED

DS2143Q ,E1 ControllerFEATURES PIN ASSIGNMENT E1/ISDN-PRI framing transceiver1 VDDTCLK 40 Frames to CAS, CCS, and CRC4 ..
DS2143QN+ ,E1 ControllerapplicationsAD4 10 31 LI_CS Onboard Sa data link support circuitryAD5 LI_CLK11 3012 29 FEBE E-Bit ..
DS21448 ,3.3V E1/T1/J1 Quad Line InterfaceAPPLICATIONS CSU Line Build-Outs for T1 Integrated Multiservice Access Platforms AMI, HDB3, and B ..
DS21448DK ,3.3V E1/T1/J1 Line Interface Design Kit Daughter CardFEATURES The DS21448DK is an easy-to-use evaluation board Demonstrates Key Functions of the DS214 ..
DS21448L ,3.3V E1/T1/J1 Quad Line Interfaceapplications). Intel or Motorola Detects/Generates Blue (AIS) Alarms The DS21448 has diagnostic ..
DS21448L+ ,3.3V E1/T1/J1 Quad Line InterfacePIN DESCRIPTION .....7 3. DETAILED DESCRIPTION 13 3.1 DS21448 AND DS21Q348 DIFFERENCES.....13 4. PO ..

DS2143Q
E1 Controller
FEATURESE1/ISDN-PRI framing transceiverFrames to CAS, CCS, and CRC4 formatsParallel control portOnboard two frame elastic store slip bufferExtracts and inserts CAS signaling bitsProgrammable output clocks for fractional E1
links, DS0 loopbacks, and drop and insert
applicationsOnboard Sa data link support circuitryFEBE E-Bit detection, counting and
generationPin-compatible with DS2141A T1 Controller5V supply; low power (50 mW) CMOSAvailable in 40-pin DIP and 44-pin PLCC
(DS2143Q)
PIN ASSIGNMENT
DESCRIPTION
The DS2143 is a comprehensive, software-driven E1 framer. It is meant to act as a slave or coprocessor to
a microcontroller or microprocessor. Quick access via the parallel control port allows a single micro to
handle many E1 lines. The DS2143 is very flexible and can be configured into numerous orientations via
DS2143/DS2143Q
E1 Controller
www.dalsemi.com
40-Pin DIP (600-mil)
TCHCLK
TNEG
AD1
AD2
AD3
AD4
AD5
AD6
BTS
AD7
VDD
TLCLK
INT1
INT2
RLOS/LOTC
TCHBLK
RCHBLK
LI_CS
LI_CLK
LI_SDI
RNEG
SYSCLK
TSER
TPOS
AD0
TCLK
TSYNC
TLINK
RD(DS)
ALE(AS)
WR(R/W)
VSS
RLINK
RPOS
RSYNC
RSER
RCHCLK
RLCLK
RCLK
AD0
AD1AD2
AD3
AD4
AD5
RLOS/LOTC
TCHBLK
RCHBLK
LI_CS
LI_CLK
LI_SDI
AD6NC
TPOST
CHCLK
TSERTC
TSYNCS
WR(R/
RLI
RLCL
6 5 4 3 2 1 44 43 42 41 40
18 19 20 21 22 23 24 25 26 27 28
AD7
BTS
RD(DS)
TLIN
TLC
RCL
RCHCL
SYSCLK
RNEG
RPOS
44-PIN PLCC
DS2143/DS2143Q
can access. These internal registers are used to configure the device and obtain information from the E1
link. The device fully meets al l of the latest E1 specifications, including CCITT G.704, G.706, and
G.732.
1.0 INTRODUCTION
The DS2143 E1 Controller has four main sections: the receive side, the transmit side, the line interface
controller, and the parallel control port. See the Block Diagram. On the receive side, the device will
clock in the serial E1 stream via the RPOS and RNEG pins. The synchronizer will locate the frame and
multiframe patterns and establish their respective positions. This information will be used by the rest of
the receive side circuitry.
The DS2143 is an “off-line” framer, which means that all of the E1 serial stream that goes into the device
will come out of it unchanged. Once the E1 data has been framed to, the signaling data can be extracted.
The two-frame elastic store can either be enabled or bypassed.
The transmit side clocks in the unframed E1 stream at TSER and add in the framing pattern and the
signaling. The line interface control port will update line interface devices that contain a serial port. The
parallel control port contains a multiplexed address and data structure which can be connected to either a
microcontroller or microprocessor.
Reader’s Note:
This data sheet assumes a particular nomenclature of the E1 operating environment. There are 32 8-bit
timeslots in an E1 systems which are number 0 to 31. Timeslot 0 is transmitted first and received first.
These 32 timeslots are also referred to as channels with a numbering scheme of 1 to 32. Timeslot 0 is
identical to channel 1, timeslot 1 is identical to channel 2, and so on. Each timeslot (or channel) is made
up of 8 bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is
the LSB and is transmitted last. Throughout this data sheet, the following abbreviations will be used:
FAS Frame Alignment Signal
CRC4 Cyclical Redundancy Check
CAS Channel Associated Signaling
CCS Common Channel Signaling
MF Multiframe
Sa Additional bits
Si International bits
E-bit CRC4 Error Bits
DS2143/DS2143Q
DS2143 FEATURESParallel control portOnboard two-frame elastic storeCAS signaling bit extraction and insertionFully independent transmit and receive sectionsFull alarm detectionFull access to Si and Sa bitsLoss of transmit clock detectionHDB3 coder/decoderFull transmit transparencyLarge error countersIndividual bit-by-bit Sa data link support circuitryProgrammable output clocksFrame sync generationLocal loopback capabilityAutomatic CRC4 E-bit supportLoss of receive clock detectionG.802 E1 to T1 mapping support
DS2143 BLOCK DIAGRAM
DS2143/DS2143Q
PIN DESCRIPTION Table 1
PINSYMBOLTYPEDESCRIPTION
1TCLKITransmit Clock. 2.048 MHz primary clock. A clock must be
applied at the TCLK pin for the parallel port to operate properly.
2TSERITransmit Serial Data. Transmit NRZ serial data, sampled on the
falling edge of TCLK.
3TCHCLKOTransmit Channel Clock. 256 kHz clock which pulses high during
the LSB of each channel. Useful for parallel-to-serial conversion of
channel data. See Section 13 for timing details.
TPOS
TNEGTransmit Bipolar Data. Updated on rising edge of TCLK. For
optical links, can be programmed to output NRZ data.
6-13AD0-AD7I/OAddress/Data Bus. An 8-bit multiplexed address/data bus.BTSIBus Type Select. Strap high to select Motorola bus timing; strap
low to select Intel bus timing. This pin controls the function of(DS), ALE(AS), and WR(R/W) pins. If BTS=1, then these pins
assume the function listed in parentheses ().RD(DS)IRead Input (Data Strobe).CSIChip Select. Must be low to read or write the port.ALE(AS)IAddress Latch Enable (Address Strobe). A positive-going edge
serves to demultiplex the bus.WR(R/W)IWrite Input (Read/Write).RLINKOReceive Link Data. Outputs Sa bits. See Section 13 for timing
details.VSS-Signal Ground. 0.0 volts.RLCLKOReceive Link Clock. 4 kHz to 20 kHz demand clock for the
RLINK output. Controlled by RCR2. See Section 13 for timing
details.RCLKIReceive Clock. 2.048 MHz primary clock. A clock must be applied
at the RCLK pin for the parallel port to operate properly.RCHCLKOReceive Channel Clock. 256 kHz clock which pulses high during
the LSB of each channel. Useful for serial to parallel conversion of
channel data. See Section 13 for timing details.RSEROReceive Serial Data. Received NRZ serial data, updated on rising
edges of RCLK.RSYNCI/OReceive Sync. An extracted pulse, one RCLK wide, is output at this
pin which identifies either frame (RCR1.6=0) or multiframe
boundaries (RCR1.6=1). If the elastic store is enabled via the
RCR2.1, then this pin can be enabled to be an input via RCR1.5 at
which a frame boundary pulse is applied. See Section 13 for timing
details.
RPOS
RNEGReceive Bipolar Data Inputs. Sampled on falling edge of RCLK.
Tie together to receive NRZ data and disable BPV monitoring
circuitry.SYSCLKISystem Clock. 1.544 MHz or 2.048 MHz clock. Only used when
the elastic store function is enabled via the RCR2.1. Should be tied
low in applications that do not use the elastic store.
DS2143/DS2143Q
PINSYMBOLTYPEDESCRIPTIONLI_SDIOSerial Port Data for the Line Interface. Connects directly to the
SDI input pin on the line interface. See Sections 12 and 13 for
timing details.LI_CLKOSerial Port Clock for the Line Interface. Connects directly to the
SCLK input pin on the line interface. See Sections 12 and 13 for
timing details.LI_CSOSerial Port Chip Select for the Line Interface. Connects directly
to the CS input pin on the line interface. See Sections 12 and 13 for
timing details.
RCHBLK
TCHBLKReceive/Transmit Channel Block. A user programmable output
that can be forced high or low during any of the 32 E1 channels.
Useful for blocking clocks to a serial UART or LAPD controller in
applications where not all E1 channels are used such as Fractional
E1 or ISDN-PRI. Also useful for locating individual channels in
drop-and-insert applications. See Sections 9 and 13 for details.RLOS/LOTCOReceive Loss of Sync/Loss of Transmit Clock. A dual function
output. If TCR2.0=0, then this pin will toggle high when the
synchronizer is searching for the E1 frame and multiframe. If
TCR2.0=1, then this pin will toggle high if the TCLK pin has not
toggled for 5 μs.INT2OReceive Alarm Interrupt 2. Flags host controller during conditions
defined in Status Register 2. Active low, open drain output.INT1OReceive Alarm Interrupt 1. Flags host controller during alarm
conditions defined in Status Register 1. Active low, open drain
output.TLCLKOTransmit Link Clock. 4 kHz to 20 kHz demand clock for the
TLINK input. Controlled by TCR2. See Section 13 for timing
details.TLINKITransmit Link Data. If enabled, this pin will be sampled on the
falling edge of TCLK to insert Sa bits. See Section 13 for timing
details.TSYNCI/OTransmit Sync. A pulse at this pin will establish either frame or
CAS multiframe boundaries for the DS2143. Via TCR1.1, the
DS2143 can be programmed to output either a frame or multiframe
pulse at this pin. See Section 13 for timing details.VDD-Positive Supply. 5.0 volts.
DS2143/DS2143Q
DS2143 REGISTER MAP
ADDRESS
A7 to A0
HEXR/WREGISTER
NAME
0000000000RBipolar
Violation Count
Register 1.
0000000101RBipolar
Violation Count
Register 2.
0000001002RCRC4 Count
Register 1.
0000001103RCRC4 Count
Register 2.
0000010004RE-Bit Count
Register 1.
0000010105RE-Bit Count
Register 2.
0000011006R/WStatus Register
0000011107R/WStatus Register
0000100008R/WReceive
Information
Register.
000111101ERSynchronizer
Status Register.
0001011016R/WInterrupt Mask
Register 1.
0001011117R/WInterrupt Mask
Register 2.
0001000010R/WReceive Control
Register 1.
0001000111R/WReceive Control
Register 2.
0001001012R/WTransmit Control
Register 1.
0001001113R/WTransmit Control
Register 2.
0001010014R/WCommon
Control Register.
0001010115R/WTest Register.
0001100018WLI Control
Register Byte 1.
0001100119WLI Control
Register Byte 2.
0010000020R/WTransmit Align
Frame Register.
ADDRESS
A7 to A0
HEXR/WREGISTER
NAME
0010000121R/WTransmit Non-
Align Frame
Register.
001011112FRReceive Align
Frame Register.
000111111FRReceive Non-
Align Frame
Register.
0010001022R/WTransmit
Channel
Blocking
Register 1.
0010001123R/WTransmit
Channel
Blocking
Register 2.
0010010024R/WTransmit
Channel
Blocking
Register 3.
0010010125R/WTransmit
Channel
Blocking
Register 4.
0010011026R/WTransmit Idle
Register 1.
0010011127R/WTransmit Idle
Register 2.
0010100028R/WTransmit Idle
Register 3.
0010100129R/WTransmit Idle
Register 4.
001010102AR/WTransmit Idle
Definition
Register.
001010112BR/WReceive Channel
Blocking
Register 1.
001011002CR/WReceive Channel
Blocking
Register 2.
001011012DR/WReceive Channel
Blocking
Register 3.
DS2143/DS2143Q
ADDRESS
A7 to A0
HEXR/WREGISTER
NAME
001011102ER/WReceive Channel
Blocking
Register 4.
0011000030RReceive
Signaling
Register 1.
0011000131RReceive
Signaling
Register 2.
0011001032RReceive
Signaling
Register 3.
0011001133RReceive
Signaling
Register 4.
0011010034RReceive
Signaling
Register 5.
0011010135RReceive
Signaling
Register 6.
0011011036RReceive
Signaling
Register 7.
0011011137RReceive
Signaling
Register 8.
0011100038RReceive
Signaling
Register 9.
0011100139RReceive
Signaling
Register 10.
001110103ARReceive
Signaling
Register 11.
001110113BRReceive
Signaling
Register 12.
001111003CRReceive
Signaling
Register 13.
001111013DRReceive
Signaling
ADDRESS
A7 to A0
HEXR/WREGISTER
NAME
001111103ERReceive
Signaling
Register 15.
001111113FRReceive
Signaling
Register 16.
0100000040R/WTransmit
Signaling
Register 1.
0100000141R/WTransmit
Signaling
Register 2.
0100001042R/WTransmit
Signaling
Register 3.
0100001143R/WTransmit
Signaling
Register 4.
0100010044R/WTransmit
Signaling
Register 5.
0100010145R/WTransmit
Signaling
Register 6.
0100011046R/WTransmit
Signaling
Register 7.
0100011147R/WTransmit
Signaling
Register 8.
0100100048R/WTransmit
Signaling
Register 9.
0100100149R/WTransmit
Signaling
Register 10.
010010104AR/WTransmit
Signaling
Register 11.
010010114BR/WTransmit
Signaling
Register 12.
010011004CR/WTransmit
Signaling
DS2143/DS2143Q
ADDRESS
A7 to A0
HEXR/WREGISTER
NAME
010011014DR/WTransmit
Signaling
Register 14.
010011104ER/WTransmit
Signaling
Register 15.
010011114FR/WTransmit
Signaling
Register 16.
Note: All values indicated within the Address
column are hexadecimal.
2.0 PARALLEL PORT
The DS2143 is controlled via a multiplexed bidirectional address/data bus by an external microcontroller
or microprocessor. The DS2143 can operate with either Intel or Motorola bus timing configurations. If
the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected. All
Motorola bus signals are listed in parentheses (). See the timing diagrams in the AC Electrical
Characteristics for more details. The multiplexed bus on the DS2143 saves pins because the address
information and data information share the same signal paths. The addresses are presented to the pins in
the first portion of the bus cycle and data will be transferred on the pins during second portion of the bus
cycle. Addresses must be valid prior to the falling edge of ALE(AS), at which time the DS2143 latches
the address from the AD0 to AD7 pins. Valid write data must be present and held stable during the later
portion of the DS or WR pulses. In a read cycle, the DS2143 outputs a byte of data during the latter
portion of the DS or RD pulses. The read cycle is terminated and the bus returns to a high impedance
state as RD transitions high in Intel timing or as DS transitions low in Motorola timing.
3.0 CONTROL AND TEST REGISTERS
The operation of the DS2143 is configured via a set of five registers. Typically, the control registers are
only accessed when the system is first powered up. Once the DS2143 has been initialized, the control
registers will only need to be accessed when there is a change in the system configuration. There are two
Receive Control Registers (RCR1 and RCR2), two Transmit Control Registers (TCR1 and TCR2), and a
Common Control Register (CCR). Each of the five registers is described in this section.
The Test Register at address 15 hex is used by the factory in testing the DS2143. On power-up, the Test
Register should be set to 00 hex in order for the DS2143 to operate properly.
DS2143/DS2143Q
RCR1: RECEIVE CONTROL REGISTER 1 (Address=10 Hex)
(MSB) (LSB)
RSMFRSMRSIO--FRCSYNCERESYNC
SYMBOLPOSITIONNAME AND DESCRIPTION
RSMFRCR1.7RSYNC Multiframe Function. Only used if the RSYNC pin is
programmed in the multiframe mode (RCR1.6=1).
0 = RSYNC outputs CAS multiframe boundaries
1 = RSYNC outputs CRC4 multiframe boundaries
RSMRCR1.6RSYNC Mode Select.
0 = frame mode (see the timing in Section 13)
1 = multiframe mode (see the timing in Section 13)
RSIORCR1.5RSYNC I/O Select.
0 = RSYNC is an output (depends on RCR1.6)
1 = RSYNC is an input (only valid if elastic store enabled)
(note: this bit must be set to 0 when RCR2.1=0)RCR1.4Not Assigned. Should be set to 0 when written to.RCR1.3Not Assigned. Should be set to 0 when written to.
FRCRCR1.2Frame Resync Criteria.
0 = resync if FAS received in error 3 consecutive times= resync if FAS or bit 2 of non-FAS is received in error 3
consecutive times
SYNCERCR1.1Sync Enable.
0 = auto resync enabled
1 = auto resync disabled
RESYNCRCR1.0Resync. When toggled from low to high, a resync is initiated.
Must be cleared and set again for a subsequent resync.
DS2143/DS2143Q
SYNC/RESYNC CRITERIA Table 2
FRAME OR
MULTIFRAME
LEVEL
SYNC CRITERIARESYNC CRITERIAITU
SPEC.
FASFAS present in frames N and N
+ 2, and FAS not present in
frame N + 1.
Three consecutive incorrect FAS
received.
Alternate (RCR1.2=1) the above
criteria is met or three consecutive
incorrect bit 2 of non-FAS received.
G.706
CRC4Two valid MF alignment words
found within 8 ms.
915 or more CRC4 code words out
of 1000 received in error.
G.706
CASValid MF alignment word
found and previous time slot 16
contains code other than all 0s.
Two consecutive MF alignment
words received in error.
G.732
RCR2: RECEIVE CONTROL REGISTER 2 (Address=11 Hex)
(MSB) (LSB)
Sa8SSa7SSa6SSa5SSa4SSCLKMESE-
SYMBOLPOSITIONNAME AND DESCRIPTION
Sa8SRCR2.7Sa8 Bit Select. Set to 1 to report the Sa8 bit at the RLINK pin;
set to 0 to not report the Sa8 bit.
Sa7SRCR2.6Sa7 Bit Select. Set to 1 to report the Sa7 bit at the RLINK pin;
set to 0 to not report the Sa7 bit.
Sa6SRCR2.5Sa6 Bit Select. Set to 1 to report the Sa6 bit at the RLINK pin;
set to 0 to not report the Sa6 bit.
Sa5SRCR2.4Sa5 Bit Select. Set to 1 to report the Sa5 bit at the RLINK pin;
set to 0 to not report the Sa5 bit.
Sa4SRCR2.3Sa4 Bit Select. Set to 1 to report the Sa4 bit at the RLINK pin;
set to 0 to not report the Sa4 bit.
SCLKMRCR2.2SYSCLK Mode Select.
0 = if SYSCLK is 1.544 MHz.
1 = if SYSCLK is 2.048 MHz.
ESERCR2.1Elastic Store Enable.
0 = elastic store is bypassed.
1 = elastic store is enabled.RCR2.0Not Assigned. Should be set to 0 when written to.
DS2143/DS2143Q
TCR1: TRANSMIT CONTROL REGISTER 1 (Address=12 Hex)
(MSB) (LSB)
ODFTFPTT16STUA1TSiSTSA1TSMTSIO
SYMBOLPOSITIONNAME AND DESCRIPTION
ODFTCR1.7Output Data Format.
0 = bipolar data at TPOS and TNEG.
1 = NRZ data at TPOS; TNEG=0.
TFPTTCR1.6Transmit Timeslot 0 Pass Through.
0 = FAS bits/Sa bits/Remote Alarm sourced internally from the
TAF and TNAF registers.
1 = FAS bits/Sa bits/Remote Alarm sourced from TSER.
T16STCR1.5Transmit Timeslot 16 Data Select.
0 = sample timeslot 16 at TSER pin.
1 = source timeslot 16 from TS1 to TS16 registers.
TUA1TCR1.4Transmit Unframed All 1s.
0 = transmit data normally.
1 = transmit an unframed all 1s code at TPOS and TNEG.
TSiSTCR1.3Transmit International Bit Select.
0 = sample Si bits at TSER pin.
1 = source Si bits from TAF and TNAF registers (in this mode,
TCR1.6 must be set to 0).
TSA1TCR1.2Transmit Signaling All 1s.
0 = normal operation.
1 = force timeslot 16 in every frame to all 1s.
TSMTCR1.1TSYNC Mode Select.
0 = frame mode (see the timing in Section 13).
1 = CAS and CRC4 multiframe mode (see the timing in Section
13).
TSIOTCR1.0TSYNC I/O Select.
0 = TSYNC is an input.
1 = TSYNC is an output.
DS2143/DS2143Q
TCR2: TRANSMIT CONTROL REGISTER 2 (Address=13 Hex)
(MSB) (LSB)
Sa8SSa7SSa6SSa5SSa4S-AEBEP34F
SYMBOLPOSITIONNAME AND DESCRIPTION
Sa8STCR2.7Sa8 Bit Select. Set to 1 to source the Sa8 bit from the TLINK
pin; set to 0 to not source the Sa8 bit.
Sa7STCR2.6Sa7 Bit Select. Set to 1 to source the Sa7 bit from the TLINK
pin; set to 0 to not source the Sa7 bit.
Sa6STCR2.5Sa6 Bit Select. Set to 1 to source the Sa6 bit from the TLINK
pin; set to 0 to not source the Sa6 bit.
Sa5STCR2.4Sa5 Bit Select. Set to 1 to source the Sa5 bit from the TLINK
pin; set to 0 to not source the Sa5 bit.
Sa4STCR2.3Sa4 Bit Select. Set to 1 to source the Sa4 bit from the TLINK
pin; set to 0 to not source the Sa4 bit.TCR2.2Not Assigned. Should be set to 0 when written to.
AEBETCR2.1Automatic E-Bit Enable.
0 = E-bits not automatically set in the transmit direction.
1 = E-bits automatically set in the transmit direction.
P34FTCR2.0Function of Pin 34.
0 = Receive Loss of Sync (RLOS).
1 = Loss of Transmit Clock (LOTC).
DS2143/DS2143Q
CCR: COMMON CONTROL REGISTER (Address=14 Hex)
(MSB) (LSB)
LLBTHDB3TG802TCRC4RSMRHDB3RG802RCRC4
SYMBOLPOSITIONNAME AND DESCRIPTION
LLBCCR.7Local Loopback.
0 = loopback disabled.
1 = loopback enabled.
THDB3CCR.6Transmit HDB3 Enable.
0 = HDB3 disabled.
1 = HDB3 enabled.
TG802CCR.5Transmit G.802 Enable. See Section 13 for details.
0 = do not force TCHBLK high during bit 1 of timeslot 26.
1 = force TCHBLK high during bit 1 of timeslot 26.
TCRC4CCR.4Transmit CRC4 Enable.
0 = CRC4 disabled.
1 = CRC4 enabled.
RSMCCR.3Receive Signaling Mode Select.
0 = CAS signaling mode.
1 = CCS signaling mode.
RHDB3CCR.2Receive HDB3 Enable.
0 = HDB3 disabled.
1 = HDB3 enabled.
RG802CCR.1Receive G.802 Enable. See Section 13 for details.
0 = do not force RCHBLK high during bit 1 of timeslot 26
1 = force RCHBLK high during bit 1 of timeslot 26.
RCRC4CCR.0Receive CRC4 Enable.
0 = CRC4 disabled.
1 = CRC4 enabled.
LOCAL LOOPBACK
When CCR.7 is set to a 1, the DS2143 will enter a Local LoopBack (LLB) mode. This loopback is useful
in testing and debugging applications. In LLB, the DS2143 will loop data from the transmit side back to
the receive side. This loopback is synonymous with replacing the RCLK input with the TCLK signal, and
the RPOS/RNEG inputs with the TPOS/TNEG outputs. When LLB is enabled, the following will occur:
1. data at RPOS and RNEG will be ignored;
2. all receive side signals will take on timing synchronous with TCLK instead of RCLK;
3. all functions are available.
DS2143/DS2143Q
4.0 STATUS AND INFORMATION REGISTERS
There is a set of four registers that contain information on the current real time status of the DS2143:
Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), and Synchronizer
Status Register (SSR). When a particular event has occurred (or is occurring), the appropriate bit in one
of these three registers will be set to a 1. All of the bits in these registers operate in a latched fashion
(except for the SSR). This means that if an event occurs and a bit is set to a 1 in any of the registers, it
will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set
again until the event has occurred again or if the alarm(s) is still present.
The user will always precede a read of the SR1, SR2, and RIR registers with a write. The byte written to
the register will inform the DS2143 which bits the user wishes to read and have cleared. The user will
write a byte to one of these three registers, with a 1 in the bit positions he or she wishes to read and a 0 in
the bit positions he or she does not wish to obtain the latest information on. When a 1 is written to a bit
location, the read register will be updated with current value and it will be cleared. When a 0 is written tobit position, the read register will not be updated and the previous value will be held. A write to the
status and information registers will be immediately followed by a read of the same register. The read
result should be logically AND’ed with the mask byte that was just written and this value should be
written back into the same register to insure that the bit does indeed clear. This second write is necessary
because the alarms and events in the status registers occur asynchronously in respect to their access via
the parallel port. This scheme allows an external microcontroller or microprocessor to individually poll
certain bits without disturbing the other bits in the register. This operation is key in controlling the
DS2143 with higher order software languages.
The SSR register operates differently than the other three. It is a read only register and it reports the status
of the synchronizer in real time. This register is not latched and it is not necessary to precede a read of
this register with a write.
The SR1 and SR2 registers have the unique ability to initiate a hardware interrupt via the INT1 and INT2
pins respectively. Each of the alarms and events in the SR1 and SR2 can be either masked or unmasked
from the interrupt pins via the Interrupt Mask Register 1 (IMR1) and Interrupt Mask Register 2 (IMR2)
respectively.
DS2143/DS2143Q
RIR: RECEIVE INFORMATION REGISTER (Address=08 Hex)
(MSB) (LSB)--ESFESE-FASRCCASRC
SYMBOLPOSITIONNAME AND DESCRIPTION
-RIR.7Not Assigned. Could be any value when read.
-RIR.6Not Assigned. Could be any value when read.
-RIR.5Not Assigned. Could be any value when read.
ESFRIR.4Elastic Store Full. Set when the elastic store buffer fills and a
frame is deleted.
ESERIR.3Elastic Store Empty. Set when the elastic store buffer empties
and a frame is repeated.
-RIR.2Not Assigned. Could be any value when read.
FASRCRIR.1FAS Resync Criteria Met. Set when three consecutive FAS
words are received in error.
CASRCRIR.0CAS Resync Criteria Met. Set when two consecutive CAS MF
alignment words are received in error.
DS2143/DS2143Q
SSR: SYNCHRONIZER STATUS REGISTER (Address=1E Hex)
(MSB) (LSB)
CSC5CSC4CSC3CSC2CSC0FASSACASSACRC4SA
SYMBOLPOSITIONNAME AND DESCRIPTION
CSC5SSR.7CRC4 Sync Counter Bit 5. MSB of the 6-bit counter.
CSC4SSR.6CRC4 Sync Counter Bit 4.
CSC3SSR.5CRC4 Sync Counter Bit 3.
CSC2SSR.4CRC4 Sync Counter Bit 2.
CSC1SSR.3CRC4 Sync Counter Bit 0. LSB of the 6-bit counter. The next
to LSB is not accessible.
FASSASSR.2FAS Sync Active. Set while the synchronizer is searching for
alignment at the FAS level.
CASSASSR.1CAS MF Sync Active. Set while the synchronizer is searching
for the CAS MF alignment word.
CRC4SASSR.0CRC4 MF Sync Active. Set while the synchronizer is searching
for the CRC4 MF alignment word.
CRC4 SYNC COUNTER
The CRC4 Sync Counter increments each time the 8ms CRC4 multiframe search times out. The counter
is cleared when the DS2143 has successfully obtained synchronization at the CRC4 level. The counter
can also be cleared by disabling the CRC4 mode (CCR.0=0). This counter is useful for determining the
amount of time the DS2143 has been searching for synchronization at the CRC4 level. Annex B of
CCITT G.706 suggests that if synchronization at the CRC4 level cannot be obtained within 400 ms, then
the search should be abandoned and proper action taken. The CRC4 Sync Counter will rollover
DS2143/DS2143Q
SR1: STATUS REGISTER 1 (Address=06 Hex)
(MSB) (LSB)
RSA1RDMARSA0SLIPRUA1RRARCLRLOS
SYMBOLPOSITIONNAME AND DESCRIPTION
RSA1SR1.7Receive Signaling All 1s. Set when the contents of timeslot 16
contains less than 3 0s over 16 consecutive frames. This alarm is
not disabled in the CCS signaling mode.
RDMASR1.6Receive Distant MF Alarm. Set when bit 6 of timeslot 16 in
frame 0 has been set for 2 consecutive multiframes. This alarm
is not disabled in the CCS signaling mode.
RSA0SR1.5Receive Signaling All 0s. Set when over a full MF, timeslot 16
contains all 0s.
SLIPSR1.4Elastic Store Slip Occurrence. Set when the elastic store has
either repeated or deleted a frame of data.
RUA1SR1.3Receive Unframed All 1s. Set when an unframed all 1s code is
received at RPOS and RNEG.
RRASR1.2Receive Remote Alarm. Set when a remote alarm is received at
RPOS and RNEG.
RCLSR1.1Receive Carrier Loss. Set when 255 consecutive 0s have been
detected at RPOS and RNEG.
RLOSSR1.0Receive Loss of Sync. Set when the device is not synchronized
to the receive E1 stream.
DS2143/DS2143Q
ALARM CRITERIA Table 2
ALARMSET CRITERIACLEAR CRITERIAITU
SPEC.
RSA1
(receive signaling
all 1s)
over 16 consecutive frames
(one full MF) timeslot 16
contains less than 3 0s
over 16 consecutive frames (one full
MF) timeslot 16 contains three or
more 0s
G.732
RSA0
(receive signaling
all 0s)
over 16 consecutive frames
(one full MF) timeslot 16
contains all 0s
over 16 consecutive frames (one full
MF) timeslot 16 contains at least a
single 1
G.732
RDMA
(receive distant
multiframe alarm)
bit 6 in timeslot 16 of frame 0
set to 1 for two consecutive
MFs
bit 6 in timeslot 16 of frame 0 set to
0 for two consecutive MFs
O.162
RUA1
(receive unframed
all 1s)
less than three 0s in two frames
(512 bits)
more than two 0s in two frames (512
bits)
O.162
RRA
(receive remote
alarm)
bit 3 of non-align frame set to 1
for three consecutive occasions
bit 3 of non-align frame set to 0 for
three consecutive occasions
O.162
RCL
(receive carrier
loss)
255 consecutive 0s receivedin 255 bit times, at least 32 1s are
received
G.775
Note: all the alarm bits in Status Register 1 except the RUA1 will remain set after they are read if the
alarm condition still exists; the RUA1 will clear and check the next 512 bits for an all 1s condition at
which point it will again be set if the alarm condition still is present.
DS2143/DS2143Q
SR2: STATUS REGISTER 2 (Address=07 Hex)
(MSB) (LSB)
RMFRAFTMFSECTAFLOTCRCMFLORC
SYMBOLPOSITIONNAME AND DESCRIPTION
RMFSR2.7Receive CAS Multiframe. Set every 2 ms (regardless if CAS
signaling is enabled or not) on receive multiframe boundaries.
Used to alert the host that signaling data is available.
RAFSR2.6Receive Align Frame. Set every 250 μs at the beginning of
align frames. Used to alert the host that Si and Sa bits are
available in the RAF and RNAF registers.
TMFSR2.5Transmit Multiframe. Set every 2 ms (regardless if CRC4 is
enabled) on transmit multiframe boundaries. Used to alert the
host that signaling data needs to be updated.
SECSR2.4One-Second Timer. Set on increments of 1 second based on
RCLK.
TAFSR2.3Transmit Align Frame. Set every 250 μs at the beginning of
align frames. Used to alert the host that the TAF and TNAF
registers need to be updated.
LOTCSR2.2Loss of Transmit Clock. Set when the TCLK pin has not
transitioned for one channel time (or 3.9 μs). Will force pin 34
high if enabled via TCR2.0. Based on RCLK.
RCMFSR2.1Receive CRC4 Multiframe. Set on CRC4 multiframe
boundaries; will continue to be set every 2 ms on an arbitrary
boundary if CRC4 is disabled.
LORCSR2.0Loss of Receive Clock. Set when the RCLK pin has not
transitioned for at least 2 μs (3 μs ±1 μs).
DS2143/DS2143Q
IMR1: INTERRUPT MASK REGISTER 1 (Address=16 Hex)
(MSB) (LSB)
RSA1RDMARSA0SLIPRUA1RRARCLRLOS
SYMBOLPOSITIONNAME AND DESCRIPTION
RSA1IMR1.7Receive Signaling All 1s.
0 = interrupt masked.
1 = interrupt enabled.
RDMAIMR1.6Receive Distant MF Alarm.
0 = interrupt masked.
1 = interrupt enabled.
RSA0IMR1.5Receive Signaling All 0s.
0 = interrupt masked.
1 = interrupt enabled.
SLIPIMR1.4Elastic Store Slip Occurrence.
0 = interrupt masked.
1 = interrupt enabled.
RUA1IMR1.3Receive Unframed All 1s.
0 = interrupt masked.
1 = interrupt enabled.
RRAIMR1.2Receive Remote Alarm.
0 = interrupt masked.
1 = interrupt enabled.
RCLIMR1.1Receive Carrier Loss.
0 = interrupt masked.
1 = interrupt enabled.
RLOSIMR1.0Receive Loss of Sync.
0 = interrupt masked.
1 = interrupt enabled.
DS2143/DS2143Q
IMR2: INTERRUPT MASK REGISTER 2 (Address=17 Hex)
(MSB) (LSB)
RMFRAFTMFSECTAFLOTCRCMFLORC
SYMBOLPOSITIONNAME AND DESCRIPTION
RMFIMR2.7Receive CAS Multiframe.
0 = interrupt masked.
1 = interrupt enabled.
RAFIMR2.6Receive Align Frame.
0 = interrupt masked.
1 = interrupt enabled.
TMFIMR2.5Transmit Multiframe.
0 = interrupt masked.
1 = interrupt enabled.
SECIMR2.41-Second Timer.
0 = interrupt masked.
1 = interrupt enabled.
TAFIMR2.3Transmit Align Frame.
0 = interrupt masked.
1 = interrupt enabled.
LOTCIMR2.2Loss Of Transmit Clock.
0 = interrupt masked.
1 = interrupt enabled.
RCMFIMR2.1Receive CRC4 Multiframe.
0 = interrupt masked.
1 = interrupt enabled.
LORCIMR2.0Loss of Receive Clock.
0 = interrupt masked.
1 = interrupt enabled.
5.0 ERROR COUNT REGISTERS
There are a set of three counters in the DS2143 that record bipolar violations, errors in the CRC4 SMF
code words, and E-bits as reported by the far end. Each of these three counters are automatically updated
on 1-second boundaries as determined by the 1-second timer in Status Register 2 (SR2.4). Hence, these
registers contain performance data from the previous second. The user can use the interrupt from the 1-
second timer to determine when to read these registers. The user has a full second to read the counters
before the data is lost.
DS2143/DS2143Q
BPVCR1:
UPPER BIPOLAR VIOLATION COUNT REGISTER 1 (Address=00 Hex)
BPVCR2:
LOWER BIPOLAR VIOLATION COUNT REGISTER 2 (Address=01 Hex)
(MSB) (LSB)
BV7BV6BV5BV4BV3BV2BV1BV0BPVCR2
BV15BV14BV13BV12BV11BV10BV9BV8BPVCR1
SYMBOLPOSITIONNAME AND DESCRIPTION
BV15BPVCR1.7MSB of the bipolar violation count.
BV0BPVCR2.0LSB of the bipolar violation count.
Bipolar Violation Count Register 1 (BPVCR1) is the most significant word and BPVCR2 is the least
significant word of a 16-bit counter that records bipolar violations (BPVs). If the HDB3 mode is set for
the receive side via CCR.2, then HDB3 code words are not counted. This counter increments at all times
and is not disabled by loss of sync conditions. The counter saturates at 65,535 and will not rollover. The
bit error rate on a E1 line would have to be greater than 10**-2 before the BPVCR would saturate.
CRCCR1: CRC4 COUNT REGISTER 1 (Address=02 Hex)
CRCCR2: CRC4 COUNT REGISTER 2 (Address=03 Hex)
(MSB) (LSB)
CRC7CRC6CRC5CRC4CRC3CRC2CRC1CRC0CRCCR2
CRC14CRC14CRC13CRC12CRC11CRC10CRC9CRC8CRCCR1
SYMBOLPOSITIONNAME AND DESCRIPTION
CRC15CRCCR1.7MSB of the CRC4 error count.
CRC0CRCCR2.0LSB of the CRC4 error count.
CRC4 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant
word of a 16-bit counter that records word errors in the Cyclic Redundancy Check 4 (CRC4). Since the
maximum CRC4 count in a 1-second period is 1000, this counter cannot saturate. The counter is disabled
during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of sync occurs at the
CAS level.

Partno	Mfg	Dc	Qty	Available	Descript
DS2143Q	MAXIM	N/a	122	avai	E1 Controller