DS2141AQ Fast Delivery |IC PHOENIX CO.,LIMITED

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DS2141AQ
T1 Controller
FEATURESDS1/ISDN-PRI framing transceiverFrames to D4, ESF, and SLC-96 formatsParallel control portOnboard, dual two-frame elastic store slip
buffersExtracts and inserts robbed-bit signalingProgrammable output clocksOnboard FDL support circuitry5V supply; low-power CMOSAvailable in 40-pin DIP and 44-pin PLCC
(DS2141Q)Compatible with DS2186 Transmit Line
Interface, DS2187 Receive Line Interface,DS2188 Jitter Attenuator, DS2290 T1
Isolation Stik, and DS2291 T1 Long Loop
Stik
PIN ASSIGNMENT
DESCRIPTION
The DS2141A is a comprehensive, software-driven T1 framer. It is meant to act as a slave or coprocessor
to a microcontroller or microprocessor. Quick access via the parallel control port allows a single micro to
handle many T1 lines. The DS2141A is very flexible and can be configured into numerous orientationsvia software. The software orientation of the device allows the user to modify their design to conform to
40-Pin DIP (600-mil)
TCHCLK
TNEG
AD1
AD2
AD3
AD4
AD5
AD6
BTS
AD7
VDD
TLCLK
INT1
INT2
RLOS/LOTC
TCHBLK
RCHBLKCSCLKSDI
RNEG
SYSCLK
TSER
TPOS
AD0
TCLK
TSYNC
TLINK
VSS
RLINK
RPOS
RSYNC
RSER
RCHCLK
RLCLK
RCLK
AD0AD1AD2
AD3
AD4
AD5
RLOS/LOTCTCHBLK
RCHBLKLI_CS
LI_CLK
LI_SDIAD6NC
TPOST
HCLK
TSERTC
TSYNCS
WR(R/
AD7
BTS
RD(DS)NC
TLIN
TLC
SYN
SYSCLKRNEGRPOS
DS2141A
link. The device fully meets all of the latest T1 specifications including ANSI T1.403-1989, AT&T TR
62411 (12-90), and CCITT G.704 and G.706.
1.0 INTRODUCTION
The DS2141A T1 Controller has four main sections: the receive side, the transmit side, the line interface
controller, and the parallel control port. See the block diagram below. On the receive side, the device will
clock in the serial T1 stream via the RPOS and RNEG pins. The synchronizer will locate the frame and
multiframe patterns and establish their respective positions. This information will be used by the rest ofthe receive side circuitry.
The DS2141A is an “off-line” framer, which means that all of the T1 serial stream that goes into the
device will come out of it unchanged. Once the T1 data has been framed to, the robbed-bit signaling data
and FDL can be extracted. The 2-frame elastic stores can either be enabled or bypassed.
The transmit side clocks in the unframed T1 stream at TSER and adds in the framing pattern, the robbed-
bit signaling, and the FDL. The line interface control port will update line interface devices that contain a
serial port. The parallel control port contains a multiplexed address and data structure which can beconnected to either a microcontroller or microprocessor.
DS2141A BLOCK DIAGRAM
DS2141A
DS2141A FEATURESParallel control portLarge error countersOnboard dual 2-frame elastic storeFDL support circuitryRobbed-bit signaling extraction and insertionProgrammable output clocksFully independent transmit and receive sectionsFrame sync generationError-tolerant yellow and blue alarm detectionOutput pin test modePayload loopback capabilitySLC-96 supportRemote loop up/down code detectionLoss of transmit clock detectionLoss of receive clock detection1's density violation detection
PIN DESCRIPTION Table 1
DS2141A
DS2141A
DS2141A REGISTER MAP
DS2141A
Note: All values indicated within the Address
column are hexadecimal.
2.0 PARALLEL PORT
The DS2141A is controlled via a multiplexed bidirectional address/data bus by an external
microcontroller or microprocessor. The DS2141A can operate with either Intel or Motorola bus timing
configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will
be selected. All Motorola bus signals are listed in parentheses (). See the timing diagrams in the AC
Electrical Characteristics for more details. The multiplexed bus on the DS2141A saves pins because theaddress information and data information share the same signal paths. The addresses are presented to the
pins in the first portion of the bus cycle and data will be transferred on the pins during second portion of
the bus cycle. Addresses must be valid prior to the falling edge of ALE(AS), at which time the DS2141A
latches the address from the AD0 to AD7 pins. Valid write data must be present and held stable during
the later portion of the DS or WR pulses. In a read cycle, the DS2141A outputs a byte of data during the
latter portion of the DS or RD pulses. The read cycle is terminated and the bus returns to a high
impedance state as RD transitions high in Intel timing or as DS transitions low in Motorola timing.
3.0 CONTROL REGISTERS
The operation of the DS2141A is configured via a set of six registers. Typically, the control registers are
only accessed when the system is first powered up. Once, the DS2141A has been initialized, the control
DS2141A
RCR1: RECEIVE CONTROL REGISTER 1 (2Bh)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONRCR1.7Not Assigned. Should be set to 0 when written to.
ARCRCR1.6Auto Resync Criteria.0=Resync on OOF or RCL event.
1=Resync on OOF only.
OOF1RCR1.5Out Of Frame Select 1.0=2/4 frame bits in error.
1=2/5 frame bits in error.
OOF2RCR1.4Out Of Frame Select 2.
0=follow RCR1.5.1=2/6 frame bits in error.
SYNCCRCR1.3Sync Criteria.
In D4 Framing Mode.
0=search for Ft pattern, then search for Fs pattern.1=cross couple Ft and Fs pattern.
In ESF Framing Mode.
0=search for FPS pattern only.
1=search for FPS and verify with CRC6.
SYNCTRCR1.2Sync Time.0=qualify 10 bits.
1=qualify 24 bits.
SYNCERCR1.1Sync Enable.0=auto resync enabled.
1=auto resync disabled.
RESYNCRCR1.0Resync. When toggled from low to high, a resync is initiated.
Must be cleared and set again for a subsequent resync.
DS2141A
RCR2: RECEIVE CONTROL REGISTER 2 (2Ch)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
RCSRCR2.7Receive Code Select.
0=idle code (7F Hex).1=digital milliwatt code (1E/0B/0B/1E/9E/8B/8B/9E Hex).
RZBTSIRCR2.6Receive Side ZBTSI Enable.
0=ZBTSI disabled.
1=ZBTSI enabled.
RSDWRCR2.5RSYNC Double-Wide.
0=do not pulse double-wide in signaling frames.
1=do pulse double-wide in signaling frames.
(note: this bit must be set to 0 when RCR2.4 = 1 or whenRCR2.3 = 1).
RSMRCR2.4RSYNC Mode Select.
0=frame mode (see the timing in Section 13).
1=multiframe mode (see the timing in Section 13).
RSIORCR2.3RSYNC I/O Select.
0=RSYNC is an output.
1=RSYNC is an input (only valid if elastic store enabled).
(note: this bit must be set to 0 when CCR1.2 = 0).
RD4YMRCR2.2Receive Side D4 Yellow Alarm Select.
0=0 in bit 2 of all channels.
1=a 1 in the S-bit position of frame 12.
FSBERCR2.1Fs-Bit Error Report Enable.0=do not report bit errors in the Fs-bit position in FECR.
1=report bit errors in the Fs-bit position in FECR.
BPVCRSRCR2.0BPVCRS Function Select.0=counts bipolar violations.
1=counts ESF error events (CRC6 OR 'ed with RLOS).
DS2141A
TCR1: TRANSMIT CONTROL REGISTER 1 (35h)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
ODFTCR1.7Output Data Format.
0=bipolar data at TPOS and TNEG.1=NRZ data at TPOS; TNEG = 0.
TFPTTCR1.6Transmit Framing Pass Through.
0=Ft or FPS bits sourced internally.
1=Ft or FPS bits sampled at TSER during F-bit time.
TCPTTCR1.5Transmit CRC Pass Through.
0=source CRC6 bits internally.
1=CRC6 bits sampled at TSER during F-bit time.
RBSETCR1.4Robbed Bit Signaling Enable.0=no signaling is inserted in any channel.
1=signaling is inserted in all channels (the TTR registers can be
used to block insertion on a channel by channel basis).
GB7STCR1.3Global Bit 7 Stuffing.0=allow the TTR registers to determine which channels
containing all zeros are to be bit 7 stuffed.
1=force bit 7 stuffing in all zero byte channels regardless of how
the TTR registers are programmed.
TLINKTCR1.2TLINK Select.0=source FDL or Fs bits from TFDL register.
1=source FDL or Fs bits from the TLINK pin.
TBLTCR1.1Transmit Blue Alarm.0=transmit data normally.
1=transmit an unframed all 1's code at TPOS and TNEG.
TYELTCR1.0Transmit Yellow Alarm.
0=do not transmit yellow alarm.1=transmit yellow alarm.
DS2141A
TCR2: TRANSMIT CONTROL REGISTER 2 (36h)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
TESTMTCR2.7Test Mode Select. Set this bit to a 1 to force all outputs
(including I/O pins) either high (TCR2.6 = 1) or low (TCR2.6 =0).
TESTIOTCR2.6Test I/O Pins.
0=force all output (and I/O) pins to a logic 0.
1=force all output (and I/O) pins to a logic 1.
TZBTSITCR2.5Transmit Side ZBTSI Enable.
0=ZBTSI disabled.
1=ZBTSI enabled.
TSDWTCR2.4TSYNC Double-Wide.0=do not pulse double-wide in signaling frames.
1=do pulse double-wide in signaling frames.
(note: this bit must be set to 0 when TCR 2.3 = 1 or when
TCR2.2 = 0).
TSMTCR2.3TSYNC Mode Select.
0=frame mode (see the timing in Section 13).
1=multiframe mode (see the timing in Section 13).
TSIOTCR2.2TSYNC I/O Select.0=TSYNC is an input.
1=TSYNC is an output.
TD4YMTCR2.1Transmit Side D4 Yellow Alarm Select.0=0s in bit 2 of all channels.
1=a 1 in the S-bit position of frame 12.
B7ZSTCR2.0Bit 7 Zero Suppression Enable.
0=no stuffing occurs.1=Bit 7 forced to a 1 in channels with all 0s.
DS2141A
CCR1: COMMON CONTROL REGISTER 1 (37h)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
TESECCR1.7Transmit Elastic Store Enable.
0=elastic store is bypassed.
1=elastic store is enabled.
P34FCCR1.6Function of Pin 34.0=Receive Loss of Sync (RLOS).
1=Loss of Transmit Clock (LOTC).
RSAOCCR1.5Receive Signaling All 1's.0=allow robbed signaling bits to appear at RSER.
1=force all robbed signaling bits at RSER to 1.CCR1.4Not Assigned. Should be set to 0 when written to.
SCLKMCCR1.3SYSCLK Mode Select.0=if SYSCLK is 1.544 MHz.
1=if SYSCLK is 2.048 MHz.
RESECCR1.2Receive Elastic Store Enable.0=elastic store is bypassed.
1=elastic store is enabled.
PLBCCR1.1Payload Loopback.
0=loopback disabled.1=loopback enabled.
LLBCCR1.0Local Loopback.
0=loopback disabled.
1=loopback enabled.
PAYLOAD LOOPBACK
When CCR1.1 is set to a 1, the DS2141A will be forced into Payload LoopBack (PLB). Normally, this
loopback is only enabled when ESF framing is being performed. In a PLB situation, the DS2141A will
loop the 192 bits of payload data (with BPVs corrected) from the receive section back to the transmitsection. The FPS framing pattern, CRC6 calculation, and the FDL bits are not looped back, they are
reinserted by the DS2141A. When PLB is enabled, the following will occur:
1. Data will be transmitted from the TPOS and TNEG pins synchronous with RCLK instead of TCLK.
2. All of the receive side signals will continue to operate normally.
3. The TCHCLK and TCHBLK signals are forced low.
DS2141A
LOCAL LOOPBACK
When CCR1.0 is set to a 1, the DS2141A will enter a Local LoopBack (LLB) mode. This loopback is
useful in testing and debugging applications. In LLB, the DS2141A will loop data from the transmit side
back to the receive side. This loopback is synonymous with replacing the RCLK input with the TCLK
signal, and the RPOS/RNEG inputs with the TPOS/TNEG outputs. When LLB is enabled, the following
will occur:
1. The TPOS and TNEG pins will transmit an unframed all 1's.2. Data at RPOS and RNEG will be ignored.
3. All receive side signals will take on timing synchronous with TCLK instead of RCLK.
CCR1: COMMON CONTROL REGISTER 2 (38h)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
TFMCCR2.7Transmit Frame Mode Select.0=D4 framing mode.
1=ESF framing mode.
TB8ZSCCR2.6Transmit B8ZS Enable.0=B8ZS disabled.
1=B8ZS enabled.
TSLC96CCR2.5Transmit SLC-96/Fs Bit Insertion Enable.
0=SLC-96 disabled.1=SLC-96 enabled.
TFDLCCR2.4Transmit Zero Stuffer Enable.
0=zero stuffer disabled.
1=zero stuffer enabled.
RFMCCR2.3Receive Frame Mode Select.
0=D4 framing mode.
1=ESF framing mode.
RB8ZSCCR2.2Receive B8ZS Enable.
0=B8ZS disabled.
1=B8ZS enabled.
RSLC96CCR2.1Receive SLC-96 Enable.0=SLC-96 disabled.
1=SLC-96 enabled.
RFDLCCR2.0Receive Zero Destuffer Enable.0=zero destuffer disabled.
DS2141A
4.0 STATUS AND INFORMATION REGISTERS
There is a set of three registers that contain information on the current real time status of the DS2141A:
Status Register 1 (SR1), Status Register 2 (SR2), and the Receive Information Register (RIR). When a
particular event has occurred (or is occurring), the appropriate bit in one of these three registers will be
set to a 1. All of the bits in these registers operate in a latched fashion. This means that if an event occurs
and a bit is set to a 1 in any of the registers, it will remain set until the user reads that bit. The bit will becleared when it is read and it will not be set again until the event has occurred again (or in the case of
RLOS, if loss of sync is still present).
The user will always precede a read of these registers with a write. The byte written to the register will
inform the DS2141A which bits the user wishes to read and have cleared. The user will write a byte toone of these three registers, with a 1 in the bit positions he or she wishes to read and a 0 in the bit
positions he or she does not wish to obtain the latest information on. When a 1 is written to a bit location,
the read register will be updated with current value and it will be cleared. When a 0 is written to a bit
position, the read register will not be updated and the previous value will be held. A write to the status
and information registers will be immediately followed by a read of the same register. The read resultshould be logically AND’ed with the mask byte that was just written and this value should be written
back into the same register to insure that the bit does indeed clear. This second write is necessary because
the alarms and events in the status registers occur asynchronously in respect to their access via the
parallel port. This scheme allows an external microcontroller or microprocessor to individually poll
certain bits without disturbing the other bits in the register. This operation is key in controlling theDS2141A with higher-order software languages.
The SR1 and SR2 registers have the unique ability to initiate a hardware interrupt via the INT1 and INT2
pins respectively. Each of the alarms and events in the SR1 and SR2 can be either masked or unmasked
from the interrupt pins via the Interrupt Mask Register 1 (IMR1) and Interrupt Mask Register 2 (IMR2)
respectively.
DS2141A
RIR: RECEIVE INFORMATION REGISTER (22h)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
COFARIR.7Change of Frame Alignment. Set when the last resync resulted
in a change of frame or multiframe alignment.
8ZDRIR.6Eight Zero Detect. Set when a string of eight consecutive 0s has
been received at RPOS and RNEG.
16ZDRIR.5Sixteen Zero Detect. Set when a string of 16 consecutive 0s hasbeen received at RPOS and RNEG.
RESFRIR.4Receive Elastic Store Full. Set when the elastic store buffer
fills and a frame is deleted.
RESERIR.3Receive Elastic Store Empty. Set when the elastic store buffer
empties and a frame is repeated.
SEFERIR.2Severely Errored Framing Event. Set when 2 out of 6 framing
bits are received in error.
B8ZSRIR.1B8ZS Code Word Detect. Set when a B8ZS code word is
detected at RPOS and RNEG independent of whether the B8ZS
mode is selected or not via CCR2.2.
FBERIR.0Frame Bit Error. Set when a Ft (D4) or FPS (ESF) framing bit
is received in error.
Note: If the transmit elastic store slips, both RIR.4 and RIR.3 will be set.
DS2141A
SR1: STATUS REGISTER 1 (20h)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
LUPSR1.7Loop Up Code Detected. Set when the repeating …00001…
loop up code is being received.
LDNSR1.6Loop Down Code Detected. Set when the repeating …001…
loop down code is being received.
LOTCSR1.5Loss of Transmit Clock. Set when the TCLK pin has not
transitioned for one channel time (or 5.2 μs). Will force pin-34
high if enabled via CCR1.6. Based on RCLK.
SLIPSR1.4Elastic Store Slip Occurrence. Set when the elastic store haseither repeated or deleted a frame of data.
RBLSR1.3Receive Blue Alarm. Set when an all 1's code is received at
RPOS and RNEG.
RYELSR1.2Receive Yellow Alarm. Set when a yellow alarm is received at
RPOS and RNEG.
RCLSR1.1Receive Carrier Loss. Set when 192 consecutive 0s have been
detected at RPOS and RNEG.
RLOSSR1.0Receive Loss of Sync. Set when the device is not synchronized
to the receive T1 stream.
LOOP UP/DOWN CODE DETECTION
Bits SR1.7 and SR1.6 will indicate when either the standard “loop up” or “loop down” codes are beingreceived by the DS2141A. When a loop up code has been received for 5 seconds, the CPE is expected to
loop the recovered data (without correcting BPVs) back to the source. The loop down code indicates that
the loopback should be discontinued. See the AT&T publication TR 62411 for more details. The
DS2141A will detect the loop up/down codes in both framed and unframed circumstances with bit error
rates as high as 10-2. The loop code detector has a nominal integration period of 48 ms. Hence, after about48 ms of receiving either code, the proper status bit will be set to a 1. After this initial indication, it is
recommended that the software poll the DS2141A every 100 ms to 500 ms until five seconds have
elapsed to insure that the code is continuously present. Once five seconds have passed, the line interface
should be taken into or out of loopback.
DS2141A
SR2: STATUS REGISTER 2 (21h)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
RMFSR2.7Receive Multiframe. Set on receive multiframe boundaries.
TMFSR2.6Transmit Multiframe. Set on transmit multiframe boundaries.
SECSR2.5One Second Timer. Set on increments of one second based on
RCLK; will be set in increments of 999 ms, 999 ms, and 1002
ms every three seconds.
RFDLSR2.4Receive FDL Buffer Full. Set when the receive FDL buffer
(RFDL) fills to capacity (8-bits).
TFDLSR2.3Transmit FDL Buffer Empty. Set when the transmit FDLbuffer (TDFL) empties.
RMTCHSR2.2Receive FDL Match Occurrence. Set when the RFDL matches
either RFDLM1 or RFDLM2.
RAFSR2.1Receive FDL Abort. Set when eight consecutive 1's are
received in the FDL.
LORCSR2.0Loss of Receive Clock. Set when the RCLK pin has not
transitioned for at least 2 μs (3 μs ± 1 μs).
DS2141A
IMR1: INTERRUPT MASK REGISTER 1 (7Fh)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
LUPIMR1.7Loop Up Code Detected.
0=interrupt masked.1=interrupt enabled.
LDNIMR1.6Loop Down Code Detected.
0=interrupt masked.
1=interrupt enabled.
LOTCIMR1.5Loss of Transmit Clock.
0=interrupt masked.
1=interrupt enabled.
SLIPIMR1.4Elastic Store Slip Occurrence.0=interrupt masked.
1=interrupt enabled.
RBLIMR1.3Receive Blue Alarm.0=interrupt masked.
1=interrupt enabled.
RYELIMR1.2Receive Yellow Alarm.
0=interrupt masked.1=interrupt enabled.
RCLIMR1.1Receive Carrier Loss.
0=interrupt masked.
1=interrupt enabled.
RLOSIMR1.0Receive Loss of Sync.
0=interrupt masked.
1=interrupt enabled.
DS2141A
IMR2: INTERRUPT MASK REGISTER 2 (6Fh)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
RMFIMR2.7Receive Multiframe.
0=interrupt masked.1=interrupt enabled.
TMFIMR2.6Transmit Multiframe.
0=interrupt masked.
1=interrupt enabled.
SECIMR2.5One Second Timer.
0=interrupt masked.
1=interrupt enabled.
RFDLIMR2.4Receive FDL Buffer Full.0=interrupt masked.
1=interrupt enabled.
TFDLIMR2.3Transmit FDL Buffer Empty.0=interrupt masked.
1=interrupt enabled.
RMTCHIMR2.2Receive FDL Match Occurrence.
0=interrupt masked.1=interrupt enabled.
RAFIMR2.1Receive FDL Abort.
0=interrupt masked.
1=interrupt enabled.
LORCIMR2.0Loss of Receive Clock.
0=interrupt masked.
1=interrupt enabled.
DS2141A
5.0 ERROR COUNT REGISTERS
There is a set of three counters in the DS2141A that record bipolar violations, errors in the CRC6 code
words, and frame bit errors. Each of these three counters is automatically updated on 1-second boundaries
as determined by the 1-second timer in Status Register 2 (SR2.5). Hence, these registers contain
performance data from the previous second. The user can use the interrupt from the 1-second timer to
determine when to read these registers. The user has a full second to read the counters before the data islost.
BPVCR1: BIPOLAR VIOLATION COUNT REGISTER 1 (23h)
BPVCR2: BIPOLAR VIOLATION COUNT REGISTER 2 (24h)
(MSB) (LSB)BPVCR1BPVCR2
SYMBOLPOSITIONNAME AND DESCRIPTION
BV15BPVCR1.7MSB of the bipolar violation count.
BV0BPVCR2.0LSB of the bipolar violation count.
Bipolar Violation Count Register 1 (BPVCR1) is the most significant word and BPVCR2 is the least
significant word of a 16-bit counter that records bipolar violations (BPVs). If the B8ZS mode is set for
the receive side via CCR2.2, then B8ZS code words are not counted. This counter increments at all times
and is not disabled by loss of sync conditions. The counter saturates at 65,535 and will not roll over. If theDS2141A is programmed to record ESF error events (RCR2.0=1), then the BPVCR will increment for
each ESF multiframe that contains either an error in the CRC6 word or an out-of-frame occurrence (loss
of sync).
CRCCR1: CRC6 COUNT REGISTER 1 (25h)
CRCCR2: CRC6 COUNT REGISTER 2 (26h)
(MSB) (LSB)CRCCR1CRCCR2
SYMBOLPOSITIONNAME AND DESCRIPTION
CRC7CRCCR1.7MSB of the CRC6 count.
CRC0CRCCR2.0LSB of the CRC6 count.
CRC6 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant
word of a 16-bit counter that records word errors in the Cyclic Redundancy Check 6 (CRC6) when the
DS2141A is operated in the ESF framing mode (CCR2.3 = 1). This counter saturates at 65,535 and willnot roll over. The counter is disabled during loss of sync conditions.
DS2141A
FECR: FRAME ERROR COUNT REGISTER (27h)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
FE7FECR.7MSB of the Frame Error count.
FE0FECR.0LSB of the Frame Error count.
The Frame Error Count Register (FECR) is a 8-bit counter that records either errors in the framing
pattern. The FECR will count individual bit errors in the ESF framing pattern (...001011...) if the device
is set into the ESF framing mode (CCR2.3 = 1) and it will count individual bit errors in the Ft framing
pattern (...101010...) in the D4 framing mode (CCR2.3 = 0). If RCR2.1=1, then the FECR will also recordindividual bit errors in the Fs framing pattern (...001110...) when it is in the D4 framing mode. This
counter saturates at 255 and will not roll over. The counter is disabled during loss of sync conditions.
6.0 FDL/FS EXTRACTION AND INSERTION
The DS2141A has the ability to extract/insert data from/into the Facility Data Link (FDL) in the ESF
framing mode and from/into Fs-bit position in the D4 framing mode. Since SLC-96 utilizes the Fs-bitposition, this capability can also be used in SLC-96 applications. The operation of the receive and
transmit sections will be discussed separately.
6.1 Receive Section
In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the Receive FDL
register (RFDL). Since the RFDL is 8 bits in length, it will fill up every 2 ms (8 x 250 μs). The DS2141Awill signal an external microcontroller that the buffer has filled via the SR2.4 bit. If enabled via IMR2.4,
the INT2 pin will toggle low indicating that the buffer has filled and needs to be read. The user has 2 ms
to read this data before it is lost. If the byte in the RFDL matches either of the bytes programmed into the
RFDLM1 or RFDLM2 registers, then the SR2.2 bit will be set to a 1 and the INT2 pin will toggled low if
enabled via IMR2.2. This feature allows an external microcontroller to ignore the FDL or Fs pattern untilan important event occurs.
The DS2141A also contains a 0 destuffer which is controlled via the CCR2.0 bit. In both ANSI T1.403
and TR54016, communications on the FDL follow a subset of a LAPD protocol. The LAPD protocol
states that no more than five 1's should be transmitted in a row so that the data does not resemble anopening or closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.0, the DS2141A
will automatically look for five 1's in a row, followed by a 0. If it finds such a pattern, it will
automatically remove the 0. If the 0 destuffer sees six or more 1's in a row followed by a 0, the 0 is not
removed. The CCR2.0 bit should always be set to a 1 when the DS2141A is extracting the FDL. More on
how to use the DS2141A in FDL applications is covered in a separate Application Note.

Partno	Mfg	Dc	Qty	Available	Descript
DS2141AQ	DALLAS	N/a	161	avai	T1 Controller