DS21372 Fast Delivery |IC PHOENIX CO.,LIMITED

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DS21372TN ,3.3V Bit Error Rate Tester (BERT)applications requiring gap clocking such as Fractional-T1, Switched-56, DDS, normal framing require ..
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DS21372
3.3V Bit Error Rate Tester (BERT)
FEATURESGenerates/detects digital bit patterns for
analyzing, evaluating and troubleshooting
digital communications systemsOperates at speeds from DC to 20 MHzProgrammable polynomial length and
feedback taps for generation of any other
pseudorandom pattern up to 32 bits in length
including: 26-1, 29-1, 211-1, 215-1, 220-1, 223-1,
and 232-1Programmable user-defined pattern and
length for generation of any repetitive pattern
up to 32 bits in lengthLarge 32-bit error count and bit count
registersSoftware programmable bit error insertionFully independent transmit and receive
sections8-bit parallel control portDetects test patterns with bit error rates up to-2
PIN ASSIGNMENT
ORDERING INFORMATION
DS21372(00 C to 700 C)
DS21372N(-400 C to +850 C)
DESCRIPTION
The DS21372 Bit Error Rate Tester (BERT) is a software programmable test pattern generator, receiver,
and analyzer capable of meeting the most stringent error performance requirements of digital
transmission facilities. Two categories of test pattern generation (Pseudo-random and Repetitive)
conform to CCITT/ITU O.151, O.152, O.153, and O.161 standards. The DS21372 operates at clock rates
ranging from DC to 20 MHz. This wide range of operating frequency allows the DS21372 to be used in
existing and future test equipment, transmission facilities, switching equipment, multiplexers, DACs,
Routers, Bridges, CSUs, DSUs, and CPE equipment.
The DS21372 user-programmable pattern registers provide the unique ability to generate loopback
patterns required for T1, Fractional-T1, Smart Jack, and other test procedures. Hence the DS21372 can
initiate the loopback, run the test, check for errors, and finally deactivate the loopback.
The DS21372 consists of four functional blocks: the pattern generator, pattern detector, error counter, and
control interface. The DS21372 can be programmed to generate any pseudorandom pattern with length up
to 232-1 bits (see Table 5, Note 9) or any user programmable bit pattern from 1 to 32 bits in length. Logic
inputs can be used to configure the DS21372 for applications requiring gap clocking such as Fractional-
T1, Switched-56, DDS, normal framing requirements, and per-channel test procedures. In addition, the
DS21372
3.3VBitErrorRateTester(BERT)
www.dalsemi.com
AD0
AD1
TEST
VSS
AD2
AD3
AD4
RLOS
VSS
VDD
INT
WR(R/W)
ALE (AS)
BTS
RD(DS
ATA
RCLKRDI
RDA
DS21372
32-PIN TQFP
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
DS21372
1. GENERAL OPERATION
1.1 PATTERN GENERATION
The DS21372 is programmed to generate a particular test pattern by programming the following registers:Pattern Set Registers (PSR)Pattern Length Register (PLR)Polynomial Tap Register (PTR)Pattern Control Register (PCR)Error Insertion Register (EIR)
Please see Tables 4 and 5 for examples of how to program these registers in order to generate some
standard test patterns. Once these registers are programmed, the user will then toggle the TL (Transmit
Load) bit or pin to load the pattern into the onboard pattern generation circuitry and the pattern will begin
appearing at the TDATA pin.
1.2 PATTERN SYNCHRONIZATION
The DS21372 expects to receive the same pattern that it transmitted. The synchronizer examines the data
at RDATA and looks for characteristics of the transmitted pattern. The user can control the onboard
synchronizer with the Sync Enable and Resync bits in the Pattern Control Register.
In pseudorandom mode, the received pattern is tested to see if it fits the polynomial generator as defined
in the transmit side. For pseudorandom patterns, only the original pattern and an all ones pattern or an all
0s pattern will satisfy this test. Synchronization in pseudorandom pattern mode should be qualified by
using the RA1 and RA0 indicators in the Status Register. Synchronization is declared after 34 + n bits are
received without error, where n is the exponent in the polynomial from Table 4. Once in synchronization
(SR.0 = 1) any deviation from this pattern will be counted by the Bit Error Count Register.
In repetitive pattern mode a received pattern of the same length as being transmitted will satisfy this test.
Synchronization in repetitive pattern mode should be qualified by using the RA1 and RA0 indicators in
the Status Register and examining the Pattern Receive Register (PRR0--3). See section 10 for an
explanation of the Pattern Receive Register. Once in synchronization (SR.0 = 1) any deviation from this
pattern will be counted by the Bit Error Count Register.
1.3 BER CALCULATION
Users can calculate the actual Bit Error Rate (BER) of the digital communications channel by reading the
bit error count out of the Bit Error Count Register (BECR) and reading the bit count out of the Bit Count
Register (BCR) and then dividing the BECR value with the BCR value. The user has total control over
the integration period of the measurement. The LC (Load Count) bit or pin is used to set the integration
period.
1.4 GENERATING ERRORS
Via the Error Insertion Register (EIR), the user can intentionally inject a particular error rate into the
transmitted data stream. Injecting errors allows users to stress communication links and to check the
functionality of error monitoring equipment along the path.
DS21372
1.5 POWER-UP SEQUENCE
On power-up, the registers in the DS21372 will be in a random state. The user must program all the
internal registers to a known state before proper operation can be insured.
DS21372 FUNCTIONAL BLOCK DIAGRAM Figure 1
DS21372 PATTERN GENERATION BLOCK DIAGRAM Figure 2
NOTES:
1. Tap A always equals length (N-1) of pseudorandom or repetitive pattern.
2. Tab B can be programmed to any feedback tap for pseudorandom pattern generation.
RLOS
DS21372
DETAILED PIN DESCRIPTION Table 1
PINSYMBOLTYPEDESCRIPTION
1TLITransmit Load. A positive-going edge loads the pattern generator with
the contents of the Pattern Set Registers. The MSB of the repetitive or
pseudorandom pattern appears at TDATA after the third positive edge of
TCLK from asserting TL. TL is logically OR’ed with PCR.7 and should
be tied to VSS if not used. See Figure 8 for timing information.AD0I/OData Bus. An 8-bit multiplexed address/data bus.AD1I/OData Bus. An 8-bit multiplexed address/data bus.TESTITest. Set high to 3-state all output pins (INT, ADx, TDATA, RLOS).
Should be tied to VSS to enable all outputs.
5VSS-Signal Ground. 0.0V. Should be tied to local ground plane.AD2I/OData Bus. An 8-bit multiplexed address/data bus.AD3I/OData Bus. An 8-bit multiplexed address/data bus.AD4I/OData Bus. An 8-bit multiplexed address/data bus.AD5I/OData Bus. An 8-bit multiplexed address/data bus.AD6I/OData Bus. An 8-bit multiplexed address/data bus.AD7I/OData Bus. An 8-bit multiplexed address/data bus.VSS-Signal Ground. 0.0V. Should be tied to local ground plane.VDD-Positive Supply. 3.3V.BTSIBus Type Select. Strap high to select Motorola bus timing; strap low to
select Intel bus timing. This pin controls the function of the RD (DS),
ALE(AS), and WR(R/W) pins. If BTS = 1, then these pins assume the
function listed in parenthesis ().RD(DS)IRead Input (Data Strobe).CSIChip Select. Must be low to read or write the port.ALE(AS)IAddress Latch Enable (Address Strobe). A positive going edge serves
to demultiplex the bus.WR(R/W)IWrite Input (Read/Write).INTOAlarm Interrupt. Flags host controller during conditions defined in
Status Register. Active low, open drain output.VDD-Positive Supply. 3.3V.VSS-Signal Ground. 0.0V. Should be tied to local ground plane.LCILoad Count. A positive-going edge latches the current bit and bit error
count into the user accessible BCR and BECR registers and clears the
internal count registers. LC is logically OR’ed with control bit PCR.4.
Should be tied to VSS if not used.RLOSOReceive Loss Of Sync. Indicates the real time status of the receive
synchronizer. Active high output.
DS21372
PINSYMBOLTYPEDESCRIPTIONRLIReceive Load. A positive-going edge loads the previous 32 bits of data
received at RDATA into the Pattern Receive Registers. RL is logically
OR’ed with control bit PCR.3. Should be tied to VSS if not used.RDATAIReceive Data. Received NRZ serial data, sampled on the rising edge of
RCLK.RDISIReceive Disable. Set high to prevent the data at RDATA from being
sampled. Set low to allow bits at RDATA to be sampled. Should be tied
to VSS if not used. See Figure 6 for timing information. All receive side
operations are disabled when RDIS is high.RCLKIReceive Clock. Input clock from transmission link. 0 to 20 MHz. Can
be a gapped clock. Fully independent from TCLK.VDD-Positive Supply. 3.3V.VSS-Signal Ground. 0.0V. Should be tied to local ground plane.TCLKITransmit Clock. Transmit demand clock. 0 to 20 MHz. Can be a
gapped clock. Fully independent of RCLK.TDISITransmit Disable. Set high to hold the current bit being transmitted at
TDATA. Set low to allow the next bit to appear at TDATA. Should be
tied to VSS if not used. See Figure 7 for timing information. All transmit
side operations are disabled when TDIS is high.TDATAOTransmit Data. Transmit NRZ serial data, updated on the rising edge of
TCLK.
DS21372 REGISTER MAP Table 2
ADDRESSR/WREGISTER NAMEADDRESSR/WREGISTER NAMER/WPattern Set Register 3.0CRBit Error Counter Register 3.R/WPattern Set Register 2.0DRBit Error Counter Register 2.R/WPattern Set Register 1.0ERBit Error Counter Register 1.R/WPattern Set Register 0.0FRBit Error Counter Register 0.R/WPattern Length Register.10RPattern Receive Register 3.R/WPolynomial Tap Register.11RPattern Receive Register 2.R/WPattern Control Register.12RPattern Receive Register 1.R/WError Insert Register.13RPattern Receive Register 0.RBit Counter Register 3.14RStatus Register.RBit Counter Register 2.15R/WInterrupt Mask Register.RBit Counter Register 1.1CR/WTest Register (see note 1)RBit Counter Register 0.
NOTE:
DS21372
2. PARALLEL CONTROL INTERFACE
The DS21372 is controlled via a multiplexed bi-directional address/data bus by an external
microcontroller or microprocessor. The DS21372 can operate with either Intel or Motorola bus timing
configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will
be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in the A.C.
Electrical Characteristics for more details. The multiplexed bus on the DS21372 saves pins because the
address information and data information share the same signal paths. The addresses are presented to the
pins in the first portion of the bus cycle and data will be transferred on the pins during second portion of
the bus cycle. Addresses must be valid prior to the falling edge of ALE (AS), at which time the DS21372
latches the address from the AD0 to AD7 pins. Valid write data must be present and held stable during
the later portion of the DS or WR pulses. In a read cycle, the DS21372 outputs a byte of data during the
latter portion of the DS or RD pulses. The read cycle is terminated and the bus returns to a high
impedance state as RD transitions high in Intel timing or as DS transitions low in Motorola timing. The
DS21372 can also be easily connected to non-multiplexed buses. RCLK and TCLK are used to update
counters and load transmit and receive pattern registers. At slow clock rates, sufficient time must be
allowed for these port operations.
3. PATTERN SET REGISTERS
The Pattern Set Registers (PSR) are loaded each time a new pattern (whether it be pseudorandom or
repetitive) is to be generated. When a pseudorandom pattern is generated, all four PSRs must be loaded
with FF Hex. When a repetitive pattern is to be created, the four PSRs are loaded with the pattern that is
to be repeated. Please see Tables 4 and 5 for some programming examples.
PATTERN SET REGISTERS
(MSB) (LSB)
PS31PS30PS29PS28PS27PS26PS25PS24PSR3 (addr.=00 Hex)
PS23PS22PS21PS20PS19PS18PS17PS16PSR2 (addr.=01 Hex)
PS15PS14PS13PS12PS11PS10PS9PS8PSR1 (addr.=02 Hex)
PS7PS6PS5PS4PS3PS2PS1PS0PSR0 (addr.=03 Hex)
4. PATTERN LENGTH REGISTER
Length Bits LB4 to LB0 determine the length of the pseudorandom polynomial or programmable
repetitive pattern that is generated and detected. With the pseudorandom patterns, the “Tap A” feedback
position of the pattern generator is always equal to the value in the Pattern Length Register (PLR). Please
refer to Figure 2 for a block diagram of the pattern generator and to Tables 4 and 5 for some
programming examples.
DS21372
PLR: PATTERN LENGTH REGISTER (ADDRESS=04 HEX)
(MSB) (LSB)--LB4LB3LB2LB1LB0
SYMBOLPOSITIONNAME AND DESCRIPTIONPLR1.7Not Assigned. Should be set to 0 when written to.PLR1.6Not Assigned. Should be set to 0 when written to.PLR1.5Not Assigned. Should be set to 0 when written to.
LB4PLR1.4Length Bit 4.
LB3PLR1.3Length Bit 3.
LB2PLR1.2Length Bit 2.
LB1PLR1.1Length Bit 1.
LB0PLR1.0Length Bit 0.
5. POLYNOMIAL TAP REGISTER
Polynomial Tap Bits PT4 - PT0 determine the feedback position of Tap B connected to the XOR input of
the pattern generator. Feedback Tap B provides one of two feedback paths within the pattern generator.
Please refer to Figure 2 for a block diagram of the pattern generator and to Tables 4 and 5 for register
programming examples.
PTR: POLYNOMIAL TAP REGISTER (ADDRESS=05 HEX)
(MSB) (LSB)--PT4PT3PT2PT1PT0
SYMBOLPOSITIONNAME AND DESCRIPTION
-PTR.7Not Assigned. Should be set to 0 when written to.
-PTR.6Not Assigned. Should be set to 0 when written to.
-PTR.5Not Assigned. Should be set to 0 when written to.
PT4PTR.4Polynomial Tap Bit 4.
PT3PTR.3Polynomial Tap Bit 3.
PT2PTR.2Polynomial Tap Bit 2.
PT1PTR.1Polynomial Tap Bit 1.
PT0PTR.0Polynomial Tap Bit 0.
6. PATTERN CONTROL REGISTER
The Pattern Control Register (PCR) is used to configure the operating parameters of the DS21372 and to
control the patterns being generated and received. Also the PCR is used to control the pattern
synchronizer and the error and bit counters.
DS21372
PCR: PATTERN CONTROL REGISTER (ADDRESS=06 HEX)
(MSB) (LSB)QRSSPSLCRLSYNCERESYNCLPBK
SYMBOLPOSITIONNAME AND DESCRIPTIONPCR.7Transmit Load. A low to high transition loads the pattern
generator with the contents of the Pattern Set Registers. PCR.7 is
logically ORed with the input pin TL. Must be cleared and set
again for subsequent loads.
QRSSPCR.6Zero Suppression Select. Forces a 1 into the pattern whenever
the next 14 bit positions are all 0s. Should only be set when
using the QRSS pattern.
0 = Zero suppression disabled
1 = Zero suppression enabledPCR.5Pattern Select.
0 = Repetitive Pattern
1 = Pseudorandom PatternPCR.4Latch Count Registers. A low to high transition latches the bit
and error counts into the user accessible registers BCR and
BECR and clears the internal register count. PCR.4 is logically
OR’ed with input pin LC. Must be cleared and set again for
subsequent loads.PCR.3Receive Data Load. A transition from low to high loads the
previous 32 bits of data received at RDATA into the Pattern
Receive Registers (PRR). PCR.3 is logically OR’ed with input
pin RL. Must be cleared and set again for subsequent latches.
SYNCEPCR.2SYNC Enable.
0 = auto resync is enabled.
1 = auto resync is disabled.
RESYNCPCR.1Initiate Manual Resync Process. A low to high transition will
force the DS21372 to resynchronize to the incoming pattern at
RDATA. Must be cleared and set again for a subsequent resync.
LPBKPCR.0Transmit/Receive Loopback Select. When enabled, the
RDATA input is disabled; TDATA continues to output data as
normal. See Figure 1.
0 = loopback disabled
1 = loopback enabled
DS21372
7. ERROR INSERT REGISTER
The Error Insertion Register (EIR) controls circuitry within the DS21372 that allows the generated
pattern to be intentionally corrupted. Bit errors can be inserted automatically at regular intervals by
properly programming the EIR0 to EIR2 bits or bit errors can be inserted at random (under
microcontroller control) via the EIR.3 bit.
EIR: ERROR INSERT REGISTER (ADDRESS=07 HEX)
(MSB) (LSB)-TINVRINVSBEEIR2EIR1EIR0
SYMBOLPOSITIONNAME AND DESCRIPTION
-EIR.7Not Assigned. Should be set to 0 when written to.
-EIR.6Not Assigned. Should be set to 0 when written to.
TINVEIR.5Transmit Data Inversion Select.
0 = do not invert data to be transmitted at TDATA
1 = invert data to be transmitted at TDATA
RINVEIR.4Receive Data Inversion Select.
0 = do not invert data received at RDATA
1 = invert data received at RDATA
SBEEIR.3Single Bit Error Insert. A low to high transition will create a
single bit error. Must be cleared and set again for a subsequent
bit error to be inserted. Can be used to accomplish rates not
addressed in Table 3 (e.g., BER of less than 10-7).
EIB2EIR.2Error Insert Bit 2. See Table 3.
EIB1EIR.1Error Insert Bit 1. See Table 3.
EIB0EIR.0Error Insert Bit 0. See Table 3.
ERROR BIT INSERTION Table 3
EIB2EIB1EIB0ERROR RATE INSERTED00no errors automatically inserted110-1010-2110-3010-4110-5010-6110-7
DS21372
PSEUDORANDOM PATTERN GENERATION (PCR.5=1) Table 4
PATTERN TYPEPTRPLRPSR3PSR2PSR1PSR0TINVRINV3 - 10002FFFFFFFF004 - 10003FFFFFFFF005 - 10104FFFFFFFF006 - 10405FFFFFFFF007 - 10006FFFFFFFF007 - 1 Fractional T1 LB Activate0306FFFFFFFF007 - 1 Fractional T1 LB Deactivate0306FFFFFFFF119 - 1 O.153 (511 type)0408FFFFFFFF0010 - 10209FFFFFFFF0011 – 1 O.152 and O.153 (2047 type)080AFFFFFFFF0015 - 1 O.1510D0EFFFFFFFF1117 - 10210FFFFFFFF0018 - 10611FFFFFFFF0020 - 1 O.1530213FFFFFFFF0020 - 1 O.151 QRSS (PCR.6=1)1013FFFFFFFF0021 - 10114FFFFFFFF0022 - 10015FFFFFFFF0023 - 1 O.1511116FFFFFFFF1125 - 10218FFFFFFFF0028 - 1021BFFFFFFFF0029 - 1011CFFFFFFFF0031 - 1021EFFFFFFFF0032 - 1 (see note below)101FFFFFFFFF00
DS21372
REPETITIVE PATTERN GENERATION (PCR.5=0) Table 5
PATTERN TYPEPTRPLRPSR3PSR2PSR1PSR0TINVRINV
all 1s0000FFFFFFFF00
all 0s0000FFFFFFFE00
alternating 1s and 0s0001FFFFFFFE00
double alternating 1s and 0s0003FFFFFFFC00
3 in 240017FF20002200
1 in 16000FFFFF000100
1 in 80007FFFFFF0100
1 in 40003FFFFFFF100
D4 Line Loopback Activate0004FFFFFFF000
D4 Line Loopback Deactivate0002FFFFFFFC00
Notes For Tables 4 and 5:
1. PTR = Polynomial Tap Register (address = 05)
2. PLR = Pattern Length Register (address = 04)
3. PSR3 = Pattern Set Register 3 (address = 00)
4. PSR2 = Pattern Set Register 2 (address = 01)
5. PSR1 = Pattern Set Register 1 (address = 02)
6. PSR0 = Pattern Set Register 0 (address = 03)
7. TINV = Transmit Data Inversion Select Bit (EIR.5)
8. RINV = Receive Data Inversion Select Bit (EIR.4)
9. For the 232 -1 pattern, the random pattern actually repeats every (4093 x 220) + 1046529 bits instead of32 - 1.
8. BIT COUNT REGISTERS
The Bit Count Registers (BCR3 to BCR0) comprise a 32-bit count of bits (actually RCLK cycles)
received at RDATA. BC31 is the MSB of the 32-bit count. The bit counter increments for each cycle of
RCLK when input pin RDIS is low. The bit counter is disabled during loss of SYNC. The Status Register
bit BCOF is set when this 32-bit register overflows. Upon an overflow condition, the user must clear the
BCR by either toggling the LC bit or pin. The DS21372 latches the bit count into the BCR registers and
clears the internal bit count when either the PCR.4 bit or the LC input pin toggles from low to high. The
bit count and bit error count (available via the BECRs) are used by an external processor to compute the
BER performance on a loop or channel basis.

Partno	Mfg	Dc	Qty	Available	Descript
DS21372	DS	N/a	24	avai	3.3V Bit Error Rate Tester (BERT)