DS21554-L ,3.3V/5V E1 Single-Chip TransceiversApplications meet all the latest E1 specifications, including ITU-T Fully Independent Transmit an ..
DS21554LB ,3.3V/5V E1 Single Chip Transceivers (SCT)FUNCTIONAL DESCRIPTION7 1.2. DOCUMENT REVISION HISTORY .8 2.
DS21554LB ,3.3V/5V E1 Single Chip Transceivers (SCT)Applications meet all the latest E1 specifications, including ITU-T Fully Independent Transmit an ..
DS21554LB+ ,3.3V/5V E1 Single Chip Transceivers (SCT) DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
DS21554LBN+ ,3.3V/5V E1 Single Chip Transceivers (SCT)Applications meet all the latest E1 specifications, including ITU-T Fully Independent Transmit an ..
DS21554LN ,3.3V/5V E1 Single-Chip TransceiversTABLE OF CONTENTS 1. INTRODUCTION...... 6 1.1.
DS21354L-DS21554L-DS21554-L-DS21554LN
3.3V/5V E1 Single-Chip Transceivers
GENERAL DESCRIPTION The DS21354/DS213554 single-chip transceivers
(SCTs) contain all the necessary functions to connect to
E1 lines. The devices are upward-compatible versions
of the DS2153 and DS2154 SCTs. The on-board
clock/data recovery circuitry coverts the AMI/HDB3 E1
waveforms to an NRZ serial stream. Both devices
automatically adjust to E1 22AWG (0.6mm) twisted-
pair cables from 0 to over 2km in length. They can
generate the necessary G.703 waveshapes for both 75�
coax and 120� twisted cables. The on-board jitter
attenuator (selectable to either 32 bits or 128 bits) can
be placed in either the transmit or receive data paths.
The framer locates the frame and multiframe
boundaries and monitors the data stream for alarms. It is
also used for extracting and inserting signaling data, Si,
and Sa-bit information. The on-board HDLC controller
can be used for Sa-bit links or DS0s. The devices
contain a set of internal registers that the user can
access to control the operation of the units. Quick
access through the parallel control port allows a single
controller to handle many E1 lines. The devices fully
meet all the latest E1 specifications, including ITU-T
G.703, G.704, G.706, G.823, G.732, and I.431, ETS
300 011, 300 233, and 300 166, as well as CTR12 and
CTR4.
PIN CONFIGURATION
FEATURES ��Complete E1 (CEPT) PCM-30/ISDN-PRI
Transceiver Functionality
��On-Board Long- and Short-Haul Line Interface for Clock/Data Recovery and Waveshaping
��32-Bit or 128-Bit Crystal-Less Jitter Attenuator
��Frames to FAS, CAS, CCS, and CRC4 Formats
��Integral HDLC Controller with 64-Byte Buffers
Configurable for Sa Bits, DS0, or Sub-DS0 Operation
��Dual Two-Frame Elastic Store Slip Buffers that
can Connect to Asynchronous Backplanes up to
8.192MHz
��Interleaving PCM Bus Operation
��8-Bit Parallel Control Port that can be used
Directly on Either Multiplexed or Nonmultiplexed Buses (Intel or Motorola)
��Extracts and Inserts CAS Signaling
��Detects and Generates Remote and AIS Alarms
��Programmable Output Clocks for Fractional E1, H0, and H12 Applications
��Fully Independent Transmit and Receive Functionality
��Full Access to Si and Sa Bits Aligned with
CRC-4 Multiframe
��Four Separate Loopback Functions for Testing
Functions
��Large Counters for Bipolar and Code Violations,
CRC4 Codeword Errors, FAS Word Errors, and E Bits
��IEEE 1149.1 JTAG-Boundary Scan Architecture
��Pin Compatible with DS2154/52/352/552 SCTs
��3.3V (DS21354) or 5V (DS21554) Supply; Low-Power CMOS
��100-pin LQFP package (14mm x 14mm)
ORDERING INFORMATION
DS21354/DS21554
3.3V/5V E1 Single-Chip Transceivers
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
TABLE OF CONTENTS
1. INTRODUCTION..................................................................................................................6 1.1. FUNCTIONAL DESCRIPTION..............................................................................................................................7
1.2. DOCUMENT REVISION HISTORY.............................................................................................................8
2. BLOCK DIAGRAM..............................................................................................................9
3. PIN DESCRIPTION............................................................................................................10 3.1. PIN FUNCTION DESCRIPTION................................................................................................................14 3.1.1. Transmit-Side Pins..............................................................................................................................14
3.1.2. Receive-Side Pins...............................................................................................................................17 3.1.3. Parallel Control Port Pins....................................................................................................................20
3.1.4. JTAG Test Access Port Pins...............................................................................................................22 3.1.5. Interleave Bus Operation Pins............................................................................................................22
3.1.6. Line Interface Pins..............................................................................................................................23 3.1.7. Supply Pins.........................................................................................................................................24
4. PARALLEL PORT.............................................................................................................25 4.1. REGISTER MAP........................................................................................................................................25
5. CONTROL, ID, AND TEST REGISTERS..........................................................................30 5.1. POWER-UP SEQUENCE..........................................................................................................................30 5.2. SYNCHRONIZATION AND RESYNCHRONIZATION...............................................................................32
5.3. FRAMER LOOPBACK...............................................................................................................................36 5.4. AUTOMATIC ALARM GENERATION........................................................................................................38
5.5. REMOTE LOOPBACK...............................................................................................................................40 5.6. LOCAL LOOPBACK...................................................................................................................................40
6. STATUS AND INFORMATION REGISTERS....................................................................43 6.1. CRC4 SYNC COUNTER............................................................................................................................45
7. ERROR COUNT REGISTERS...........................................................................................50 7.1. BPV OR CODE VIOLATION COUNTER...................................................................................................50 7.2. CRC4 ERROR COUNTER.........................................................................................................................51
7.3. E-BIT COUNTER.......................................................................................................................................51 7.4. FAS ERROR COUNTER.................................................................................................................................52
8. DS0 MONITORING FUNCTION........................................................................................53
9. SIGNALING OPERATION.................................................................................................56 9.1. PROCESSOR-BASED SIGNALING..........................................................................................................56
9.2. HARDWARE-BASED SIGNALING............................................................................................................58 9.2.1. Receive Side.......................................................................................................................................58
9.2.2. Transmit Side......................................................................................................................................59
10. PER-CHANNEL CODE GENERATION AND LOOPBACK...............................................60 10.1. TRANSMIT-SIDE CODE GENERATION................................................................................................60
10.1.1. Simple Idle Code Insertion and Per-Channel Loopback.....................................................................60 10.1.2. Per-Channel Code Insertion...............................................................................................................61
10.2. RECEIVE-SIDE CODE GENERATION...................................................................................................62
11. CLOCK BLOCKING REGISTERS.....................................................................................63
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
12. ELASTIC STORES OPERATION......................................................................................65 12.1. RECEIVE SIDE.......................................................................................................................................65
12.2. TRANSMIT SIDE.....................................................................................................................................65
13. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION..................................66 13.1. HARDWARE SCHEME...........................................................................................................................66 13.2. INTERNAL REGISTER SCHEME BASED ON DOUBLE FRAME.........................................................66
13.3. INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME....................................................68
14. HDLC CONTROLLER FOR THE SA BITS OR DS0.........................................................70 14.1. GENERAL OVERVIEW...........................................................................................................................70
14.2. HDLC STATUS REGISTERS..................................................................................................................71 14.3. BASIC OPERATION DETAILS...............................................................................................................72
14.3.1. Example: Receive an HDLC Message................................................................................................72 14.3.2. Example: Transmit an HDLC Message...............................................................................................72
14.4. HDLC REGISTER DESCRIPTION..........................................................................................................73
15. LINE INTERFACE FUNCTIONS........................................................................................80 15.1. RECEIVE CLOCK AND DATA RECOVERY.......................................................................................................81 15.2. TRANSMIT WAVESHAPING AND LINE DRIVING..............................................................................................81
15.3. JITTER ATTENUATOR..................................................................................................................................82 15.4. PROTECTED INTERFACES...........................................................................................................................86
15.5. RECEIVE MONITOR MODE..........................................................................................................................89
16. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT......................90 16.1. INSTRUCTION REGISTER.............................................................................................................................95
16.2. TEST REGISTERS.......................................................................................................................................96
17. INTERLEAVED PCM BUS OPERATION..........................................................................98 17.1. CHANNEL INTERLEAVE...............................................................................................................................99
17.2. FRAME INTERLEAVE...................................................................................................................................99
18. FUNCTIONAL TIMING DIAGRAMS................................................................................100 18.1. RECEIVE.................................................................................................................................................100 18.2. TRANSMIT...............................................................................................................................................104
19. OPERATING PARAMETERS..........................................................................................111
20. AC TIMING PARAMETERS AND DIAGRAMS...............................................................112 20.1. MULTIPLEXED BUS AC CHARACTERISTICS................................................................................................112
20.2. NONMULTIPLEXED BUS AC CHARACTERISTICS..........................................................................................115 20.3. RECEIVE-SIDE AC CHARACTERISTICS......................................................................................................117
20.4. TRANSMIT AC CHARACTERISTICS.............................................................................................................121
21. PACKAGE INFORMATION.............................................................................................124 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
LIST OF FIGURES Figure 2-1. DS21354/554 Block Diagram.............................................................................................................................9
Figure 15-1. Basic External Analog Connections..............................................................................................................83
Figure 15-2. Optional Crystal Connection...........................................................................................................................83
Figure 15-3. Jitter Tolerance.................................................................................................................................................84
Figure 15-4. Jitter Attenuation..............................................................................................................................................84
Figure 15-5. Transmit Waveform Template........................................................................................................................85
Figure 15-6. Protected Interface Example for the DS21554............................................................................................87
Figure 15-7. Protected Interface Example for the DS21354............................................................................................88
Figure 15-8. Typical Monitor Port Application....................................................................................................................89
Figure 16-1. JTAG Functional Block Diagram....................................................................................................................91
Figure 16-2. TAP Controller State Diagram........................................................................................................................94
Figure 17-1. IBO Basic Configuration Using Four SCTs..................................................................................................99
Figure 18-1. Receive-Side Timing......................................................................................................................................100
Figure 18-2. Receive-Side Boundary Timing (with Elastic Store Disabled).................................................................100
Figure 18-3. Receive-Side 1.544MHz Boundary Timing (with Elastic Store Enabled)..............................................101
Figure 18-4. Receive-Side 2.048MHz Boundary Timing (with Elastic Store Enabled)..............................................101
Figure 18-5. Receive-Side Interleave Bus Operation, Byte Mode................................................................................102
Figure 18-6. Receive-Side Interleave Bus Operation, Frame Mode.............................................................................103
Figure 18-7. Transmit-Side Timing....................................................................................................................................104
Figure 18-8. Transmit-Side Boundary Timing (with Elastic Store Disabled)................................................................104
Figure 18-9. Transmit-Side 1.544MHz Boundary Timing (with Elastic Store Enabled).............................................105
Figure 18-10. Transmit-Side 2.048MHz Boundary Timing (with Elastic Store Enabled)...........................................105
Figure 18-11. Transmit-Side Interleave Bus Operation, Byte Mode.............................................................................106
Figure 18-12. Transmit-Side Interleave Bus Operation, Frame Mode..........................................................................107
Figure 18-13. G.802 Timing................................................................................................................................................108
Figure 18-14. DS21354/DS21554 Framer Synchronization Flowchart........................................................................109
Figure 18-15. DS21354/DS21554 Transmit Data Flow..................................................................................................110
Figure 20-1. Intel Bus Read Ac Timing (BTS = 0/MUX = 1)...........................................................................................113
Figure 20-2. Intel Bus Write Timing (BTS = 0/MUX = 1).................................................................................................113
Figure 20-3. Motorola Bus AC Timing (BTS = 1/MUX = 1)............................................................................................114
Figure 20-4. Intel Bus Read AC Timing (BTS = 0/MUX = 0)..........................................................................................115
Figure 20-5. Intel Bus Write AC Timing (BTS = 0/MUX = 0)..........................................................................................116
Figure 20-6. Motorola Bus Read AC Timing (BTS = 1/MUX = 0)..................................................................................116
Figure 20-7. Motorola Bus Write AC Timing (BTS = 1/MUX = 0)..................................................................................116
Figure 20-8. Receive-Side AC Timing...............................................................................................................................118
Figure 20-9. Receive System Side AC Timing.................................................................................................................119
Figure 20-10. Receive Line Interface AC Timing.............................................................................................................120
Figure 20-11. Transmit-Side AC Timing............................................................................................................................122
Figure 20-12. Transmit System Side AC Timing..............................................................................................................123
Figure 20-13. Transmit Line Interface Side AC Timing...................................................................................................123
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
LIST OF TABLES Table 3-1. Pin Description Sorted by Pin Number.............................................................................................................10
Table 3-2. Pin Description by Symbol.................................................................................................................................12
Table 4-1. Register Map Sorted by Address......................................................................................................................25
Table 5-1. Device ID Bit Map................................................................................................................................................30
Table 5-2. SYNC/RESYNC Criteria.....................................................................................................................................32
Table 6-1. Alarm Criteria.......................................................................................................................................................46
Table 14-1. HDLC Controller Register List.........................................................................................................................70
Table 15-1. Line Build-Out Select in LICR for the DS21554............................................................................................81
Table 15-2. Line Build-Out Select in LICR for the DS21354............................................................................................82
Table 15-3. Transformer Specifications..............................................................................................................................82
Table 15-4. Receive Monitor Mode Gain............................................................................................................................89
Table 16-1. Instruction Codes for IEEE 1149.1 Architecture...........................................................................................95
Table 16-2. ID Code Structure..............................................................................................................................................96
Table 16-3. Device ID Codes................................................................................................................................................96
Table 16-4. Boundary Scan Control Bits.............................................................................................................................97
Table 17-1. IBO Master Device Select................................................................................................................................98
