DS21349Q ,3.3V T1/J1 Line Interface UnitTABLE OF CONTENTS 1. DETAILED DESCRIPTION.......4 2. OPERATING MODES......5 3. INITIALIZATION AND R ..
DS21349Q+ ,3.3V T1/J1 Line Interface UnitAPPLICATIONS Four CSU Filters from 0dB to -22.5dB Routers Transmit/Receive Performance Monitors ..
DS21352 ,3.3V DS21352 and 5V DS21552 T1 Single Chip TransceiversFUNCTIONAL DESCRIPTION....83.2 DOCUMENT REVISION HISTORY...104.
DS21352DK ,T1 Single-Chip Transceiver Design Kit Daughter CardFEATURES The DS21352 design kit is an easy-to-use evaluation Demonstrates Key Functions of DS2135 ..
DS21352G ,3.3V DS21352 and 5V DS21552 T1 Single Chip Transceivers3.3V DS21352 and 5V DS21552T1 Single-Chip Transceivers
DS21352L ,3.3V DS21352 and 5V DS21552 T1 Single-Chip TransceiversFEATURES PIN ASSIGNMENT Complete DS1/ISDN–PRI/J1 transceiver functionality Long and Short haul L ..
DS21349Q-DS21349Q+
3.3V T1/J1 Line Interface Unit
GENERAL DESCRIPTION The DS21349 is a fully integrated LIU for long-
haul or short-haul T1 applications over twisted-
pair installations. It interfaces to two twisted-pair
lines—one pair for transmit and one pair for
receive through an appropriate network
interface. The device can be configured for
control through software or hardware mode.
Software control is accomplished over a serial
port in hardware mode; individual pin settings
allow stand-alone operation. The device provides
a precise, crystal-less jitter attenuator that can be
placed in either the transmit or receive path.
APPLICATIONS Routers
Data Service Units (DSUs)
Channel Service Units (CSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
PIN CONFIGURATION
FEATURES � Fully Integrated Line Interface Unit (LIU) � Pin Compatible with LevelOne LXT362 � Supports Both Long Haul and Short Haul � Crystal-Less Jitter Attenuator � Jitter Attenuator Programmable for Transmit
or Receive Path � Meets ANSI T1.102, T1.403, T1.408, and
AT&T 62411 � Usable Receive Sensitivity of 0dB to -36dB
That Allows the Device to Operate on
0.63mm (22AWG) Cables Up to 6k Feet in
Length � Five Line Build-Out Settings for Short-Haul
Applications � Four CSU Filters from 0dB to -22.5dB � Transmit/Receive Performance Monitors
with Driver-Fail, Monitor-Open, and Loss-
of-Signal Outputs � Bipolar or NRZ Interface � Programmable B8ZS Encoder/Decoder � QRSS Generator/Detector � Local, Remote, and Analog Loopbacks � Generates and Detects In-Band Loop-Up and
Loop-Down Codes � Serial Interface Provides Access to Control
Registers
ORDERING INFORMATION
PART TEMP
RANGE
PIN-
PACKAGE DS21349Q 0°C to +70°C 28 PLCC
DS21349Q+ 0°C to +70°C 28 PLCC
DS21349QN -40°C to +85°C 28 PLCC
DS21349QN+-40°C to +85°C 28 PLCC
+Denotes lead-free/RoHS-compliant package.
10
11
25
24
23
22
21
20
19
12 13 14 15 16 17 18
4 3 2 1 28 27 26
DS21349 TOP VIEW
PLCC
DS21349
3.3V T1/J1 Line Interface Unit
DEMO KIT AVAILABLE
DS21349
TABLE OF CONTENTS
1. DETAILED DESCRIPTION.................................................................................................4
2. OPERATING MODES.........................................................................................................5
3. INITIALIZATION AND RESET............................................................................................9
4. REGISTER DEFINITIONS..................................................................................................10
5. TRANSMITTER...................................................................................................................16 5.1 TRANSMIT DIGITAL DATA INTERFACE...............................................................................................16
5.2 TRANSMIT MONITORING..................................................................................................................16
5.3 TRANSMIT IDLE MODE.....................................................................................................................16
5.4 TRANSMIT PULSE SHAPE................................................................................................................16
6. RECEIVER..........................................................................................................................17 6.1 RECEIVE EQUALIZER.......................................................................................................................17
6.2 RECEIVE DATA RECOVERY..............................................................................................................17
6.3 RECEIVE DIGITAL-DATA INTERFACE.................................................................................................17
6.4 RECEIVE MONITOR MODE...............................................................................................................17
7. JITTER ATTENUATION.....................................................................................................18
8. HARDWARE MODE...........................................................................................................18
9. SOFTWARE MODE............................................................................................................19 9.1 INTERRUPT HANDLING....................................................................................................................19
10. DIAGNOSTIC MODE OPERATION....................................................................................22 10.1 LOOPBACK MODES.........................................................................................................................22
10.1.1 Local Loopback (LLB)...................................................................................................................................22
10.1.2 Analog Loopback (ALB)................................................................................................................................22
10.1.3 Remote Loopback (RLB)..............................................................................................................................22
10.1.4 Network Loopback........................................................................................................................................23
10.1.5 Dual Loopback..............................................................................................................................................23
10.2 INTERNAL PATTERN GENERATION AND DETECTION..........................................................................24
10.2.1 Transmit Alarm-Indication Signal (TAIS)......................................................................................................24
10.2.2 Quasirandom Signal Source (QRSS)...........................................................................................................24
10.2.3 In-Band Network Loop-Up or Loop-Down Code Generator.........................................................................25
10.3 ERROR INSERTION AND DETECTION.................................................................................................25
10.3.1 Bipolar Violation Insertion (INSBPV)............................................................................................................25
10.3.2 Logic Error Insertion (INSLE).......................................................................................................................25
10.3.3 Logic Error Detection (QPD).........................................................................................................................25
10.3.4 Bipolar Violation Detection (BPV).................................................................................................................25
10.4 ALARM MONITORING.......................................................................................................................26
10.4.1 Receive-Carrier Loss (RCL).........................................................................................................................26
10.4.2 Alarm-Indication-Signal Detection (AIS).......................................................................................................26
10.4.3 Driver-Fail Monitor-Open (DFMO)................................................................................................................26
10.4.4 Jitter Attenuator Limit Trip (JALT).................................................................................................................26
10.5 OTHER DIAGNOSTIC REPORTS........................................................................................................26
10.5.1 Receive Line-Attenuation Indication.............................................................................................................26
11. NETWORK INTERFACE....................................................................................................27
12. DC CHARACTERISTICS....................................................................................................31
13. PACKAGE INFORMATION................................................................................................35 13.1 28-PIN PLCC (56-G4001-001)......................................................................................................35
DS21349
LIST OF FIGURES Figure 1-1. Block Diagram.......................................................................................................................................4
Figure 2-1. Hardware Mode Pinout........................................................................................................................6
Figure 2-2. Serial Port Mode Pinout.......................................................................................................................6
Figure 9-1. Serial Data Port Operation for Read Access..................................................................................20
Figure 9-2. Serial Data Port Operation for Write Access..................................................................................20
Figure 10-1. Loopbacks in the DS21349 Block Diagram..................................................................................24
Figure 11-1. Basic Network Interface..................................................................................................................28
Figure 11-2. T1 Transmit Pulse Template..........................................................................................................29
Figure 11-3. Jitter Tolerance.................................................................................................................................30
Figure 11-4. Jitter Attenuation...............................................................................................................................30
Figure 12-1. Serial Bus Read Timing (MODE1 = 1)..........................................................................................32
Figure 12-2. Serial Bus Write Timing (MODE1 = 1)..........................................................................................32
Figure 12-3. AC Characteristics for Receive Side.............................................................................................33
Figure 12-4. AC Characteristics for Transmit Side............................................................................................34
LIST OF TABLES Table 2-A. Operating Modes...................................................................................................................................5
Table 2-B. Control Pins for Hardware and Software Modes..............................................................................5
Table 2-C. Signal Descriptions...............................................................................................................................7
Table 4-A. Register Map........................................................................................................................................10
Table 4-B. Register Bit Positions..........................................................................................................................10
Table 4-C. Jitter Attenuator Selection..................................................................................................................11
Table 4-D. Line Code and Interface Selection...................................................................................................11
Table 4-E. Line Build-Out Selection.....................................................................................................................11
Table 4-F. Data Pattern Selection........................................................................................................................12
Table 9-A. CLKE Pin Selection.............................................................................................................................19
Table 9-B. Control and Operation Mode Selection............................................................................................21
Table 10-A. Diagnostic Modes..............................................................................................................................22
Table 11-A. Specifications for Receive Transformer.........................................................................................27
Table 11-B. Specifications for Transmit Transformer........................................................................................27
Table 11-C. Transformer Turns Ratio vs. Series Resistance..........................................................................27
DS21349
1. DETAILED DESCRIPTION The DS21349 is a complete T1 line interface unit (LIU) for short-haul and long-haul applications.
Receive sensitivity adjusts automatically to the incoming signal and can be limited to -18dB, -26dB, or
-36dB. The device can generate the necessary DSX-1 line build-outs or CSU line build-outs of 0dB,
-7.5dB, -15dB, and -22.5dB. The on-board crystal-less jitter attenuator requires a 1.544MHz reference
clock. The jitter attenuator FIFO is selectable to either 32 bits or 128 bits in depth and can be placed in
either the transmit or receive data paths. The DS21349 has diagnostic capabilities such as loopbacks and
QRSS pattern generation and detection. The device can also generate and detect the in-band loop-up and
loop-down codes specified in AT&T 62411. The device can be configured for control using a serial
interface, or for hardware mode. The device fully meets all of the latest T1 specifications including ANSI
T1.102-1999, ANSI T1.403-1999, ANSI T1.408, and AT&T 62411.
Figure 1-1. Block Diagram l L
itter
tten
uator
TRING
TTIP
RRING
RTIP
riv
ilte
ilte
/ D
rro
r In
TPOS
TCLK
TNEGQ
RPOS
RCLK
RNEG
RCL/QPD
NLOOP
Power connections Hardware Interface Serial Interface
INT
ASEL1L2L3
LLB
it A
VCO / PLL
DS21349
2. OPERATING MODES The DS21349 has several pins with multiple functions and names according to the selected operating
mode. These operating modes are summarized in the tables below.
Table 2-A. Operating Modes
QRSS DISABLED QRSS ENABLED PIN BIPOLAR NRZ BIPOLAR NRZ 1 MCLK
2 TCLK
3 TPOS TDATA INSLER
4 TNEG INSBPV INSBPV RNEG BPV RNEG BPV RPOS RDATA RPOS RDATA
8 RCLK
13 TTIP
16 TRING
19 RTIP
20 RRING
Control pins are affected by serial port and hardware modes.
Table 2-B. Control Pins for Hardware and Software Modes
HARDWARE MODE SERIAL PORT MODE PIN NRZ QRSS NRZ QRSS 5 MODE1 MODE1
9 MODE0 MODE0
11 JASEL N.C.
12 RCL RCL/QPD RCL RCL/QPD
23 L0 INT
24 L1 SDI
25 L2 SDO
17 L3 N.C.
18 NLOOP NLOOP
26 RLB NLB CS
27 LLB ALB SCLK
28 TAIS QRSS CLKE
DS21349
Figure 2-1. Hardware Mode Pinout
Figure 2-2. Serial Port Mode Pinout 1314151617183212726
GND
VDD
RRING
RTIP
MODE1
RNEG
RPOS
RCLK
MODE0
VSM
JASEL
GND
VDD
DS21349 1314151617183212726
SDO
SDI
INT
GND
VDD
RRING
RTIP
MODE1
RNEG
RPOS
RCLK
MODE0
VSM
N/C
GND
VDD
OOP
DS21349
DS21349
Table 2-C. Signal Descriptions
PIN NAME I/O FUNCTION MCLK I Master Clock. A 1.544MHz clock source with TTL levels is applied at this pin. This
clock is used internally for both clock/data recovery and for jitter attenuation.
2 TCLK I Transmit Clock. A 1.544MHz primary clock. Used to clock data through the transmit
side formatter. Can be sourced internally by MCLK or RCLK.
TPOS Transmit Positive Data. Sampled on the falling edge of TCLK for data to be
transmitted out onto the line.
TDATA Transmit NRZ Data. Sampled on the falling edge of TCLK for data to be transmitted
onto the line. 3
INSLER
Transmit Insert Logic Error. Rising edge on INSLER inserts a logic error into the
outbound QRSS pattern. Sampled on falling edge of TCLK.
TNEG Transmit Negative Data. Sampled on the falling edge of TCLK for data to be
transmitted out onto the line. 4
INSBPV Transmit Insert Bipolar Violation. INSBPV is sampled on the falling edge of TCLK.
Rising edge inserts one BPV.
5 MODE1 I2 Mode Select 1. Connect low to select hardware mode. Connect high to select serial
port mode. See also MODE0.
RNEG
Receive Negative Data. Updated on the rising edge (CCR2.0 = 0) or the falling edge
(CCR2.0 = 1) of RCLK with the bipolar data out of the line interface. Always valid
on rising edge of RCLK in hardware mode. 6
BPV
Receive Bipolar Violation. Transitions high for one clock cycle marking an inbound
bipolar violation. Valid on rising edge of RCLK.
RPOS
Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or the falling edge
(CCR2.0 = 1) of RCLK with bipolar data out of the line interface. Always valid on
rising edge of RCLK in hardware mode.
RDATA Receive Data. RDATA is the NRZ output from the line interface. Set NRZE
(CCR1.6) to a 1 for NRZ applications. In NRZ mode, data is output on RPOS while a
received error causes a positive-going pulse synchronous with RCLK at RNEG
(Section 6). RCLK O Receive Clock. Buffered recovered clock from the line. Synchronous to MCLK in
absence of signal at RTIP and RRING.
9 MODE0 I2 Mode Select 0. Set high to disable all output pins (including the serial control port).
Set low for normal operation. Useful in board level testing. See also MODE1.
10 VSM I Voltage Supply Mode. Connect high for 3.3V operation. Has 10kΩ pullup.
11 JASEL I2
Jitter Attenuator Select
0 = Place the jitter attenuator on the transmit side
1 = Place the jitter attenuator on the receive side
Float = Disable jitter attenuator
Not used in software mode
RCL Receive Carrier Loss. An output that toggles high during a receive carrier loss.
12
QPD QPD. Output high when QRSS detector is searching for QRSS data pattern. Output
high for one-half clock cycle on bit error. Connect to external counter to count bit
errors.
13/
16
TTIP/
TRING O Transmit Tip and Ring. Analog line driver outputs. These pins connect through a
step-up transformer to the line (Section 5).
DS21349
PIN NAME I/O FUNCTION 17 L3 I LBO3. LBO0 through LBO3 are used to select transmitter output pulse, and receiver
gain.
18 NLOOP O
Network Loopback Active. Output high when RLB is activated by in-band loop-up
command present for 5 seconds. Output is reset when RLP is deactivated by in-band
loop-down command present for 5 seconds. Activation of remote loopback through
hardware pin 26 or control bit RLB releases the NLOOP output.
19/
20
RTIP/
RRING I Receive Tip and Ring. Analog inputs for clock recovery circuitry. These pins connect
through a 1:1 transformer to the line (Section 6).
21 VDD — Positive Supply. 3.3V ±5%. See also VSM pin 10.
22 VSS — Signal Ground
L0 LBO0. LBO0 through LBO3 are used to select transmitter output pulse, and receiver
gain. 23
INT
I/O
INT. Used to alert the host when one or more bits are set in the status register.
L1 LBO1. LBO0 through LBO3 are used to select transmitter output pulse, and receiver
gain. 24
SDI Serial Data Input. Input for serial address and data stream. Sampled on rising of
SCLK.
L2 LBO2. LBO0 through LBO3 are used to select transmitter output pulse, and receiver
gain.
25
SDO Serial Data Output. Updated on falling edge of SCLK if CLKE is connected high.
Updated on rising edge of SCLK if CLKE is connected low. SDO is high-Z during
write cycle or when CS is high.
RLB
Remote Loopback. Used to invoke remote loopback. When held high, the transmitter
inputs are ignored and inbound data received at RTIP and RRING is routed to the
transmitter outputs, TTIP and TRING and transmitted at the inbound recovered clock
rate.
NLB Network Loopback. Enables network loopback detection when RLB floats.
26
CS 2
Chip Select. Must be low to read or write to the device. CS is an active-low signal.
LLB
Local Loopback. Used to invoke local loopback. When held high, digital inputs
TPOS and TNEG are looped back to RPOS and RNEG, through the jitter attenuator
if enabled. Floating this input invokes analog loopback. The analog output signal at
TTIP and TRING is routed to the receive inputs RTIP and RRING.
27
SCLK 2
Serial Clock Input. Input clock to operate serial port. Max clock rate, 2.048MHz.
TAIS Transmit AIS. Input high forces transmitter to output unframed all ones. Unavailable
in remote loopback.
QRSS QRSS. Floating this pin enables QRSS pattern generator and detector. Input low
enables normal transmission of data.
28
CLKE 2 Clock Edge Select
0 = Update RNEG/RPOS on falling edge of RCLK, SDO updated on rising edge of
SCLK.
1 = Update RNEG/RPOS on rising edge of RCLK, SDO updated on falling edge of
SCLK.
Note 1: G.703 requires an accuracy of ±50ppm for T1. TR62411 and ANSI specifications require an accuracy of ±32ppm for T1 interfaces.
Note 2: Input pins have three operating modes.
DS21349
3. INITIALIZATION AND RESET During power-up, all control registers are cleared, disabling the transmitter outputs. The device requires a
master clock supplied to the MCLK input pin to operate the PLL. This master clock must be independent,
free-running, and jitter free.
A reset initializes the status and state machines for the RCL, AIS, NLOOP, and QRSS blocks. Under
software control, setting the RESET bit (CR2.7) clears all registers. Allow up to 100ms for the receiver to
recover from initialization.
DS21349
4. REGISTER DEFINITIONS The DS21349 contains eight registers for configuring the device and reading status. These are accessible
using the serial port. Table 4-A lists the register names and addresses.
Reading or writing to the internal registers requires writing one address/command byte prior to
transferring register data. The first bit written (LSb) of the address/command byte specifies whether the
access is a read (1) or a write (0). The next 6 bits identify the register address.
The last bit (MSb) of the address/command byte is the burst mode bit. When the burst bit is enabled (set
to 1) and a READ operation is performed, addresses 10h through 17h are read sequentially, starting at
address 10h. And when the burst bit is enabled and a WRITE operation is performed, addresses 10h
through 17h are written sequentially, starting at address 10h. Burst operation is stopped once address 17h
is read. All data transfers are initiated by driving the CS input low. All data transfers are terminated if the
CS input transitions high. Port control logic is disabled and SDO is tri-stated when CS is high.
Table 4-A. Register Map
REGISTER SYMBOL ADDRESS Control Register 1 CR1 B010000
Control Register 2 CR2 B010001
Control Register 3 CR3 B010010
Interrupt Mask Register IMR B010011
Transition Status Register TSR B010100
Status Register SR B010101
Information Register IR B010110
Control Register 4 CR4 B010111
Table 4-B. Register Bit Positions
SYMBOL 7 (MSb) 6 5 4 3 2 1 0 (LSb) CR1 JASEL1 JASEL0 ENCENBUNIENB L3 L2 L1 L0
CR2 RESET PAT1 PAT0 TAIS ENLOOP ALB LLB RLB
CR3 JA6HZ TPD — EQZMON20EQZMON26JA128 LIRST TAOZ
IMR Z16D JALT DFMO B8ZSD QRSS AIS NLOOP RCL
TSR Z16D JALT DFMO B8ZSD QRSS AIS NLOOP RCL
SR — — DFMO — QRSS AIS NLOOP RCL
IR RL3 RL2 RL1 RL0 LUP LDN TSCD LOTC
CR4 — — — — — RCL2048 XFMR2 XFMR1
Note: Set unused bits to 0 for normal operation.
DS21349
CR1 (B010000): Control Register 1
MSb LSb JASEL1 JASEL0 ENCENB UNIENB L3 L2 L1 L0
SYMBOL POSITION FUNCTION JASEL1 CR1.7 Jitter attenuator select (Table 4-C)
JASEL0 CR1.6 Jitter attenuator select (Table 4-C)
ENCENB CR1.5 B8ZS and NRZ control (Table 4-D)
UNIENB CR1.4 BPV and NRZ control (Table 4-D)
L3 CR1.3 Line build-out control (Table 4-E)
L2 CR1.2 Line build-out control (Table 4-E)
L1 CR1.1 Line build-out control (Table 4-E)
L0 CR1.0 Line build-out control (Table 4-E)
Table 4-C. Jitter Attenuator Selection
JASEL1 JASEL0 JITTER ATTENUATOR FUNCTION 0 1 Transmit path
1 1 Receive path
X 0 Disabled
Table 4-D. Line Code and Interface Selection
UNIENB ENCENB LINE CODE INTERFACE 0 0 AMI Bipolar
1 0 AMI NRZ
X 1 B8ZS NRZ
Table 4-E. Line Build-Out Selection
L3 L2 L1 L0 APPLICATION OUTPUT SIGNAL Rx GAIN (dB) 0 0 0 0 T1 Long Haul 0dB 36
0 0 1 0 T1 Long Haul -7.5dB 36
0 1 0 0 T1 Long Haul -15dB 36
0 1 1 0 T1 Long Haul -22.5dB 36
0 0 0 1 T1 Long Haul 0dB 26
0 0 1 1 T1 Long Haul -7.5dB 26
0 1 0 1 T1 Long Haul -15dB 26
0 1 1 1 T1 Long Haul -22.5dB 26
1 0 0 1 D4 Short Haul 6V 18 0 1 1 T1 Short Haul DSX-1 (0ft to 133ft) 18 1 0 0 T1 Short Haul DSX-1 (133ft to 266ft) 18 1 0 1 T1 Short Haul DSX-1 (266ft to 399ft) 18 1 1 0 T1 Short Haul DSX-1 (399ft to 533ft) 18 1 1 1 T1 Short Haul DSX-1 (533ft to 655ft) 18
DS21349
CR2 (B010001): Control Register 2
MSb LSb RESET PAT1 PAT0 TAIS ENLOOP ALB LLB RLB
SYMBOL POSITION FUNCTION RESET CR2.7 Resets device states and clears all registers.
PAT1 CR2.6 Selects output data pattern (Table 4-F).
PAT0 CR2.5 Selects output data pattern (Table 4-F).
TAIS CR2.4 0 = Transmit data normally
1 = Transmit unframed all ones
ENLOOP CR2.3 0 = Disable in-band loop-code detection
1 = Enable in-band loop-code detection
ALB CR2.2 0 = Disable analog loopback
1 = Enable analog loopback
LLB CR2.1 0 = Disable local loopback
1 = Enable local loopback
RLB CR2.0 0 = Disable remote loopback
1 = Enable remote loopback
Table 4-F. Data Pattern Selection
PAT0 PAT1 DATA SOURCE 0 0 TPOS/TNEG
0 1 Transmit QRSS 0 In-band loop-up 00001 1 In-band loop-down 001
CR3 (B010010): Control Register 3
MSb LSb JA6HZ TPD — EQZMON20 EQZMON26 JA128 LIRST TAOZ
SYMBOL POSITION FUNCTION JA6HZ CR3.7
0 = Set bandwidth of jitter attenuator to 3Hz
1 = Set bandwidth of jitter attenuator to 6Hz; not available if
JA128 = 1
TPD CR3.6 0 = Enable transmitter outputs
1 = Disable transmitter outputs
— CR3.5 —
EQZMON20 CR3.4 0 = Normal receiver operation
1 = Add 20dB of resistive gain to inbound signal
EQZMON26 CR3.3 0 = Normal receiver operation
1 = Add 26dB of resistive gain to inbound signal
JA128 CR3.2 0 = Jitter attenuator buffer depth = 32 bits
1 = Jitter attenuator buffer depth = 128 bits
LIRST CR3.1 0 = Normal operation
1 = Reset the receive LIU state machine
TAOZ CR3.0 0 = Disable transmit alternate 1s and 0s
DS21349
IMR (B010011): Interrupt Mask Register
MSb LSb Z16D JALT DFMO B8ZSD QRSS AIS NLOOP RCL
SYMBOL POSITION FUNCTION Z16D IMR.7 0 = Enable 16-zero detect interrupt
1 = Disable 16-zero detect interrupt
JALT IMR.6 0 = Enable jitter-attenuator limit-trip interrupt
1 = Disable jitter-attenuator limit-trip interrupt
DFMO IMR.5 0 = Enable driver-open interrupt
1 = Disable driver-open interrupt
B8ZSD IMR.4 0 = Enable B8ZS-detect interrupt
1 = Disable B8ZS-detect interrupt
QRSS IMR.3 0 = Enable QRSS interrupt
1 = Disable QRSS interrupt
AIS IMR.2 0 = Enable AIS interrupt
1 = Disable AIS interrupt
NLOOP IMR.1 0 = Enable network-loopback interrupt
1 = Disable network-loopback interrupt
RCL IMR.0 0 = Enable receive carrier-loss interrupt
1 = Disable receive carrier-loss interrupt
TSR (B010100): Transition Status Register
MSb LSb Z16D JALT DFMO B8ZSD QRSS AIS NLOOP RCL
SYMBOL POSITION FUNCTION Z16D TSR.7 Set when the receiver detects 16 consecutive 0s; cleared when
IMR.7 is cleared.
JALT TSR.6 Set when the jitter attenuator FIFO reaches to within 4 bits of its
limit; cleared when IMR.6 is cleared.
DFMO TSR.5 Set when SR.5 changes state; cleared when IMR.5 is cleared.
B8ZSD TSR.4 Set when the receiver detects B8ZS codewords; cleared when
IMR.4 is cleared.
QRSS TSR.3 Set when SR.3 changes state; cleared when IMR.3 is cleared.
AIS TSR.2 Set when SR.2 changes state; cleared when IMR.2 is cleared.
NLOOP TSR.1 Set when SR.1 changes state; cleared when IMR.1 is cleared.
RCL TSR.0 Set when SR.0 changes state; cleared when IMR.0 is cleared.
DS21349
SR (B010101): Status Register
MSb LSb — — DFMO — QRSS AIS NLOOP RCL
SYMBOL POSITION FUNCTION — SR.7 —
— SR.6 —
DFMO SR.5 Set when transmitter detects open circuit.
— SR.4 —
QRSS SR.3 Set when the QRSS pattern is present at the receiver.
AIS SR.2 Set when the AIS pattern is present at the receiver.
NLOOP SR.1 Set when the in-band loop-up code is present at the receiver.
RCL SR.0
Set when receiver has detected consecutive s set forth by CR4.2.
Cleared when the receiver detects 14 1s in a window of 112 clock
cycles.
IR (B010110): Information Register
MSb LSb RL3 RL2 RL1 RL0 LUP LDN TSCD LOTC
SYMBOL POSITION FUNCTION RL3 IR.7 —
RL2 IR.6 —
RL1 IR.5 —
RL0 IR.4 —
LUP IR.3 Set when in-band loop-up code is being received.
LDN IR.2 Set when in-band loop-down code is being received.
TSCD IR.1 Set when transmitter detects a short circuit.
LOTC IR.0 Set when TCLK has not transitioned for approximately 5µs.
Receive Level Indication: RL0 is the LSB and RL3 is the MSB of a 4-bit nibble that is used to indicate the inbound
signal strength. Convert the binary to decimal and multiply by -2.5dB. The result indicates the approximate
attenuation seen at the receiver inputs.
DS21349
CR4 (B010111): Control Register 4
MSb LSb — — — — — RCL2048 XFMR2 XFMR1
SYMBOL POSITION FUNCTION CR4.7 — CR4.6 — CR4.5 — CR4.4 — CR4.3 —
RCL2048 CR4.2 0 = RCL threshold: 192 consecutive 0s
1 = RCL threshold: 2048 consecutive 0s
XFMR2 CR4.1 Set to 0 for use with standard transformers.
Set to 1 for use with alternate transformers (Table 11-C)
XFMR1 CR4.0 Set to 0 for use with standard transformers.
Set to 1 for use with alternate transformers (Table 11-C)
DS21349
5. TRANSMITTER
5.1 Transmit Digital Data Interface Data is clocked into the device at the TCLK rate. In bipolar mode, TPOS and TNEG are the data inputs;
in NRZ mode, TDATA is the data input. Input data can pass through either the jitter attenuator or the
B8ZS encoder or both. In software mode, setting ENCENB enables B8ZS encoding. In hardware mode,
floating the MODE1 pin enables B8ZS encoding. With B8ZS encoding enabled, the L0 through L3 inputs
determine the coding and is listed in Table 4-E. TCLK supplies input synchronization. See Section 12 for
the TCLK and MCLK timing requirements.
5.2 Transmit Monitoring In software mode, the DFMO bit in the status register is set when an open circuit in the transmitter path is
detected. A transition on this bit can provide an interrupt, and a transition sets the DFMO bit in the
transition status register. Setting CDFMO in the interrupt mask register, leaving a 1 in that bit location
masks the interrupt.
5.3 Transmit Idle Mode Transmit idle mode allows multiple transceivers to be connected to a single line for redundant
applications. When TCLK is not present, transmit idle mode becomes active, and TTIP and TRING
change to high-impedance state. Remote loopback, dual loopback, TAIS, or detection of network loop-up
code in the receive direction temporarily disable the high-impedance state.
5.4 Transmit Pulse Shape As shown in Table 4-E, line build-out control inputs (L0 through L3) determine the transmit pulse shape.
In software mode, these control inputs are located in control register 1; in hardware mode, these control
inputs are the L0 through L3 pins.
Shaped pulses meeting the various T1, DS1, and DSX-1 specifications are applied to the AMI line driver
for transmission onto the line at TTIP and TRING. The transceiver produces DSX-1 pulses for short-haul
T1 applications (settings from 0dB to 6dB of cable) and DS1 pulses for long-haul T1 applications
(settings from 0dB to -22.5dB). Refer to Table 4-E for pulse mask specifications.
DS21349
6. RECEIVER A 1:1 transformer provides the interface between the twisted pair and receiver inputs RTIP and RRING.
Recovered data is output at RPOS and RNEG (or RDATA in NRZ mode), and the recovered clock is
output at RCLK. See Section 12 for receiver timing specifications.
6.1 Receive Equalizer The receiver can apply up to 36dB of gain. Control of the equalizer is accomplished by the L0 through L3
control inputs. These control signals are detailed in Table 4-E and determine the maximum gain that is
applied. In software mode, these control signals are in Control Register 1; in hardware mode, these
control inputs are the L0 through L3 pins. With L0 low, up to 36dB of gain can be applied; when L0 is
high, 26dB can be applied in the gain limit to provide better noise immunity in shorter loop operations.
6.2 Receive Data Recovery The clock and data recovery engine provides input jitter tolerance that exceeds the requirements of AT&T
62411. Inbound signal is filtered, equalized, and over-sampled 16 times. Then it is applied to the B8ZS
decoder if enabled.
6.3 Receive Digital-Data Interface Recovered data is routed to the RCL monitor. In software mode, data also goes through the alarm
indication signal (AIS) monitor. The jitter attenuator can be enabled or disabled in the receive path or
transmit path. Received data can be routed to the B8ZS decoder or bypassed. Finally, the device can send
the digital data to the framer as either bipolar or NRZ data.
6.4 Receive Monitor Mode The receive equalizer can be used in monitor-mode applications. Monitor-mode applications require
20dB of resistive attenuation of the signal, plus an allowance for cable attenuation (less than 20dB). In
software mode, setting CR3.4 (EQZMON20) enables the device to operate in monitor-mode applications
that require 20dB of resistive attenuation of the signal. Setting CR3.3 (EQZMON26) enables the device
to operate in monitor-mode applications that require 26dB of resistve attenuation. Setting both CR3.3 and
CR3.4 enables the device to operate in monitor-mode applications that require 32dB of resistive
attenuation. The monitor mode feature is not available in hardware mode.
DS21349
7. JITTER ATTENUATION The jitter attenuator only requires a jitter-free clock at 1.544MHz applied to the MCLK input. In
hardware mode, the jitter attenuator is a 32-bit FIFO buffer. Pulling the JASEL pin high places the jitter
attenuator in the receive path. Pulling the JASEL pin low places the jitter attenuator in the transmit path,
floating the JASEL pin disables the jitter attenuator. In software mode, clearing CR1.6 (JASEL0) disables
the jitter attenuator, setting CR1.6 enables the jitter attenuator. If enabled, clearing CR1.7 (JASEL1)
places the jitter attenuator in the transmit path, setting CR1.7 places the jitter attenuator in the receive
path. The jitter attenuator FIFO is 32 bits in length if CR3.2 (JA128) is cleared, 128 bits if set. The device
clocks data in the jitter attenuator using TCLK if placed in the transmit path, and RCLK if placed in the
receive path. Data is clocked out of the jitter attenuator using the dejittered clock produced by the internal
PLL. When the jitter attenuator is within two bits of overflowing or underflowing, the jitter attenuator
will adjust the output clock by one-eighth of a clock cycle. The jitter attenuator adds an average delay of
16 bits if the buffer depth is 32 bits in length, 64 bits if the buffer depth is 128 bits in length. In the event
of an RCL condition, if the jitter attenuator is in the receive path then RCLK is derived from MCLK.
Transition Status register bit TSR.6 (JALT) indicates that the jitter attenuator has adjusted the output
clock. This bit is latched, when set it remains set until the software reads the bit. The JALT can also
produce a hardware interrupt.
8. HARDWARE MODE The DS21349 operates in hardware mode when the MODE1 pin is pulled low or floated. In hardware
mode, configuration of the device is under control of various input pins. RPOS, RNEG, and RDATA are
valid on the rising edge of RCLK only. Some functions such as INT, clock edge select, and some
diagnostic modes are not available.
