DS21348G ,3.3V E1/T1/J1 line interfaceTABLE OF CONTENTS1. LIST OF FIGURES. 42. LIST OF TABLES .. 53. INTRODUCTION... 63.1 DOCUMENT REVISI ..
DS21348G+ ,3.3V E1/T1/J1 Line Interfaceapplications. Throughout the data sheet, J1 is represented wherever T1 exists. Receive sensitivity ..
DS21348GN ,3.3V E1/T1/J1 line interfaceapplications.Throughout the data sheet, J1 is represented wherever T1 exists. Receive sensitivity a ..
DS21348GN+ ,3.3V E1/T1/J1 Line Interfaceapplications. The crystal-less on-board jitter attenuator requires only a 2.048MHz MCLK for both E1 ..
DS21348T , 3.3V E1/T1/J1 Line Interface
DS21348T+ ,3.3V E1/T1/J1 Line Interfaceapplications. The device can generate the necessary G.703 E1 waveshapes in 75Ω or 120Ω
DS21348G-DS21348GN-DS21348TN-DS21Q348N
3.3V E1/T1/J1 line interface
FEATURESComplete E1, T1, or J1 line interface unit
(LIU)Supports both long-haul and short-haul
trunksInternal software-selectable receive-side
termination for 75Ω/100Ω/120�3.3V power supply32-bit or 128-bit crystal-less jitter attenuator
requires only a 2.048MHz master clock for
both E1 and T1 with option to use 1.544MHz
for T1Generates the appropriate line build-outs,with and without return loss, for E1 and
DSX-1 and CSU line build-outs for T1AMI, HDB3, and B8ZS, encoding/decoding16.384MHz, 8.192MHz, 4.096MHz, or2.048MHz clock output synthesized to
recovered clockProgrammable monitor mode for receiverLoopbacks and PRBS pattern generation/
detection with output for received errorsGenerates/detects in-band loop codes, 1 to 16
bits including CSU loop codes8-bit parallel or serial interface with optional
hardware modeMuxed and nonmuxed parallel bus supportsIntel or MotorolaDetects/generates blue (AIS) alarmsNRZ/bipolar interface for TX/RX data I/OTransmit open-circuit detectionReceive Carrier Loss (RCL) indication(G.775)High-Z State for TTIP and TRING50mA (rms) current limiter
PIN DESCRIPTION
ORDERING INFORMATIONDS21348TN 44-Pin TQFP(-40�C to +85�C)
DS21348T44-Pin TQFP (0� C to +70�C)
DS21348GN7mm CABGA(-40�C to +85�C)
DS21348G7mm CABGA (0� C to +70�C)
DS21Q348N(Quad) BGA (-40�C to +85�C)
DS21Q348(Quad) BGA (0� C to +70� C)
44 TQFP
DS21348/Q348
3.3V E1/T1/J1 Line Interface
DS21348/Q348
DESCRIPTIONThe DS21348 is a complete selectable E1 or T1 LIU for short-haul and long-haul applications.
Throughout the data sheet, J1 is represented wherever T1 exists. Receive sensitivity adjusts automatically
to the incoming signal and can be programmed for 0dB to 12 dB or 0dB to 43dB for E1 applications and
0dB to 30dB or 0dB to 36dB for T1 applications. The device can generate the necessary G.703 E1
waveshapes in 75Ω or 120Ω applications and DSX-1 line build outs or CSU line build outs of 0dB,-7.5dB, -15dB, and -22.5dB for T1 applications. The crystal-less onboard jitter attenuator requires only a
2.048MHz MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK in T1
applications). The jitter attenuator FIFO is selectable to either 32 bits or 128 bits in depth and can be
placed in either the transmit or receive data paths. An X 2.048MHz output clock synthesized to RCLK is
available for use as a backplane system clock (where n = 1, 2, 4, or 8). The DS21348 has diagnosticcapabilities such as loopbacks and PRBS pattern generation/detection. 16-bit loop-up and loop-down
codes can be generated and detected. The device can be controlled via an 8-bit parallel muxed or
nonmuxed port, serial port, or used in hardware mode. The device fully meets all of the latest E1 and T1
specifications including ANSI T1.403-1999, ANSI T1.408, AT&T TR 62411, ITU G.703, G.704, G.706,
G.736, G.775, G.823, I.431, O.151, O.161, ETSI ETS 300 166, JTG.703, JTI.431, JJ-20.1, TBR12,TBR13, and CTR4.
DS21348/Q348
TABLE OF CONTENTSLIST OF FIGURES...............................................................................................................................4LIST OF TABLES................................................................................................................................5INTRODUCTION.................................................................................................................................6
3.1DOCUMENT REVISION HISTORY............................................................................................6PIN DESCRIPTION.............................................................................................................................9HARDWARE MODE.........................................................................................................................22
5.1REGISTER MAP..........................................................................................................................23
5.2PARALLEL PORT OPERATION................................................................................................23
5.3SERIAL PORT OPERATION......................................................................................................24CONTROL REGISTERS....................................................................................................................24
6.1DEVICE POWER-UP AND RESET............................................................................................31STATUS REGISTERS.......................................................................................................................34DIAGNOSTICS..................................................................................................................................39
8.1IN-BAND LOOP CODE GENERATION AND DETECTION...................................................39
8.2LOOPBACKS...............................................................................................................................43
8.2.1Remote Loopback (RLB).........................................................................................................43
8.2.2Local Loopback (LLB)............................................................................................................43
8.2.3Analog Loopback (LLB)..........................................................................................................44
8.2.4Dual Loopback (DLB)............................................................................................................44
8.3PRBS GENERATION & DETECTION.......................................................................................44
8.4ERROR COUNTER......................................................................................................................44
8.4.1Error Counter Update............................................................................................................45
8.5ERROR INSERTION....................................................................................................................45ANALOG INTERFACE.....................................................................................................................46
9.1 RECEIVER.....................................................................................................................................46
9.2 TRANSMITTER...........................................................................................................................47
9.3 JITTER ATTENUATOR..............................................................................................................47
9.4 G.703 SYNCHRONIZATION SIGNAL......................................................................................48
10.DS21Q348 QUAD LIU.......................................................................................................................55
11.DC CHARACTERISTICS..................................................................................................................59
12.AC CHARACTERISTICS..................................................................................................................61
13.MECHANICAL DIMENSIONS.........................................................................................................70
13.1MECHANICAL DIMENSIONS—QUAD VERSION.................................................................72
DS21348/Q348
1. LIST OF FIGURESFigure 3-1 DS21348 BLOCK DIAGRAM...................................................................................................7Figure 3-2 RECEIVE LOGIC.......................................................................................................................8
Figure 3-3 TRANSMIT LOGIC...................................................................................................................9
Figure 4-1 PARALLEL PORT MODE PINOUT (BIS1 = 0, BIS0 = 1 or 0).............................................22
Figure 4-2 SERIAL PORT MODE PINOUT (BIS1 = 1, BIS0 = 0)..........................................................22
Figure 4-3 HARDWARE MODE PINOUT (BIS1 = 1, BIS0 = 1)............................................................22Figure 5-1 SERIAL PORT OPERATION FOR READ ACCESS (R=1) MODE 1..................................25
Figure 5-2 SERIAL PORT OPERATION FOR READ ACCESS MODE 2.............................................25
Figure 5-3 SERIAL PORT OPERATION FOR READ ACCESS MODE 3.............................................26
Figure 5-4 SERIAL PORT OPERATION FOR READ ACCESS MODE 4.............................................26
Figure 5-5 SERIAL PORT OPERATION FOR WRITE ACCESS (R=0) MODES 1&2 ...……………27Figure 5-6 SERIAL PORT OPERATION FOR WRITE ACCESS MODES 3& 4 …………...…………27
Figure 9-1 BASIC INTERFACE…………………………………………………………………………49
Figure 9-2 PROTECTED INTERFACE USING INTERNAL RECEIVE TERMINATION....................50
Figure 9-3 PROTECTED INTERFACE USING EXTERNAL RECEIVE TERMINATION...................51
Figure 9-4 E1 TRANSMIT PULSE TEMPLATE......................................................................................52Figure 9-5 T1 TRANSMIT PULSE TEMPLATE......................................................................................53
Figure 9-6 JITTER TOLERANCE.............................................................................................................54
Figure 9-7 JITTER ATTENUATION........................................................................................................54
Figure 10-1 BGA 12 x 12 PIN LAYOUT..................................................................................................58
Figure 12-1 INTEL BUS READ TIMING (PBTS = 0, BIS1 = 0, BIS0 = 0).............................................62Figure 12-2 INTEL BUS WRITE TIMING (PBTS = 0, BIS1 = 0, BIS0 = 0)...........................................62
Figure 12-3 MOTOROLA BUS TIMING (PBTS = 1, BIS1 = 0, BIS0 = 0) ............................................63
Figure 12-4 INTEL BUS READ TIMING (PBTS = 0, BIS1 = 0, BIS0 = 1).............................................65
Figure 12-5 INTEL BUS WRITE TIMING (PBTS = 0, BIS1 = 0, BIS0 = 1)...........................................65
Figure 12-6 MOTOROLA BUS READ TIMING (PBTS = 1, BIS1 = 0, BIS0 = 1).................................66Figure 12-7 MOTOROLA BUS WRITE TIMING (PBTS = 1, BIS1 = 0, BIS0 = 1)................................66
Figure 12-8 SERIAL BUS TIMING (BIS1 = 1, BIS0 = 0)........................................................................67
Figure 12-9 RECEIVE SIDE TIMING......................................................................................................68
Figure 12-10 TRANSMIT SIDE TIMING.................................................................................................69
DS21348/Q348
2. LIST OF TABLESTable 4-1 BUS INTERFACE SELECTION................................................................................................9
Table 4-2a PIN ASSIGNMENT IN PARALLEL PORT MODE..............................................................10
Table 4-2b PIN DESCRIPTIONS IN PARALLEL PORT MODE (Sorted by Pin Name, DS21348T Pin
Numbering)..........................................................................................................................................11Table 4-3a PIN ASSIGNMENT IN SERIAL PORT MODE.....................................................................13
Table 4-3b PIN DESCRIPTIONS IN SERIAL PORT MODE (Sorted by Pin Name, DS21348T Pin
Numbering)..........................................................................................................................................14
Table 4-4a PIN ASSIGNMENT IN HARDWARE MODE.......................................................................16
Table 4-4b PIN DESCRIPTIONS IN HARDWARE MODE (Sorted by Pin Name, DS21348T PinNumbering)..........................................................................................................................................17
Table 4-5 LOOPBACK CONTROL IN HARDWARE MODE................................................................20
Table 4-6 TRANSMIT DATA CONTROL IN HARDWARE MODE.....................................................20
Table 4-7 RECEIVE SENSITIVITY SETTINGS......................................................................................20
Table 4-8 MONITOR GAIN SETTINGS..................................................................................................20Table 4-9 INTERNAL RX TERMINATION SELECT.............................................................................20
Table 4-10 MCLK SELECTION................................................................................................................20
Table 5-1 REGISTER MAP.......................................................................................................................23
Table 6-1 MCLK SELECTION..................................................................................................................29
Table 6-2 RECEIVE SENSITIVITY SETTINGS......................................................................................31Table 6-3 BACK PLANE CLOCK SELECT.............................................................................................32
Table 6-4 MONITOR GAIN SETTINGS..................................................................................................32
Table 6-5 INTERNAL RX TERMINATION SELECT.............................................................................33
Table 7-1 RECEIVED ALARM CRITERIA.............................................................................................35
Table 7-2 RECEIVE LEVEL INDICATION.............................................................................................38Table 8-1 TRANSMIT CODE LENGTH...................................................................................................40
Table 8-2 RECEIVE CODE LENGTH......................................................................................................40
Table 8-3 DEFINITION OF RECEIVED ERRORS..................................................................................44
Table 8-4 FUNCTION OF ECRS BITS AND RNEG PIN........................................................................45
Table 9-1 LINE BUILD OUT SELECT FOR E1 IN REGISTER CCR4 (ETS = 0).................................48Table 9-2 LINE BUILD OUT SELECT FOR T1 IN REGISTER CCR4 (ETS = 1).................................48
Table 9-3 TRANSFORMER SPECIFICATIONS FOR 3.3V OPERATION............................................48
Table 10-1 DS21Q348 PIN ASSIGNMENT..............................................................................................55
DS21348/Q348
3. INTRODUCTIONThe analog AMI/HDB3 waveform off of the E1 line or the AMI/B8ZS waveform off of the T1 line is
transformer coupled into the RTIP and RRING pins of the DS21348. The user has the option to use
internal termination, software selectable for 75Ω/100Ω/120� applications, or external termination. The
device recovers clock and data from the analog signal and passes it through the jitter attenuation MUXoutputting the received line clock at RCLK and bipolar or NRZ data at RPOS and RNEG. The DS21348
contains an active filter that reconstructs the analog received signal for the nonlinear losses that occur in
transmission. The receive circuitry is also configurable for various monitor applications. The device has a
usable receive sensitivity of 0dB to -43dB for E1 and 0dB to -36dB for T1, which allows the device to
operate on 0.63mm (22AWG) cables up to 2.5km (E1) and 6k feet (T1) in length. Data input at TPOS andTNEG is sent via the jitter attenuation mux to the waveshaping circuitry and line driver. The DS21348
will drive the E1 or T1 line from the TTIP and TRING pins via a coupling transformer. The line driver
can handle both CEPT 30/ISDN-PRI lines for E1 and long haul (CSU) or short haul (DSX-1) lines for T1.
3.1 DOCUMENT REVISION HISTORY1) Datasheet for 3.3V only, 011801.
2) Added supply current measurements; added thermal characteristics of quad package, 092101.
DS21348/Q348
DS21348 BLOCK DIAGRAM Figure 3-1TRING
TTIPRRING
RTIP
to
/
to
*(R
to
BIS0
BIS1
HRST*
TESTBPCLK
RPOS
RCLK
RNEG
TPOS
TCLK
TNEG
PBEORCL/LOTC
DS21348/Q348
RECEIVE LOGIC Figure 3-2RPOS
RNEG
From
Remote
LoopbackRCLK
PBEO
DS21348/Q348
TRANSMIT LOGIC Figure 3-3
4. PIN DESCRIPTIONThe DS21348 can be controlled in a parallel port mode, a serial port mode, or a hardware mode (Table
4-1, 4-2, and 4-3). The parallel and serial port modes are described in Section 3, and the Hardware Mode
is described below.
BUS INTERFACE SELECTION Table 4-1TPOS
TNEG
Remote
Loopback
TCLK
DS21348/Q348
PIN ASSIGNMENT IN PARALLEL PORT MODE Table 4-2a
DS21348/Q348
PIN DESCRIPTIONS IN PARALLEL PORT MODE (Sorted by Pin Name,DS21348T Pin Numbering) Table 4-2b
DS21348/Q348
DS21348/Q348
PIN ASSIGNMENT IN SERIAL PORT MODE Table 4-3a
DS21348/Q348
PIN DESCRIPTIONS IN SERIAL PORT MODE (Sorted by Pin Name, DS21348TPin Numbering) Table 4-3b
DS21348/Q348
DS21348/Q348
PIN ASSIGNMENT IN HARDWARE MODE Table 4-4a
DS21348/Q348
PIN DESCRIPTIONS IN HARDWARE MODE (Sorted by Pin Name, DS21348T PinNumbering) Table 4-4b
DS21348/Q348
DS21348/Q348
NOTES:1) G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specs require an
accuracy of ±32ppm for T1 interfaces.2) * Denotes active low.
DS21348/Q348
LOOP BACK CONTROL IN HARDWARE MODE Table 4-5
TRANSMIT DATA CONTROL IN HARDWARE MODE Table 4-6
RECEIVE SENSITIVITY SETTINGS Table 4-7
MONITOR GAIN SETTINGS Table 4-8
INTERNAL RX TERMINATION SELECT Table 4-9
MCLK SELECTION Table 4-10
DS21348/Q348
PARALLEL PORT MODE PINOUT (BIS1 = 0, BIS0 = 1 or 0) Figure 4-1
SERIAL PORT MODE PINOUT (BIS1 = 1, BIS0 = 0) Figure 4-2tie high
tie low
tie low
tie
lo
tie low
tie low (MUX) or high (non-MUX)
e l
DS21348/Q348
HARDWARE MODE PINOUT (BIS1 = 1, BIS0 = 1) Figure 4-3
5. HARDWARE MODEIn hardware mode (BIS1 = 1, BIS0 = 1), pins 1-19, 23, 25, 31, and 44 are redefined to be used for
initializing the DS21348. BPCLK (pin 31) defaults to a 16.384MHz output when in hardware mode. The
RCL/LOTC (pin 25) is designated to RCL when in hardware mode. JABDS (CCR4.2) defaults to logic 0.
The RHBE (CCR2.3) and THBE (CCR2.2) control bits are combined and controlled by HBE at pin 11
while the RSCLKE (CCR5.3) and TSCLKE (CCR5.2) bits are combined and controlled by SCLKE atpin 4. TCES (CCR2.1) and RCES (CCR2.0) are combined and controlled by CES at pin 12. The
transmitter functions are combined and controlled by TX1 (pin 15) and TX0 (pin 14). The loopback
functions are controlled by LOOP1 (pin 17) and LOOP0 (pin 16). All other control bits default to the
logic 0 setting.
tie high
tie high
tie low
DS21348/Q348
5.1 Register MapTable 5-1 REGISTER MAP
NOTES:1) Register addresses 16h to 1Fh do not exist.
2) In the Serial Port Mode, the LSB is on the right hand side.
3) In the Serial Port Mode, data is read and written LSB first.
4) In the Serial Port Mode, the A bit (the LSB) determines whether the access is a read (A = 1) or a write
(A = 0).5) In the Serial Port Mode, the B bit (the MSB) determines whether the access is a burst access (B = 1)
or a single register access (B = 0).
DS21348/Q348
5.2 Parallel Port OperationWhen using the parallel interface on the DS21348 (BIS1 = 0) the user has the option for either
multiplexed bus operation (BIS1 = 0, BIS0 = 0) or non-multiplexed bus operation (BIS1 = 0, BIS0 = 1).
The DS21348 can operate with either Intel or Motorola bus timing configurations. If the PBTS pin is tied
low, Intel timing will be selected; if tied high, Motorola timing will be selected. All Motorola bus signals
are listed in parenthesis (). See the timing diagrams in Section 12 for more details.
5.3 Serial Port OperationSetting BIS1 = 1 and BIS0 = 0 enables the serial bus interface on the DS21348. Port read/write timing is
unrelated to the system transmit and receive timing, allowing asynchronous reads or writes by the host.
See Section 12 for the AC timing of the serial port. All serial port accesses are LSB first. See Figure 5-1,Figure 5-2, Figure 5-3, and Figure 5-4 for more details.
Reading or writing to the internal registers requires writing one address/command byte prior to
transferring register data. The first bit written (LSB) of the address/command byte specifies whether the
access is a read (1) or a write (0). The next 5 bits identify the register address. Bit 7 is reserved and mustbe set to 0 for proper operation.
The last bit (MSB) of the address/command byte is the burst mode bit. When the burst bit is enabled
(B = 0) and a READ operation is performed, addresses 0 through 15h are read sequentially, starting at
address 0h. And when the burst bit is enabled and a WRITE operation is performed, addresses 0 through16h are written sequentially, starting at address 0h. Burst operation is stopped once address 15h is read.
See Figure 5-5 and Figure 5-6 for more details.
All data transfers are initiated by driving the CS* input low. When Input Clock-Edge Select (ICES) is
low, input data is latched on the rising edge of SCLK and when ICES is high, input data is latched on thefalling edge of SCLK. When Output Clock-Edge Select (OCES) is low, data is output on the falling edge
of SCLK and when OCES is high, data is output on the rising edge of SCLK. Data is held until the next
falling or rising edge. All data transfers are terminated if the CS* input transitions high. Port control logic
is disabled and SDO is 3-stated when CS* is high.
DS21348/Q348
SERIAL PORT OPERATION FOR READ ACCESS (R=1) MODE 1 Figure 5-1ICES = 1 (sample SDI on the falling edge of SCLK)
OCES = 1 (update SDO on rising edge of SCLK)
SERIAL PORT OPERATION FOR READ ACCESS MODE 2 Figure 5-2ICES = 1 (sample SDI on the falling edge of SCLK)
OCES = 0 (update SDO on falling edge of SCLK)2345678910111213141516
SCLK
SDI
CS*
(lsb)
(msb)
READ ACCESS ENABLED345678910111213141516
SCLK
SDI
CS*
(lsb)(msb)
(lsb)
(msb)
DS21348/Q348
SERIAL PORT OPERATION FOR READ ACCESS MODE 3 Figure 5-3ICES = 0 (sample SDI on the rising edge of SCLK)
OCES = 0 (update SDO on falling edge of SCLK)
SERIAL PORT OPERATION FOR READ ACCESS MODE 4 Figure 5-4ICES = 0 (sample SDI on the rising edge of SCLK)
OCES = 1 (update SDO on rising edge of SCLK)2345678910111213141516
SCLK
SDI
CS*
(lsb)(msb)
(lsb)
(msb)345678910111213141516D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0
SCLK
SDI
SDO
CS*
(lsb)(msb)
(lsb)(msb)
DS21348/Q348
SERIAL PORT OPERATION FOR WRITE ACCESS (R=0) MODES 1 & 2 FigureICES = 1 (sample SDI on the falling edge of SCLK)
SERIAL PORT OPERATION FOR WRITE ACCESS (R=0) MODES 3 & 4Figure 5-6
ICES = 0 (sample SDI on the rising edge of SCLK)2345678910111213141516SCLK
CS*
(msb)
SDO
(lsb)(msb)
(lsb)
WRITE ACCESS ENABLED345678910111213141516SCLK
CS*
SDI
SDO(msb)
(lsb)
WRITE ACCESS ENABLED
DS21348/Q348
6. CONTROL REGISTERS
CCR1 (00H): COMMON CONTROL REGISTER 1
(MSB)(LSB)
SYMBOLPOSITIONDESCRIPTIONETSCCR1.7
E1/T1 Select.0 = E1
1 = T1
NRZECCR1.6
NRZ Enable.0 = Bipolar data at RPOS/RNEG and TPOS/TNEG1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a
positive going pulse when device receives a BPV, CV, or EXZ.
RCLACCR1.5
Receive Carrier Loss Alternate Criteria.0 = RCL declared upon 255 (E1) or 192 (T1) consecutive zeros
1 = RCL declared upon 2048 (E1) or 1544 (T1) consecutivezeros
ECUECCR1.4
Error Counter Update Enable. A 0 to 1 transition forces thenext clock cycle to load the error counter registers with the
latest counts and reset the counters. The user must wait a
minimum of two clocks cycles (976ns for E1 and 1296ns forT1) before reading the error count registers to allow for a proper
update. See Section 6 for details.
JAMUXCCR1.3
Jitter Attenuator MUX. Controls the source for JACLK. See .0 = JACLK sourced from MCLK (2.048MHz or 1.544MHz at
MCLK)1 = JACLK sourced from internal PLL (2.048MHz at MCLK)
TTOJCCR1.2
TCLK to JACLK. Internally connects TCLK to JACLK. See .0 = disabled
1 = enabled
TTORCCR1.1
TCLK to RCLK. Internally connects TCLK to RCLK. See .0 = disabled
1 = enabled
LOTCMCCCR1.0
Loss Of Transmit Clock Mux Control. Determines whether
the transmit logic should switch to JACLK if the TCLK input
should fail to transition. See .0 = do not switch to JACLK if TCLK stops
1 = switch to JACLK if TCLK stops
DS21348/Q348
MCLK SELECTION Table 6-1
CCR2 (01H): COMMON CONTROL REGISTER 2
(MSB)(LSB)
SYMBOLPOSITIONDESCRIPTIONP25SCCR2.7
Pin 25 Select. Forced to logic 0 in hardware mode.0 = toggles high during a Receive Carrier Loss condition
1 = toggles high if TCLK does not transition for at least 5�s-CCR2.6
Not Assigned. Should be set to zero when written to.SCLDCCR2.5
Short Circuit Limit Disable (ETS = 0). Controls the 50 mA(rms) current limiter.
0 = enable 50 mA current limiter
1 = disable 50 mA current limiterCLDSCCR2.4
Custom Line Driver Select. Setting this bit to a one will
redefine the operation of the transmit line driver. When this bit
is set to a one and CCR4.5 = CCR4.6 = CCR4.7 = 0, then the
device will generate a square wave at the TTIP and TRING
outputs instead of a normal waveform. When this bit is set to a
one and CCR4.5 = CCR4.6 = CCR4.7 � 0, then the device will
force TTIP and TRING outputs to become open drain drivers
instead of their normal push-pull operation. This bit should be
set to zero for normal operation of the device. Contact thefactory for more details on how to use this bit.RHBECCR2.3
Receive HDB3/B8ZS Enable.0 = enable HDB3 (E1)/B8ZS (T1)
1 = disable HDB3 (E1)/B8ZS (T1)
THBECCR2.2
Transmit HDB3/B8ZS Enable.0 = enable HDB3 (E1)/B8ZS (T1)1 = disable HDB3 (E1)/B8ZS (T1)
TCESCCR2.1
Transmit Clock Edge Select. Selects which TCLK edge to
sample TPOS and TNEG.
0 = sample TPOS and TNEG on falling edge of TCLK
1 = sample TPOS and TNEG on rising edge of TCLKRCESCCR2.0
Receive Clock Edge Select. Selects which RCLK edge to
update RPOS and RNEG.
0 = update RPOS and RNEG on rising edge of RCLK
1 = update RPOS and RNEG on falling edge of RCLK
DS21348/Q348
CCR3 (02H): COMMON CONTROL REGISTER 3
(MSB)(LSB)
SYMBOLPOSITIONDESCRIPTIONTUA1CCR3.7
Transmit Unframed All Ones. The polarity of this bit is setsuch that the device will transmit an all ones pattern on power-
up or device reset. This bit must be set to a one to allow the
device to transmit data. The transmission of this data pattern is
always timed off of the JACLK (See Figure 3-1).
0 = transmit all ones at TTIP and TRING1 = transmit data normally
ATUA1CCR3.6
Automatic Transmit Unframed All Ones. Automatically
transmit an unframed all ones pattern at TTIP and TRING
during a receive carrier loss (RCL) condition or receive all ones
condition.0 = disabled
1 = enabled
TAOZCCR3.5
Transmit Alternate Ones and Zeros. Transmit a …101010…pattern at TTIP and TRING. The transmission of this data
pattern is always timed off of TCLK (See Figure 3-1).0 = disabled
1 = enabled
TPRBSECCR3.4
Transmit PRBS Enable. Transmit a 2 - 1 (E1) or a 2 - 1
(T1) PRBS at TTIP and TRING.
0 = disabled1 = enabled
TLCECCR3.3
Transmit Loop Code Enable. Enables the transmit side to
transmit the loop up code in the Transmit Code Definition
registers (TCD1 and TCD2). See Section 6 for details.
0 = disabled
1 = enabledLIRSTCCR3.2
Line Interface Reset. Setting this bit from a zero to a one willinitiate an internal reset that resets the clock recovery state
machine and re-centers the jitter attenuator. Normally this bit isonly toggled on power-up. Must be cleared and set again for a
subsequent reset.
IBPVCCR3.1
Insert BPV. A 0 to 1 transition on this bit will cause a single
BiPolar Violation (BPV) to be inserted into the transmit data
stream. Once this bit has been toggled from a 0 to a 1, thedevice waits for the next occurrence of three consecutive ones
to insert the BPV. This bit must be cleared and set again for a
subsequent error to be inserted. See .
IBECCR3.0
Insert Bit Error. A 0 to 1 transition on this bit will cause a
single logic error to be inserted into the transmit data stream.This bit must be cleared and set again for a subsequent error to
DS21348/Q348
6.1 Device Power-Up and ResetThe DS21348 will reset itself upon power-up setting all writeable registers to 00h and clear the status and
information registers. CCR3.7 (TUA1) = 0 results in the LIU transmitting unframed all ones. After the
power supplies have settled following power-up, initialize all control registers to the desired settings, then
toggle the LIRST bit (CCR3.2). At anytime, the DS21348 can be reset to the default settings by bringing
HRST* (pin 29) low (level triggered) or by powering down and powering up again.
CCR4 (03H): COMMON CONTROL REGISTER 4
(MSB)(LSB)
SYMBOLPOSITIONDESCRIPTIONCCR4.7
Line Build Out Select Bit 2. Sets the transmitter build out; seeTable 9-1 for E1 and Table 9-2 for T1.CCR4.6
Line Build Out Select Bit 1. Sets the transmitter build out; seeTable 9-1 for E1 and Table 9-2 for T1.CCR4.5
Line Build Out Select Bit 0. Sets the transmitter build out; seeTable 9-1 for E1 and Table 9-2 for T1.
EGLCCR4.4
Receive Equalizer Gain Limit. This bit controls the sensitivityof the receive equalizer. See Table 6-2.
JASCCR4.3
Jitter Attenuator Select.0 = place the jitter attenuator on the receive side1 = place the jitter attenuator on the transmit side
JABDSCCR4.2
Jitter Attenuator Buffer Depth Select.0 = 128 bits
1 = 32 bits (use for delay sensitive applications)
DJACCR4.1
Disable Jitter Attenuator.0 = jitter attenuator enabled
1 = jitter attenuator disabled
TPDCCR4.0
Transmit Power-Down.0 = normal transmitter operation
1 = powers down the transmitter and 3-states the TTIP andTRING pins
RECEIVE SENSITIVITY SETTINGS Table 6-2
DS21348/Q348
CCR5 (04H): COMMON CONTROL REGISTER 5
(MSB)(LSB)
SYMBOLPOSITIONDESCRIPTIONBPCS1CCR5.7
Back Plane Clock Select 1. See Table 6-3 for details.BPCS0CCR5.6
Back Plane Clock Select 0. See Table 6-3 for detailsMM1CCR5.5
Monitor Mode 1. See Table 6-4.MM0CCR5.4
Monitor Mode 0. See Table 6-4.RSCLKECCR5.3
Receive Synchronization Clock Enable.0 = disable 2.048MHz synchronization receive mode
1 = enable 2.048MHz synchronization receive modeTSCLKECCR5.2
Transmit Synchronization Clock Enable.0 = disable 2.048MHz transmit synchronization clock
1 = enable 2.048MHz transmit synchronization clock
RT1CCR5.1
Receive Termination 1. See Table 6-5 for details.RT0CCR5.0
Receive Termination 0. See Table 6-5 for details.
BACK PLANE CLOCK SELECT Table 6-3
MONITOR GAIN SETTINGS Table 6-4
DS21348/Q348
INTERNAL RX TERMINATION SELECT Table 6-5
CCR6 (05H): COMMON CONTROL REGISTER 6
(MSB)(LSB)
SYMBOLPOSITIONDESCRIPTIONLLBCCR6.7
Local Loopback. In Local Loopback (LLB), transmit data willbe looped back to the receive path passing through the jitter
attenuator if it is enabled. Data in the transmit path will act as
normal. See for details.
0 = loopback disabled1 = loopback enabled
RLBCCR6.6
Remote Loopback. In Remote Loopback (RLB), data output
from the clock/data recovery circuitry will be looped back to the
transmit path passing through the jitter attenuator if it is
enabled. Data in the receive path will act as normal while datapresented at TPOS and TNEG will be ignored. See for details.
0 = loopback disabled1 = loopback enabled
ARLBECCR6.5
Automatic Remote Loopback Enable & Reset. When this bitis set high, the device will automatically go into remoteloopback when it detects loop up code programmed into the
Receive Loop Up Code Definition Registers (RUPCD1 and
RUPCD2) for a minimum of 5 seconds and it will also set the
RIR2.1 status bit. Once in a RLB state, it will remain in this
state until it has detected the loop code programmed into theReceive Loop Down Code Definition Registers (RDNCD1 and
RDNCD2) for a minimum of 5 seconds at which point it will
force the device out of RLB and clear RIR2.1. The automatic
RLB circuitry can be reset by toggling this bit from a 1 to a 0.
The action of the automatic remote loopback circuitry islogically OR’ed with the RLB (CCR6.6) control bit (i.e. either
one can cause a RLB to occur).
ALBCCR6.4
Analog Loopback. In Analog Loopback (ALB), signals at
TTIP and TRING will be internally connected to RTIP and
RRING. The incoming signals, from the line, at RTIP andRRING will be ignored. The signals at TTIP and TRING will
be transmitted as normal. See for more details.
DS21348/Q348
SYMBOLPOSITIONDESCRIPTIONreceive recovered clock and data to bypass the jitter attenuation
while still allowing the BPCLK output to use the jitter
attenuator. See for details.0 = disabled
1 = enabled
ECRS2CCR6.2
Error Count Register Select 2. See Section 8.4 for details.ECRS1CCR6.1
Error Count Register Select 1. See Section 8.4 for details.ECRS0CCR6.0
Error Count Register Select 0. See Section 8.4 for details.
7. STATUS REGISTERSThere are three registers that contain information on the current real time status of the device, StatusRegister (SR) and Receive Information Registers 1 and 2 (RIR1/RIR2). When a particular event has
occurred (or is occurring), the appropriate bit in one of these three registers will be set to a one. Some of
the bits in SR, RIR1, and RIR2 are latched bits and some are real time bits. The register descriptions
below list which status bits are latched and which are real time bits. For latched status bits, when an event
or an alarm occurs the bit is set to a one and will remain set until the user reads that bit. The bit will becleared when it is read and it will not be set again until the event has occurred again. Two of the latched
status bits (RUA1 and RCL) will remain set after reading if the alarm is still present.
The user will always precede a read of any of the three status registers with a write. The byte written to
the register will inform the DS21348 which bits the user wishes to read and have cleared. The user willwrite a byte to one of these registers with a one in the bit positions to be read and a zero in the other bit
positions. When a one is written to a bit location, that location will be updated with the latest information.
When a zero is written to a bit position, that bit position will not be updated and the previous value will
be held. A write to the status and information registers will be immediately followed by a read of the
same register. The read result should be logically AND’ed with the mask byte that was just written andthis value should be written back into the same register to insure that bit does indeed clear. This second
write step is necessary because the alarms and events in the status registers occur asynchronously with
respect to their access via the parallel port. This write-read-write scheme allows an external
microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the
register. This operation is key in controlling the DS21348 with higher-order software languages.
The bits in the SR register have the unique ability to initiate a hardware interrupt via the INT* output pin.
Each of the alarms and events in the SR can be either masked or unmasked from the interrupt pin via the
Interrupt Mask Register (IMR). The interrupts caused by the RCL, RUA1, and LOTC bits in SR act
differently than the interrupts caused by the other status bits in SR. The RCL, RUA1 and LOTC bits willforce the INT* pin low whenever they change state (i.e., go active or inactive). The INT* pin will be
allowed to return high (if no other interrupts are present) when the user reads the alarm bit that caused the
interrupt to occur even if the alarm is still present. The other status bits in SR can force the INT* pin low
when they are set. The INT* pin will be allowed to return high (if no other interrupts are present) when
the user reads the event bit that caused the interrupt to occur.
DS21348/Q348
RECEIVED ALARM CRITERIA Table 7-1
NOTES:1) Receive carrier loss (RCL) is also known as loss of signal (LOS) or Red Alarm in T1.
2) See CCR1.5 for details.
SR (06H): STATUS REGISTER
(MSB)(LSB)
SYMBOLPOSITIONDESCRIPTIONLUP
(latched)
SR.7
Loop Up Code Detected. Set when the loop up code defined inregisters RUPCD1 and RUPCD2 is being received. See Section
6 for details.
LDN(latched)SR.6
Loop Down Code Detected. Set when the loop down codedefined in registers RDNCD1 and RDNCD2 is being received.
See Section 6 for details.
LOTC
(real time)
SR.5
Loss of Transmit Clock. Set when the TCLK pin has nottransitioned for 5�sec (�2�sec). Will force the LOTC pin high.
RUA1(latched)SR.4
Receive Unframed All Ones. Set when an unframed all onescode is received at RRING and RTIP. See Table 7-1for details.
RCL
(latched)
SR.3
Receive Carrier Loss. Set when a receive carrier loss conditionexists at RRING and RTIP. See Table 7-1for details.
TCLE(real time)SR.2
Transmit Current Limit Exceeded. Set when the 50 mA (rms)current limiter is activated whether the current limiter is enabled
or not.
TOCD
(real time)
SR.1
Transmit Open Circuit Detect. Set when the device detectsthat the TTIP and TRING outputs are open circuited.
PRBSD(real time)SR.0
PRBS Detect. Set when the receive-side detects a 215 - 1 (E1)or a 220 - 1 (T1) Pseudo Random Bit Sequence (PRBS).
DS21348/Q348
IMR (07H): INTERRUPT MASK REGISTER
(MSB)(LSB)
SYMBOLPOSITIONDESCRIPTIONLUPIMR.7
Loop Up Code Detected.0 = interrupt masked
1 = interrupt enabledLDNIMR.6
Loop Down Code Detected.0 = interrupt masked
1 = interrupt enabled
LOTCIMR.5
Loss of Transmit Clock.0 = interrupt masked1 = interrupt enabled
RUA1IMR.4
Receive Unframed All Ones.0 = interrupt masked
1 = interrupt enabled
RCLIMR.3
Receive Carrier Loss.0 = interrupt masked
1 = interrupt enabled
TCLEIMR.2
Transmit Current Limiter Exceeded.0 = interrupt masked
1 = interrupt enabledTOCDIMR.1
Transmit Open Circuit Detect.0 = interrupt masked
1 = interrupt enabled
PRBSDIMR.0
PRBS Detection.0 = interrupt masked1 = interrupt enabled
DS21348/Q348
RIR1 (08H): RECEIVE INFORMATION REGISTER 1
(MSB)(LSB)
SYMBOLPOSITIONDESCRIPTION(latched)
RIR1.7
Zero Detect. Set when a string of at least four (ETS = 0) oreight (ETS = 1) consecutive zeros (regardless of the length of
the string) have been received. Will be cleared when read.16ZD
(latched)
RIR1.6
Sixteen Zero Detect. Set when at least 16 consecutive zeros(regardless of the length of the string) have been received. Will
be cleared when read.
HBD
(latched)
RIR1.5
HDB3/B8ZS Word Detect. Set when an HDB3 (ETS = 0) orB8ZS (ETS = 1) code word is detected independent of whetherthe receive HDB3/B8ZS mode (CCR4.6) is enabled. Will be
cleared when read. Useful for automatically setting the line
coding.
RCLC
(latched)
RIR1.4
Receive Carrier Loss Clear. Set when the RCL alarm has metthe clear criteria defined in Table 7-1. Will be cleared whenread.
RUA1C
(latched)
RIR1.3
Receive Unframed All Ones Clear. Set when the unframed allones signal is no longer detected. Will be cleared when read.
See Table 7-1.
JALT(latched)RIR1.2
Jitter Attenuator Limit Trip. Set when the jitter attenuatorFIFO reaches to within 4 bits of its useful limit. Will be cleared
when read. Useful for debugging jitter attenuation operation.
N/ARIR1.1
Not Assigned. Could be any value when read.N/ARIR1.0
Not Assigned. Could be any value when read.
