DS21348T+ ,3.3V E1/T1/J1 Line Interfaceapplications. The device can generate the necessary G.703 E1 waveshapes in 75Ω or 120Ω
DS21348T+ ,3.3V E1/T1/J1 Line Interfaceapplications and DSX-1 line build-outs or CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB fo ..
DS21348T+ ,3.3V E1/T1/J1 Line InterfaceFEATURES PIN CONFIGURATIONS 111 PRELMINARY Complete E1, T1, or J1 Line Interface Unit 44TOP VIEW ( ..
DS21348TN ,3.3V E1/T1/J1 line interfaceapplications). The jitter attenuator FIFO is selectable to either 32 bits or 128 bits in depth and ..
DS21348T-W ,3.3V E1/T1/J1 Line Interfaceapplications). The jitter attenuator FIFO is selectable to either 32 bits or 128 bits in depth and ..
DS21349DK ,T1/J1 Line Interface Unit Design Kit DS2149DK/DS21349DK T1/J1 Line Interface Unit Design Kit
DS21348G+-DS21348GN+-DS21348T+-DS21348T-W
3.3V E1/T1/J1 Line Interface
FEATURES � Complete E1, T1, or J1 Line Interface Unit
(LIU) � Supports Both Long-Haul And Short-Haul
Trunks � Internal Software-Selectable Receive-Side
Termination for 75Ω/100Ω/120Ω � 3.3V Power Supply � 32-Bit or 128-Bit Crystal-Less Jitter
Attenuator Requires Only a 2.048MHz
Master Clock for Both E1 and T1 with
Option to Use 1.544MHz for T1 � Generates the Appropriate Line Build-Outs,
with and without Return loss, for E1 and
DSX-1 and CSU Line Build-Outs for T1 � AMI, HDB3, and B8ZS, Encoding/Decoding � 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz Clock Output Synthesized to
Recovered Clock � Programmable Monitor Mode for Receiver � Loopbacks and PRBS Pattern Generation/
Detection with Output for Received Errors � Generates/Detects In-Band Loop Codes,
1 to 16 Bits Including CSU Loop Codes � 8-Bit Parallel or Serial Interface with
Optional Hardware Mode � Muxed and Nonmuxed Parallel Bus Supports
Intel or Motorola � Detects/Generates Blue (AIS) Alarms � NRZ/Bipolar Interface for Tx/Rx Data I/O � Transmit Open-Circuit Detection � Receive Carrier Loss (RCL) Indication
(G.775) � High-Impedance State for TTIP and TRING � 50mA (RMS) Current Limiter
PIN CONFIGURATIONS
ORDERING INFORMATION + Denotes lead-free/RoHS-compliant package.
PART CHANNEL TEMP
RANGE PIN-PACKAGE
DS21348TN Single -40°C to +85°C 44 TQFP
DS21348TN+ Single -40°C to +85°C 44 TQFP
DS21348T Single 0°C to +70°C 44 TQFP
DS21348T+ Single 0°C to +70°C 44 TQFP
DS21348GN Single -40°C to +85°C 49 CSBGA
DS21348GN+ Single -40°C to +85°C 49 CSBGA
DS21348G Single 0°C to +70°C 49 CSBGA
DS21348G+ Single 0°C to +70°C 49 CSBGA
DS21Q348N Four -40°C to +85°C 144 CSBGA
DS21Q348 Four 0°C to +70°C 144 CSBGA
111PRELMINARY
DS21348/DS21Q348
3.3V E1/T1/J1 Line Interface
44 TQFP
DS21348
49 CSBGA
(7mm x 7mm)
DS21Q348 TOP VIEW
See Section 8 for 144-pin CSBGA pinout.
DS21348/DS21Q348
DETAILED DESCRIPTION The DS21348 is a complete selectable E1 or T1 line interface unit (LIU) for short-haul and long-haul
applications. Throughout the data sheet, J1 is represented wherever T1 exists. Receive sensitivity adjusts
automatically to the incoming signal and can be programmed for 0dB to 12dB or 0dB to 43dB for E1
applications and 0dB to 30dB or 0dB to 36dB for T1 applications. The device can generate the necessary
G.703 E1 waveshapes in 75Ω or 120Ω applications and DSX-1 line build-outs or CSU line build-outs of
0dB, -7.5dB, -15dB, and -22.5dB for T1 applications. The crystal-less on-board jitter attenuator requires
only a 2.048MHz MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK
in T1 applications). The jitter attenuator FIFO is selectable to either 32 bits or 128 bits in depth and can
be placed in either the transmit or receive data paths. An X 2.048MHz output clock synthesized to RCLK
is available for use as a backplane system clock (where n = 1, 2, 4, or 8).
The DS21348 has diagnostic capabilities such as loopbacks and PRBS pattern generation/detection. 16-
bit loop-up and loop-down codes can be generated and detected. The device can be controlled through an
8-bit parallel muxed or nonmuxed port, serial port, or used in hardware mode. The device fully meets all
of the latest E1 and T1 specifications including ANSI T1.403-1999, ANSI T1.408, AT&T TR 62411,
ITU G.703, G.704, G.706, G.736, G.775, G.823, I.431, O.151, O.161, ETSI ETS 300 166, JTG.703,
JTI.431, JJ-20.1, TBR12, TBR13, and CTR4.
DS21348/DS21Q348
TABLE OF CONTENTS
1. INTRODUCTION..................................................................................................................6 1.1 DOCUMENT REVISION HISTORY...............................................................................................6
2. PIN DESCRIPTION............................................................................................................10 2.1 PIN DESCRIPTIONS........................................................................................................................14
3. HARDWARE MODE..........................................................................................................25 3.1 REGISTER MAP.............................................................................................................................25
3.2 PARALLEL PORT OPERATION.........................................................................................................26
3.3 SERIAL PORT OPERATION..............................................................................................................26
4. CONTROL REGISTERS....................................................................................................29 4.1 DEVICE POWER-UP AND RESET.....................................................................................................32
5. STATUS REGISTERS.......................................................................................................36
6. DIAGNOSTICS..................................................................................................................41 6.1 IN-BAND LOOP CODE GENERATION AND DETECTION......................................................................41
6.2 LOOPBACKS..................................................................................................................................46
6.2.1 Remote Loopback (RLB).....................................................................................................................46
6.2.2 Local Loopback (LLB)..........................................................................................................................46
6.2.3 Analog Loopback (ALB).......................................................................................................................46
6.2.4 Dual Loopback (DLB)...........................................................................................................................46
6.3 PRBS GENERATION AND DETECTION............................................................................................47
6.4 ERROR COUNTER..........................................................................................................................47
6.4.1 Error Counter Update...........................................................................................................................48
6.5 ERROR INSERTION........................................................................................................................48
7. ANALOG INTERFACE......................................................................................................49 7.1 RECEIVER.....................................................................................................................................49
7.2 TRANSMITTER...............................................................................................................................50
7.3 JITTER ATTENUATOR.....................................................................................................................50
7.4 G.703 SYNCHRONIZATION SIGNAL.................................................................................................51
8. DS21Q348 QUAD LIU.......................................................................................................58
9. DC CHARACTERISTICS...................................................................................................62
10. THERMAL CHARACTERISTICS.......................................................................................63
11. AC CHARACTERISTICS...................................................................................................64
12. PACKAGE INFORMATION...............................................................................................73 12.1 44-PIN TQFP (56-G4012-001).....................................................................................................73
12.2 49-BALL CSGBA (7MM X 7MM) (56-G6006-001)...........................................................................74
12.3 144-BALL CSBGA (17MM X 17MM) (56-G6011-001).....................................................................75
DS21348/DS21Q348
LIST OF FIGURES Figure 1-1. DS21348 Block Diagram..........................................................................................................7
Figure 1-2. Receive Logic...........................................................................................................................8
Figure 1-3. Transmit Logic..........................................................................................................................9
Figure 2-1. Parallel Port Mode Pinout (BIS1 = 0, BIS0 = 1 or 0) (TQFP Package)..................................22
Figure 2-2. Serial Port Mode Pinout (BIS1 = 1, BIS0 = 0) (TQFP Package)............................................23
Figure 2-3. Hardware Mode Pinout (BIS1 = 1, BIS0 = 1) (TQFP Package).............................................24
Figure 3-1. Serial Port Operation for Read Access (R = 1) Mode 1.........................................................27
Figure 3-2. Serial Port Operation for Read Access Mode 2.....................................................................27
Figure 3-3. Serial Port Operation for Read Access Mode 3.....................................................................27
Figure 3-4. Serial Port Operation for Read Access Mode 4.....................................................................28
Figure 3-5. Serial Port Operation for Write Access (R = 0) Modes 1 and 2..............................................28
Figure 3-6. Serial Port Operation for Write Access (R = 0) Modes 3 and 4..............................................28
Figure 7-1. Basic Interface.......................................................................................................................52
Figure 7-2. Protected Interface Using Internal Receive Termination........................................................53
Figure 7-3. Protected Interface Using External Receive Termination.......................................................54
Figure 7-4. E1 Transmit Pulse Template..................................................................................................55
Figure 7-5. T1 Transmit Pulse Template..................................................................................................56
Figure 7-6. Jitter Tolerance......................................................................................................................57
Figure 7-7. Jitter Attenuation....................................................................................................................57
Figure 8-1. 144-CSBGA (17mm x 17mm) Pinout.....................................................................................61
Figure 11-1. Intel Bus Read Timing (PBTS = 0, BIS1 = 0, BIS0 = 0).......................................................65
Figure 11-2. Intel Bus Write Timing (PBTS = 0, BIS1 = 0, BIS0 = 0).......................................................65
Figure 11-3. Motorola Bus Timing (PBTS = 1, BIS1 = 0, BIS0 = 0)..........................................................66
Figure 11-4. Intel Bus Read Timing (PBTS = 0, BIS1 = 0, BIS0 = 1).......................................................68
Figure 11-5. Intel Bus Write Timing (PBTS = 0, BIS1 = 0, BIS0 = 1).......................................................68
Figure 11-6. Motorola Bus Read Timing (PBTS = 1, BIS1 = 0, BIS0 = 1)................................................69
Figure 11-7. Motorola Bus Write Timing (PBTS = 1, BIS1 = 0, BIS0 = 1)................................................69
Figure 11-8. Serial Bus Timing (BIS1 = 1, BIS0 = 0)................................................................................70
Figure 11-9. Receive Side Timing............................................................................................................71
Figure 11-10. Transmit Side Timing.........................................................................................................72
DS21348/DS21Q348
LIST OF TABLES Table 2-1. Bus Interface Selection...........................................................................................................10
Table 2-2. Pin Assignment in Parallel Port Mode.....................................................................................10
Table 2-3. Pin Assignment in Serial Port Mode........................................................................................11
Table 2-4. Pin Assignment in Hardware Mode.........................................................................................12
Table 2-5. Pin Descriptions in Parallel Port Mode (Sorted by Pin Name, DS21348T Pin Numbering).....14
Table 2-6. Pin Descriptions in Serial Port Mode (Sorted By Pin Name, DS21348T Pin Numbering).......16
Table 2-7. Pin Descriptions in Hardware Mode (Sorted By Pin Name, DS21348T Pin Numbering)........18
Table 2-8. Loopback Control in Hardware Mode......................................................................................21
Table 2-9. Transmit Data Control in Hardware Mode...............................................................................21
Table 2-10. Receive Sensitivity Settings..................................................................................................21
Table 2-11. Monitor Gain Settings............................................................................................................21
Table 2-12. Internal Rx Termination Select..............................................................................................21
Table 2-13. MCLK Selection.....................................................................................................................22
Table 3-1. Register Map...........................................................................................................................25
Table 4-1. MCLK Selection.......................................................................................................................30
Table 4-2. Receive Equalizer Sensitivity Settings....................................................................................32
Table 4-3. Backplane Clock Select...........................................................................................................34
Table 4-4. Monitor Gain Settings..............................................................................................................34
Table 4-5. Internal Rx Termination Select................................................................................................34
Table 5-1. Received Alarm Criteria..........................................................................................................36
Table 5-2. Receive Level Indication.........................................................................................................40
Table 6-1. Transmit Code Length.............................................................................................................41
Table 6-2. Receive Code Length..............................................................................................................42
Table 6-3. Definition of Received Errors...................................................................................................47
Table 6-4. Function of ECRS Bits and RNEG Pin....................................................................................48
Table 7-1. Line Build-Out Select for E1 in Register CCR4 (ETS = 0).......................................................51
Table 7-2. Line Build-Out Select for T1 in Register CCR4 (ETS = 1).......................................................51
Table 7-3. Transformer Specifications for 3.3V Operation.......................................................................51
Table 8-1. DS21Q348 Pin Assignment.....................................................................................................58
Table 9-1. Recommended DC Operating Conditions...............................................................................62
Table 9-2. Capacitance............................................................................................................................62
Table 9-3. DC Characteristics..................................................................................................................62
Table 10-1. Thermal Characteristics—DS21Q348 CSBGA Package.......................................................63
Table 10-2. Theta-JA (θJA) vs. Airflow.......................................................................................................63
Table 11-1. AC Characteristics—Multiplexed Parallel Port (BIS1 = 0, BIS0 = 0).....................................64
Table 11-2. AC Characteristics—Nonmultiplexed Parallel Port (BIS1 = 0, BIS0 = 1)...............................67
Table 11-3. AC Characteristics—Serial Port (BIS1 = 1, BIS0 = 0)...........................................................70
Table 11-4. AC Characteristics—Receive Side........................................................................................71
Table 11-5. AC Characteristics—Transmit Side.......................................................................................72
DS21348/DS21Q348
1. INTRODUCTION The analog AMI/HDB3 waveform off of the E1 line or the AMI/B8ZS waveform off of the T1 line is
transformer coupled into the RTIP and RRING pins of the DS21348. The user has the option to use
internal termination, software selectable for 75Ω/100Ω/120Ω applications, or external termination. The
device recovers clock and data from the analog signal and passes it through the jitter attenuation MUX
outputting the received line clock at RCLK and bipolar or NRZ data at RPOS and RNEG. The DS21348
contains an active filter that reconstructs the analog received signal for the nonlinear losses that occur in
transmission. The receive circuitry is also configurable for various monitor applications. The device has a
usable receive sensitivity of 0dB to -43dB for E1 and 0dB to -36dB for T1, which allows the device to
operate on 0.63mm (22AWG) cables up to 2.5km (E1) and 6k feet (T1) in length. Data input at TPOS and
TNEG is sent via the jitter attenuation mux to the waveshaping circuitry and line driver. The DS21348
will drive the E1 or T1 line from the TTIP and TRING pins via a coupling transformer. The line driver
can handle both CEPT 30/ISDN-PRI lines for E1 and long-haul (CSU) or short-haul (DSX-1) lines for
T1.
1.1 Document Revision History
REVISION DESCRIPTION 011801 Data sheet revised for 3.3V only.
092101 Added supply current measurements
Added thermal characteristics of quad package
101104 Corrected typos and removed all instances of 5V operation.
113004 Updated the storage and soldering temperature specs in the Absolute
Maximum Ratings section.
011206 Added lead-free packages to Ordering Information table on page 1.
DS21348/DS21Q348
Figure 1-1. DS21348 Block Diagram VSS
Power Connections 2
VCO / PLL
MCL
2.048MHz to
1.544MHz PLL
Jitter
Attenuator
MUX
VSM
nal
g L
back
Drive
U Filte
Wave Sh
apin
Local
Loo
pback
TRING
TTIP
Jitter
Att
atio
an be
pl
ed i
ei
r tr
ansm
it or
cei
pa
th)
Filte
Peak D
tect
Clo
ck / Da
Recovery
RRING
RTIP
Option
rmin
tio
Lo
(Dua
l Mo
Unframed
All Ones
Insertion
D0 to D7
/
D0 to
AD7
PBTS
(R/
(DS
LE(
AS)
0 t
A45
INT
BIS0
BIS1 Control and Test Port
(routed to all blocks) MUX (the Serial, Parallel, and Hardware Interfaces share device pins)
HRST
TEST
16.384MHz or
8.192MHz or
4.096MHz or
2.048MHz
Synthesizer BPCLK
RPOS
RCLK
RNEG
TPOS
TCLK
TNEG
JACLK
See Figure 3-2
See Figure 1-3
PBEO
Hardware
Interface
Control and
InterruptParallel InterfaceSerial Interface
Lo
MUX RCL/LOTC
DS21348
DS21348/DS21Q348
Figure 1-2. Receive Logic RPOS
RNEG
From
Remote
Loopback
Clock
InvertRCLK
CCR2.0
CCR1.6
Routed to
All Blocks
rx bd
mux
4 or 8 Zero Detect
16 Zero Detect
RIR1.7RIR1.6
B8ZS/HDB3
Decoder
All Ones
Detector
Loop Code
Detector
PRBS
Detector
SR.6SR.7SR.4RIR1.3
CCR2.3
RIR1.5
16-Bit Error
Counter (ECR)
muxCCR6.0SR.0
CCR6.2/
CCR6.0/
CCR6.1
NRZ Data
BPV/CV/EXZ
PBEO
CCR1.4
DS21348/DS21Q348
Figure 1-3. Transmit Logic BPV
Insert
mux
B8ZS/
HDB3
Coder
Logic
Error
Insert
mux
Gate
GateCCR3.1
CCR1.6
CCR2.2
CCR3.0
CCR3.4CCR3.3
TPOS
TNEG
Remote
Loopback
PRBS Generator
Loop Code Generator
Clock
Invert
Loss Of Transmit
Clock Detect
TCLK
CCR2.1
RCLK
JACLK
(derived
from
MCLK)
CCR1.0
CCR1.1
CCR1.2
mux
mux
Gate
To LOTC Output Pin
AND
Gate
Routed to
All Blocks
tx bd
SR.5
DS21348/DS21Q348
2. PIN DESCRIPTION The DS21348 can be controlled in a parallel port mode, serial port mode, or hardware mode (Table 2-2,
Table 2-3, and Table 2-4).
Table 2-1. Bus Interface Selection
BIS1 BIS0 PBTS MODE 0 0 0 Muxed Intel
0 0 1 Muxed Motorola
0 1 0 Nonmuxed Intel
0 1 1 Nonmuxed Motorola
1 0 — Serial Port
1 1 — Hardware
Table 2-2. Pin Assignment in Parallel Port Mode
PIN
DS21348T DS21348G I/O PARALLEL
PORT MODE C3 I CS
2 C2 I RD (DS)
3 B1 I WR (R/W)
4 D2 I ALE (AS)
5 C1 I NA
6 D3 I NA
7 D1 I/O A4
8 E1 I A3
9 F2 I A2
10 F1 I A1
11 G1 I A0
12 E3 I/O D7/AD7
13 F3 I/O D6/AD6
14 G2 I/O D5/AD5
15 F4 I/O D4/AD4
16 G3 I/O D3/AD3
17 E4 I/O D2/AD2
18 G4 I/O D1/AD1
19 F5 I/O D0/AD0
20 G5 I VSM
21 F6 — VDD
22 G6 — VSS
23 E5 I/O INT
24 E6 O PBEO
25 F7 O RCL/LOTC
26 D6 I TEST
DS21348/DS21Q348
PIN
DS21348T DS21348G I/O PARALLEL
PORT MODE 28 D7 I RRING
29 C6 I HRST
30 C7 I MCLK
31 B6 O BPCLK
32 B7 I BIS0
33 A7 I BIS1
34 C5 O TTIP
35 B5 — VSS
36 A6 — VDD
37 B4 O TRING
38 C4 O RPOS
39 A4 O RNEG
40 B3 O RCLK
41 A3 I TPOS
42 B2 I TNEG
43 A2 I TCLK
44 A1 I PBTS
Table 2-3. Pin Assignment in Serial Port Mode
PIN
DS21348T DS21348G I/O SERIAL
PORT MODE C3 I CS
2 C2 I NA
3 B1 I NA
4 D2 I NA
5 C1 I SCLK
6 D3 I SDI
7 D1 I/O SDO
8 E1 I ICES
9 F2 I OCES
10 F1 I NA
11 G1 I NA
12 E3 I/O NA
13 F3 I/O NA
14 G2 I/O NA
15 F4 I/O NA
16 G3 I/O NA
17 E4 I/O NA
18 G4 I/O NA
19 F5 I/O NA
20 G5 I VSM
21 F6 — VDD
DS21348/DS21Q348
PIN
DS21348T DS21348G I/O SERIAL
PORT MODE 23 E5 I/O INT
24 E6 O PBEO
25 F7 O RCL/LOTC
26 D6 I TEST
27 D5 I RTIP
28 D7 I RRING
29 C6 I HRST
30 C7 I MCLK
31 B6 O BPCLK
32 B7 I BIS0
33 A7 I BIS1
34 C5 O TTIP
35 B5 — VSS
36 A6 — VDD
37 B4 O TRING
38 C4 O RPOS
39 A4 O RNEG
40 B3 O RCLK
41 A3 I TPOS
42 B2 I TNEG
43 A2 I TCLK
44 A1 I NA
Table 2-4. Pin Assignment in Hardware Mode
PIN
DS21348T DS21348G I/O HARDWARE
MODE C3 I EGL
2 C2 I ETS
3 B1 I NRZE
4 D2 I SCLKE
5 C1 I L2
6 D3 I L1
7 D1 I/O L0
8 E1 I DJA
9 F2 I JAMUX
10 F1 I JAS
11 G1 I HBE
12 E3 I/O CES
13 F3 I/O TPD
14 G2 I/O TX0
15 F4 I/O TX1
DS21348/DS21Q348
PIN
DS21348T DS21348G I/O HARDWARE
MODE 17 E4 I/O LOOP1
18 G4 I/O MM0
19 F5 I/O MM1
20 G5 I VSM
21 F6 — VDD
22 G6 — VSS
23 E5 I/O RT1
24 E6 O PBEO
25 F7 O RCL
26 D6 I TEST
27 D5 I RTIP
28 D7 I RRING
29 C6 I HRST
30 C7 I MCLK
31 B6 O BPCLK
32 B7 I BIS0
33 A7 I BIS1
34 C5 O TTIP
35 B5 — VSS
36 A6 — VDD
37 B4 O TRING
38 C4 O RPOS
39 A4 O RNEG
40 B3 O RCLK
41 A3 I TPOS
42 B2 I TNEG
43 A2 I TCLK
44 A1 I RT0
DS21348/DS21Q348
2.1 Pin Descriptions
Table 2-5. Pin Descriptions in Parallel Port Mode (Sorted by Pin Name,
DS21348T Pin Numbering)
NAME PIN I/O FUNCTION A0 to A4 11 to 7 I
Address Bus. In nonmultiplexed bus operation (BIS1 = 0, BIS0 = 1), serves as the address bus. In multiplexed bus operation (BIS1 =
0, BIS0 = 0), these pins are not used and should be tied low.
ALE (AS) 4 I
Address Latch Enable (Address Strobe). When using the parallel port (BIS1 = 0) in multiplexed bus mode (BIS0 = 0), serves to
demultiplex the bus on a positive-going edge. In nonmultiplexed bus
mode (BIS0 = 1), should be tied low.
BIS0/BIS1 32/33 I
Bus Interface Select Bits 0 and 1. Used to select bus interface option. See Table 2-1 for details.
BPCLK 31 O
Backplane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz clock output that is referenced to RCLK selectable via
CCR5.7 and CCR5.6. In hardware mode, defaults to 16.384MHz
output.
CS 1 I
Chip Select, Active Low. This active-low signal must be low to read or write to the device.
D0/AD0 to
D7/AD7 19 to 12 I/O
Data Bus/Address/Data Bus. In nonmultiplexed bus operation (BIS1 = 0, BIS0 = 1), serves as the data bus. In multiplexed bus
operation (BIS1 = 0, BIS0 = 0), serves as an 8-bit multiplexed
address/data bus.
HRST 29 I
Hardware Reset, Active Low. Bringing HRST low resets the DS21348, setting all control bits to their default state of all zeros.
INT 23 O
Interrupt, Active Low. Flags host controller during conditions and change of conditions defined in the Status Register. Active low,
open drain output.
MCLK 30 I
Master Clock. A 2.048MHz (±50ppm) clock source with TTL levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz
clock source is optional.
N/A — I
Not Assigned. Should be tied low. PBEO 24 O
PRBS Bit Error Output. The receiver will constantly search for a 15-1 or a 220-1 PRBS depending on the ETS bit setting (CCR1.7).
Remains high if out of synchronization with the PRBS pattern. Goes
low when synchronized to the PRBS pattern. Any errors in the
received pattern after synchronization will cause a positive going
pulse (with same period as E1 or T1 clock) synchronous with
RCLK. PRBS bit errors can also be reported to the ECR1 and ECR2
registers by setting CCR6.2 to a logic 1.
DS21348/DS21Q348
NAME PIN I/O FUNCTION PBTS 44 I
Parallel Bus Type Select. When using the parallel port (BIS1 = 0), set high to select Motorola bus timing, set low to select Intel bus
timing. This pin controls the function of the RD (DS), ALE (AS),
and WR (R/W) pins. If PBTS = 1 and BIS1 = 0, then these pins
assume the Motorola function listed in parentheses (). In serial port
mode, this pin should be tied low.
RCLK 40 O
Receive Clock. Buffered recovered clock from the line. Synchronous to MCLK in absence of signal at RTIP and RRING.
RD (DS) 2 I
Read Input (Data Strobe), Active Low. DS is active low when in nonmultiplexed, Motorola mode. See the bus timing diagrams in
Section 11.
RCL/
LOTC 25 O
Receive Carrier Loss/Loss of Transmit Clock. An output which will toggle high during a receive carrier loss (CCR2.7 = 0) or will
toggle high if the TCLK pin has not been toggled for 5 µsec ± 2 µsec (CCR2.7 = 1). CCR2.7 defaults to logic 0 when in hardware
mode.
RNEG 39 O
Receive Negative Data. Updated on the rising edge (CCR2.0 = 0) or the falling edge (CCR2.0 = 1) of RCLK with the bipolar data out
of the line interface. Set NRZE (CCR1.6) to a one for NRZ
applications. In NRZ mode, data will be output on RPOS while a
received error will cause a positive-going pulse synchronous with
RCLK at RNEG. See Section 6.4 for details.
RPOS 38 O
Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or the falling edge (CCR2.0 = 1) of RCLK with bipolar data out of the
line interface. Set NRZE (CCR1.6) to a one for NRZ applications. In
NRZ mode, data will be output on RPOS while a received error will
cause a positive-going pulse synchronous with RCLK at RNEG. See
Section 6.4 for details.
RTIP/
RRING 27/28 I
Receive Tip and Ring. Analog inputs for clock recovery circuitry. These pins connect via a 1:1 transformer to the line. See Section 5
for details.
TCLK 43 I
Transmit Clock. A 2.048MHz or 1.544MHz primary clock. Used to clock data through the transmit side formatter. Can be sourced
internally by MCLK or RCLK. See Common Control Register 1 and
Figure 1-3.
TEST 26 I
Tri-State Control. Set high to tri-state all outputs and I/O pins (including the parallel control port). Set low for normal operation.
Useful in board level testing.
TNEG 42 I
Transmit Negative Data. Sampled on the falling edge (CCR2.1 = 0) or the rising edge (CCR2.1 = 1) of TCLK for data to be
transmitted out onto the line.
TPOS 41 I
Transmit Positive Data. Sampled on the falling edge (CCR2.1 = 0) or the rising edge (CCR2.1 = 1) of TCLK for data to be transmitted
out onto the line.
DS21348/DS21Q348
NAME PIN I/O FUNCTION TTIP/
TRING 34/37 O
Transmit Tip and Ring [TTIP AND TRING]. Analog line driver outputs. These pins connect via a step-up transformer to the line. See
Section 5 for details.
VDD 21/36 —
Positive Supply. 3.3V ±5% VSM 20 I
Voltage Supply Mode. Should be low for 3.3V operation. VSS 22/35 —
Signal Ground WR (R/W) 3 I
Write Input (Read/Write), Active Low. See the bus timing diagrams in Section 11.
Table 2-6. Pin Descriptions in Serial Port Mode (Sorted By Pin Name,
DS21348T Pin Numbering)
NAME PIN I/O FUNCTION BIS0/BIS1 32/33 I
Bus Interface Select Bits 0 and 1. Used to select bus interface option. See Table 2-1 for details.
BPCLK 31 O
Backplane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz clock output that is referenced to RCLK selectable via
CCR5.7 and CCR5.6. In hardware mode, defaults to 16.384MHz
output.
CS 1 I
Chip Select, Active Low. Active-low signal must be low to read or write to the device.
HRST 29 I
Hardware Reset, Active Low. Bringing HRST low will reset the DS21348 setting all control bits to their default state of all zeros.
ICES 8 I
Input Clock Edge Select. Selects whether the serial port data input (SDI) is sampled on rising (ICES =0) or falling edge (ICES = 1) of
SCLK.
INT 23 O
Interrupt, Active Low. Flags host controller during conditions and change of conditions defined in the Status Register. Active-low,
open-drain output.
MCLK 30 I
Master Clock. A 2.048MHz (±50ppm) clock source with TTL levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz
clock source is optional.
NA — I
Not Assigned. Should be tied low. OCES 9 I
Output Clock Edge Select. Selects whether the serial port data output (SDO) is valid on the rising (OCES = 1) or falling edge
(OCES = 0) of SCLK.
PBEO 24 O
PRBS Bit Error Output. The receiver will constantly search for a 15-1 or a 220-1 PRBS depending on the ETS bit setting (CCR1.7).
Remains high if out of synchronization with the PRBS pattern. Goes
low when synchronized to the PRBS pattern. Any errors in the
received pattern after synchronization will cause a positive going
pulse (with same period as E1 or T1 clock) synchronous with
RCLK. PRBS bit errors can also be reported to the ECR1 and ECR2
DS21348/DS21Q348
NAME PIN I/O FUNCTION RCLK 40 O
Receive Clock. Buffered recovered clock from the line. Synchronous to MCLK in absence of signal at RTIP and RRING.
RCL/LOTC 25 O
Receive Carrier Loss/Loss of Transmit Clock. An output which will toggle high during a receive carrier loss (CCR2.7 = 0) or will
toggle high if the TCLK pin has not been toggled for 5µs ± 2µs
(CCR2.7 = 1). CCR2.7 defaults to logic 0 when in hardware mode.
RNEG 39 O
Receive Negative Data. Updated on the rising edge (CCR2.0 = 0) or the falling edge (CCR2.0 = 1) of RCLK with the bipolar data out
of the line interface. Set NRZE (CCR1.6) to a one for NRZ
applications. In NRZ mode, data will be output on RPOS while a
received error will cause a positive-going pulse synchronous with
RCLK at RNEG. See Section 6.4 for details.
RPOS 38 O
Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or the falling edge (CCR2.0 = 1) of RCLK with bipolar data out of the
line interface. Set NRZE (CCR1.6) to a one for NRZ applications. In
NRZ mode, data will be output on RPOS while a received error will
cause a positive-going pulse synchronous with RCLK at RNEG. See
Section 6.4 for details.
RTIP/
RRING 27/28 I
Receive Tip and Ring. Analog inputs for clock recovery circuitry. These pins connect via a 1:1 transformer to the line. See Section 5
for details.
SCLK 5 I
Serial Clock. Serial bus clock input. SDI 6 I
Serial Data Input. Sampled on rising edge (ICES = 0) or the falling edge (ICES = 1) of SCLK.
SDO 7 O
Serial Data Output. Valid on the falling edge (OCES = 0) or the rising edge (OCES = 1) of SCLK.
TCLK 43 I
Transmit Clock. A 2.048MHz or 1.544MHz primary clock. Used to clock data through the transmit side formatter. Can be sourced
internally by MCLK or RCLK. See Common Control Register 1 and
Figure 1-3.
TEST 26 I
Tri-State Control. Set high to tri-state all outputs and I/O pins (including the parallel control port). Set low for normal operation.
Useful in board-level testing.
TNEG 42 I
Transmit Negative Data. Sampled on the falling edge (CCR2.1 = 0) or the rising edge (CCR2.1 = 1) of TCLK for data to be
transmitted out onto the line.
TPOS 41 I
Transmit Positive Data. Sampled on the falling edge (CCR2.1 = 0) or the rising edge (CCR2.1 = 1) of TCLK for data to be transmitted
out onto the line.
TTIP/TRIN34/37 O
Transmit Tip and Ring [TTIP and TRING]. Analog line-driver outputs. These pins connect via a step-up transformer to the line.
See Section 5 for details.
VDD 21/36 —
Positive Supply. 3.3V ±5% VSM 20 I
Voltage Supply Mode. Should be tied low for 3.3V operation.
DS21348/DS21Q348
Table 2-7. Pin Descriptions in Hardware Mode (Sorted By Pin Name,
DS21348T Pin Numbering)
NAME PIN I/O FUNCTION
BIS0/BIS1 32/33 I Bus Interface Select Bits 0 and 1. Used to select bus interface
option. BIS0 = 1 and BIS1 = 1 selects hardware mode.
BPCLK 31 O Backplane Clock. 16.384MHz output.
CES 12 I
Receive and Transmit Clock Edge Select. Selects which RCLK
edge to update RPOS and RNEG and which TCLK edge to sample
TPOS and TNEG.
0 = update RNEG/RPOS on rising edge of RCLK; sample
TPOS/TNEG on falling edge of TCLK
1 = update RNEG/RPOS on falling edge of RCLK; sample
TPOS/TNEG on rising edge of TCLK
DJA 8 I
Disable Jitter Attenuator.
0 = jitter attenuator enabled
1 = jitter attenuator disabled
EGL 1 I
Receive Equalizer Gain Limit. This pin controls the sensitivity of
the receive equalizer.
EGL E1 (ETS = 0)
0 = -12dB (short haul)
1 = -43dB (long haul)
EGL T1 (ETS = 1)
0 = -36dB (long haul)
1 = -30dB (limited long haul)
ETS 2 I
E1/T1 Select.
0 = E1
1 = T1
HBE 11 I
Receive and Transmit HDB3/B8ZS Enable
0 = enable HDB3 (E1)/B8ZS (T1)
1 = disable HDB3 (E1)/B8ZS (T1)
HRST 29 I Hardware Reset. Bringing HRST low will reset the DS21348.
JAMUX 9 I
Jitter Attenuator Mux. Controls the source for JACLK.
See Figure 1-1 and Table 2-13.
E1 (ETS = 0) JAMUX
MCLK = 2.048MHz 0
T1 (ETS = 1)
MCLK = 2.048MHz 1
MCLK = 1.544MHz 0
JAS 10 I
Jitter Attenuator Select
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
L0/L1/L2 7/6/5 I
Transmit LIU Waveshape Select Bits 0 and 1 [H/W Mode].
These inputs determine the waveshape of the transmitter (Table 7-1
and Table 7-2.
DS21348/DS21Q348
NAME PIN I/O FUNCTION
MCLK 30 I
Master Clock. A 2.048MHz (±50ppm) clock source with TTL
levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz
clock source is optional. G.703 requires an accuracy of ±50ppm for
both T1 and E1. TR62411 and ANSI specs require an accuracy of ±32ppm for T1 interfaces.
MM0/MM1 18/19 I Monitor Mode Select Bits 0 and 1 [H/W Mode]. These inputs
determine if the receive equalizer is in a monitor mode (Table 2-11).
NA — I Not Assigned. Should be tied low.
NRZE 3 I
NRZ Enable [H/W Mode]
0 = Bipolar data at RPOS/RNEG and TPOS/TNEG
1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a
positive going pulse when device receives a BPV, CV, or EXZ.
PBEO 24 O
PRBS Bit Error Output. The receiver will constantly search for a
QRSS (T1) or a 215-1 (E1) PRBS depending whether T1 or E1
mode is selected. Remains high if out of synchronization with the
PRBS pattern. Goes low when synchronized to the PRBS pattern.
Any errors in the received pattern after synchronization will cause a
positive going pulse (with same period as E1 or T1 clock)
synchronous with RCLK.
RCLK 40 O Receive Clock. Buffered recovered clock from the line.
Synchronous to MCLK in absence of signal at RTIP and RRING.
RCL 25 O Receive Carrier Loss. An output which will toggle high during a
receive carrier loss.
RNEG 39 O
Receive Negative Data. Updated on the rising edge (CES = 0) or
the falling edge (CES = 1) of RCLK with the bipolar data out of the
line interface. Set NRZE to a one for NRZ applications. In NRZ
mode, data will be output on RPOS while a received error will cause
a positive-going pulse synchronous with RCLK at RNEG. See
Section 6.4 for details.
RPOS 38 O
Receive Positive Data. Updated on the rising edge (CES = 0) or the
falling edge (CES = 1) of RCLK with bipolar data out of the line
interface. Set NRZE pin to a one for NRZ applications. In NRZ
mode, data will be output on RPOS while a received error will cause
a positive-going pulse synchronous with RCLK at RNEG. See
section 6.4 for details.
RT0/RT1 44/23 I Receive LIU Termination Select Bits 0 and 1 [H/W Mode]. These
inputs determine the receive termination. See Table 2-12.
RTIP/
RRING 27/28 I
Receive Tip and Ring. Analog inputs for clock recovery circuitry.
These pins connect via a 1:1 transformer to the line. See Section 5
for details.
SCLKE 4 I
Receive and Transmit Synchronization Clock Enable
0 = disable 2.048MHz synchronization transmit and receive mode
1 = enable 2.048 Hz synchronization transmit and receive mode
DS21348/DS21Q348
NAME PIN I/O FUNCTION
TEST 26 I
Tri-State Control. Set high to tri-state all outputs and I/O pins
(including the parallel control port). Set low for normal operation.
Useful in board-level testing.
TNEG 42 I
Transmit Negative Data. Sampled on the falling edge (CES = 0) or
the rising edge (CES = 1) of TCLK for data to be transmitted out
onto the line.
TPD 13 I
Transmit Power-Down
0 = normal transmitter operation
1 = powers down the transmitter and tri-states the TTIP and TRING
pins
TPOS 41 I
Transmit Positive Data. Sampled on the falling edge (CES = 0) or
the rising edge (CES = 1) of TCLK for data to be transmitted out
onto the line.
TTIP/TRING 34/37 O
Transmit Tip and Ring [TTIP and TRING]. Analog line driver
outputs. These pins connect via a step-up transformer to the line.
See Section 5 for details.
TX0/TX1 14/15 I Transmit Data Source Select Bits 0 and 1 [H/W Mode]. These
inputs determine the source of the transmit data. See Table 2-9.
VDD 21/36 — Positive Supply. 3.3V ±5%
VSM 20 I Voltage Supply Mode. Should be tied low for 3.3V operation.
VSS 22/35 — Signal Ground
Note: G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specs require an accuracy of ±32ppm for
T1 interfaces.
DS21348/DS21Q348
Table 2-8. Loopback Control in Hardware Mode
LOOPBACK SYMBOL CONTROL
BIT LOOP1 LOOP0
Remote Loopback RLB CCR6.6 1 1
Local Loopback LLB CCR6.7 1 0
Analog Loopback ALB CCR6.4 0 1
No Loopback — — 0 0
Table 2-9. Transmit Data Control in Hardware Mode
TRANSMIT DATA SYMBOL CONTROL
BIT TX1 TX0
Transmit Unframed
All Ones TUA1 CCR3.7 1 1
Transmit Alternating
Ones and Zeros TAOZ CCR3.5 1 0
Transmit PRBS TPRBSE CCR3.4 0 1
TPOS and TNEG — — 0 0
Table 2-10. Receive Sensitivity Settings
EGL
(CCR4.4)
ETS
(CCR1.7) RECEIVE SENSITIVITY 0 (E1) -12dB (short haul) 0 (E1) -43dB (long haul) 1 (T1) -30dB (limited long haul) 1 (T1) -36dB (long haul)
Table 2-11. Monitor Gain Settings
MM1
(CCR5.5)
MM0
(CCR5.4)
INTERNAL LINEAR
GAIN BOOST (dB) 0 Normal operation (no boost)
0 1 20
1 0 26
1 1 32
Table 2-12. Internal Rx Termination Select
RT1
(CCR5.1)
RT0
(CCR5.0)
INTERNAL RECEIVE
TERMINATION CONFIGURATION
0 0 Internal receive-side termination disabled
0 1 Internal receive-side 120Ω enabled
1 0 Internal receive-side 100Ω enabled
1 1 Internal receive-side 75Ω enabled
DS21348/DS21Q348
Table 2-13. MCLK Selection
MCLK
(MHz)
JAMUX
(CCR1.3)
ETS
(CCR1.7)
2.048 0 0
2.048 1 1
1.544 0 1
Figure 2-1. Parallel Port Mode Pinout (BIS1 = 0, BIS0 = 1 or 0) (TQFP
Package)
1 CS
2 RD (DS)
3 WR (R/W)
4 ALE (AS)
5 NA
6 NA
7 A4
8 A3
9 A2
10 A1
11 A0
BIS1 33
BIS0 32
BPCLK 31
MCLK 30
HRST 29
RRING 28
RTIP 27
TEST 26
RCL/LOTC 25
PBEO 24
INT 23
34 TTIP
35
VSS
36
VDD
37 T
ING
38
39
RNEG
40
RCLK
41 TP
42 T
43 T
44
PBTS
VSS
VDD
21
VSM 2
/D0
/D1
/D2
/D3
/D4
/D5
/D6
/D7
DS21348
Parallel Port
Operation
(NOTE: TIE ALL NA PINS LOW)
tie low
TIE LOW (MUX) OR HIGH (NONMUX)
TIE LOW
DS21348/DS21Q348
Figure 2-2. Serial Port Mode Pinout (BIS1 = 1, BIS0 = 0) (TQFP Package)
1 CS
2 NA
3 NA
4 NA
5 SCLK
6 SDI
7 SDO
8 ICES
9 OCES
10 NA
11 NA
BIS1 33
BIS0 32
BPCLK 31
MCLK 30
HRST 29
RRING 28
RTIP 27
TEST 26
RCL/LOTC 25
PBEO 24
INT 23
34
35
VSS
36
VDD
37 T
ING
38
39
RNEG
40
RCLK
41 TP
42 T
43 T
44
PBTS
VSS
VDD
VSM 2
19
18
17
16
15
14
13
12
DS21348
Serial Port
Operation
(NOTE: TIE ALL NA PINS LOW)
TIE HIGH
TIE LOW
E LOW
TIE LOW
DS21348/DS21Q348
Figure 2-3. Hardware Mode Pinout (BIS1 = 1, BIS0 = 1) (TQFP Package)
1 EGL
2 ETS
3 NRZE
4 SCLKE
5 L2
6 L1
7 L0
8 DJA
9 JAMUX
10 JAS
11 HBE
BIS1 33
BIS0 32
BPCLK 31
MCLK 30
HRST 29
RRING 28
RTIP 27
TEST 26
RCL 25
PBEO 24
RT1 23
34 TTIP
35
VSS
36
VDD
37 T
ING
38
39
RNEG
40
RCL
41 TP
42 T
43 T
44
RT0
VSS
VDD
VSM 2MM1 19MM0 18
LOOP1
17
LOOP0
16
TX1 TX0 14
TPD
CES
1
DS21348
Hardware
Operation
TIE HIGH
TIE HIGH
E LOW
DS21348/DS21Q348
3. HARDWARE MODE
In hardware mode (BIS1 = 1, BIS0 = 1), pins 1–19, 23, 25, 31, and 44 are redefined to be used for
initializing the DS21348. BPCLK (pin 31) defaults to a 16.384MHz output when in hardware mode. The
RCL/LOTC (pin 25) is designated to RCL when in hardware mode. JABDS (CCR4.2) defaults to logic 0.
The RHBE (CCR2.3) and THBE (CCR2.2) control bits are combined and controlled by HBE at pin 11
while the RSCLKE (CCR5.3) and TSCLKE (CCR5.2) bits are combined and controlled by SCLKE at
pin 4. TCES (CCR2.1) and RCES (CCR2.0) are combined and controlled by CES at pin 12. The
transmitter functions are combined and controlled by TX1 (pin 15) and TX0 (pin 14). The loopback
functions are controlled by LOOP1 (pin 17) and LOOP0 (pin 16). All other control bits default to the
logic 0 setting.
3.1 Register Map
Table 3-1. Register Map
NAME REGISTER R/W PARALLEL
PORT MODE
SERIAL PORT
MODE
(Notes 2 to 5)
(msb) (lsb)
CCR1 Common Control Register 1 R/W 00h B000 000A
CCR2 Common Control Register 2 R/W 01h B000 001A
CCR3 Common Control Register 3 R/W 02h B000 010A
CCR4 Common Control Register 4 R/W 03h B000 011A
CCR5 Common Control Register 5 R/W 04h B000 100A
CCR6 Common Control Register 6 R/W 05h B000 101A
SR Status Register R 06h B000 110A
IMR Interrupt Mask Register R/W 07h B000 111A
RIR1 Receive Information Register 1 R 08h B001 000A
RIR2 Receive Information Register 2 R 09h B001 001A
IBCC In-Band Code Control Register R/W 0Ah B001 010A
TCD1 Transmit Code Definition Register 1 R/W 0Bh B001 011A
TCD2 Transmit Code Definition Register 2 R/W 0Ch B001 100A
RUPCD1 Receive Up Code Definition Register 1 R/W 0Dh B001 101A
RUPCD2 Receive Up Code Definition Register 2 R/W 0Eh B001 110A
RDNCD1 Receive Down Code Definition Register 1 R/W 0Fh B001 111A
RDNCD2 Receive Down Code Definition Register 2 R/W 10h B010 000A
ECR1 Error Count Register 1 R 11h B010 001A
ECR2 Error Count Register 2 R 12h B010 010A
TEST1 Test 1 R/W 13h B010 011A
TEST2 Test 2 R/W 14h B010 100A
TEST3 Test 3 R/W 15h B010 101A
— — — (Note 1) —
Note 1: Register addresses 16h to 1Fh do not exist.
Note 2: In the Serial Port Mode, the LSB is on the right hand side.
Note 3: In the Serial Port Mode, data is read and written LSB first.
Note 4: In the Serial Port Mode, the A bit (the LSB) determines whether the access is a read (A = 1) or a write (A = 0).
Note 5: In the Serial Port Mode, the B bit (the MSB) determines whether the access is a burst access (B = 1) or a single register
access (B = 0).
DS21348/DS21Q348
3.2 Parallel Port Operation
When using the parallel interface on the DS21348 (BIS1 = 0) the user has the option for either
multiplexed bus operation (BIS1 = 0, BIS0 = 0) or non-multiplexed bus operation (BIS1 = 0, BIS0 = 1).
The DS21348 can operate with either Intel or Motorola bus timing configurations. If the PBTS pin is tied
low, Intel timing will be selected; if tied high, Motorola timing will be selected. All Motorola bus signals
are listed in parentheses (). See the timing diagrams in Section 11 for more details.
3.3 Serial Port Operation
Setting BIS1 = 1 and BIS0 = 0 enables the serial bus interface on the DS21348. Port read/write timing is
unrelated to the system transmit and receive timing, allowing asynchronous reads or writes by the host.
See Section 11 for the AC timing of the serial port. All serial port accesses are LSB first. See Figure 3-1,
Figure 3-2, Figure 3-3, and Figure 3-4 for more details.
Reading or writing to the internal registers requires writing one address/command byte prior to
transferring register data. The first bit written (LSB) of the address/command byte specifies whether the
access is a read (1) or a write (0). The next 5 bits identify the register address. Bit 7 is reserved and must
be set to 0 for proper operation.
The last bit (MSB) of the address/command byte is the burst mode bit. When the burst bit is enabled
(B = 1) and a READ operation is performed, addresses 0 through 15h are read sequentially, starting at
address 0h. And when the burst bit is enabled and a WRITE operation is performed, addresses 0 through
16h are written sequentially, starting at address 0h. Burst operation is stopped once address 15h is read.
See Figure 3-5 and Figure 3-6 for more details.
All data transfers are initiated by driving the CS input low. When Input Clock-Edge Select (ICES) is low,
input data is latched on the rising edge of SCLK and when ICES is high, input data is latched on the
falling edge of SCLK. When Output Clock-Edge Select (OCES) is low, data is output on the falling edge
of SCLK and when OCES is high, data is output on the rising edge of SCLK. Data is held until the next
falling or rising edge. All data transfers are terminated if the CS input transitions high. Port control logic
is disabled and SDO is tri-stated when CS is high.
DS21348/DS21Q348
Figure 3-1. Serial Port Operation for Read Access (R = 1) Mode 1
ICES = 1 (sample SDI on the falling edge of SCLK)
OCES = 1 (update SDO on rising edge of SCLK)
Figure 3-2. Serial Port Operation for Read Access Mode 2
ICES = 1 (sample SDI on the falling edge of SCLK)
OCES = 0 (update SDO on falling edge of SCLK)
Figure 3-3. Serial Port Operation for Read Access Mode 3
ICES = 0 (sample SDI on the rising edge of SCLK)
OCES = 0 (update SDO on falling edge of SCLK) 345678910111213141516
1A0A1A2A32A40BD2D3D4D5D6
SCLK
SDI
SDO
CS
(lsb)(msb)
(lsb)
(msb)
READ ACCESS ENABLED 345678910111213141516
1A0A1A2A3A40BD2D3D4D5D6
SCLK
SDI
SDO
CS
(lsb)(msb)
(lsb)
(msb)345678910111213141516
1A0A1A2A3A40BD2D3D4D5D6
SCLK
SDI
SDO
CS
(lsb)(msb)
(lsb)
(msb)
DS21348/DS21Q348
Figure 3-4. Serial Port Operation for Read Access Mode 4
ICES = 0 (sample SDI on the rising edge of SCLK)
OCES = 1 (update SDO on rising edge of SCLK)
Figure 3-5. Serial Port Operation for Write Access (R = 0) Modes 1 and 2
ICES = 1 (sample SDI on the falling edge of SCLK)
Figure 3-6. Serial Port Operation for Write Access (R = 0) Modes 3 and 4
ICES = 0 (sample SDI on the rising edge of SCLK) 345678910111213141516D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0
1A0A1A2A3A5A40BD0D0D0D0
SCLK
SDI
SDO
CS
(lsb)(msb)
(lsb)(msb)D2D3D4D5 D6 D0D7 2345678910111213141516SCLK
CS
0A0A1A2A3A40B
(msb)
SDI
SDOD2D3D4 D5D7
(lsb)(msb) D6
(lsb)
WRITE ACCESS ENABLED 345678910111213141516SCLK
CS
0A0A1A2A3A40B
(msb)
SDI
SDOD2D3D4D5D7
(lsb)(msb) D6
(lsb)
WRITE ACCESS ENABLED
DS21348/DS21Q348
4. CONTROL REGISTERS
CCR1 (00H): COMMON CONTROL REGISTER 1
(MSB) (LSB)
ETS NRZE RCLA ECUE JAMUX TTOJ TTOR LOTCMC
SYMBOL POSITION DESCRIPTION
ETS CCR1.7 E1/T1 Select.
0 = E1
1 = T1
NRZE CCR1.6 NRZ Enable.
0 = Bipolar data at RPOS/RNEG and TPOS/TNEG
1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a positive
going pulse when device receives a BPV, CV, or EXZ. See Figure 1-2
and Figure 1-3.
RCLA CCR1.5 Receive Carrier Loss Alternate Criteria.
0 = RCL declared upon 255 (E1) or 192 (T1) consecutive zeros
1 = RCL declared upon 2048 (E1) or 1544 (T1) consecutive zeros
ECUE CCR1.4 Error Counter Update Enable. A 0 to 1 transition forces the next clock
cycle to load the error counter registers with the latest counts and reset
the counters. The user must wait a minimum of two clocks cycles (976ns
for E1 and 1296ns for T1) before reading the error count registers to
allow for a proper update. See Section 4 and Figure 1-2 for details.
JAMUX CCR1.3 Jitter Attenuator MUX. Controls the source for JACLK (Figure 1-1).
0 = JACLK sourced from MCLK (2.048MHz or 1.544MHz at MCLK)
1 = JACLK sourced from internal PLL (2.048MHz at MCLK)
TTOJ CCR1.2 TCLK to JACLK. Internally connects TCLK to JACLK (Figure 1-3).
0 = disabled
1 = enabled
TTOR CCR1.1 TCLK to RCLK. Internally connects TCLK to RCLK (Figure 1-3).
0 = disabled
1 = enabled
LOTCMC CCR1.0 Loss Of Transmit Clock Mux Control. Determines whether the
transmit logic should switch to JACLK if the TCLK input should fail to
transition (Figure 1-3).
0 = do not switch to JACLK if TCLK stops
1 = switch to JACLK if TCLK stops
DS21348/DS21Q348
Table 4-1. MCLK Selection
MCLK
(MHz)
JAMUX
(CCR1.3)
ETS
(CCR1.7)
2.048 0 0
2.048 1 1
1.544 0 1
CCR2 (01H): COMMON CONTROL REGISTER 2
(MSB) (LSB)
P25S n/a SCLD CLDS RHBE THBE TCES RCES
SYMBOL POSITION DESCRIPTION
P25S CCR2.7 Pin 25 Select. Forced to logic 0 in hardware mode.
0 = toggles high during a Receive Carrier Loss condition
1 = toggles high if TCLK does not transition for at least 5µs
- CCR2.6 Not Assigned. Should be set to zero when written to.
SCLD CCR2.5 Short Circuit Limit Disable (ETS = 0). Controls the 50 mA (rms)
current limiter.
0 = enable 50 mA current limiter
1 = DISABLE 50 MA CURRENT LIMITER
CLDS CCR2.4 Custom Line Driver Select. Setting this bit to a one will redefine the
operation of the transmit line driver. When this bit is set to a one and
CCR4.5 = CCR4.6 = CCR4.7 = 0, then the device will generate a square
wave at the TTIP and TRING outputs instead of a normal waveform.
When this bit is set to a one and CCR4.5 = CCR4.6 = CCR4.7 ≠ 0, then
the device will force TTIP and TRING outputs to become open drain
drivers instead of their normal push-pull operation. This bit should be set
to zero for normal operation of the device. Contact the factory for more
details on how to use this bit.
RHBE CCR2.3 Receive HDB3/B8ZS Enable. See Figure 1-2.
0 = enable HDB3 (E1)/B8ZS (T1)
1 = disable HDB3 (E1)/B8ZS (T1)
THBE CCR2.2 Transmit HDB3/B8ZS Enable. See Figure 1-3.
0 = enable HDB3 (E1)/B8ZS (T1)
1 = disable HDB3 (E1)/B8ZS (T1)
TCES CCR2.1 Transmit Clock Edge Select. Selects which TCLK edge to sample TPOS
and TNEG. See Figure 1-3.
0 = sample TPOS and TNEG on falling edge of TCLK
1 = sample TPOS and TNEG on rising edge of TCLK
RCES CCR2.0 Receive Clock Edge Select. Selects which RCLK edge to update RPOS
and RNEG. See Figure 1-2.
0 = update RPOS and RNEG on rising edge of RCLK
1 = update RPOS and RNEG on falling edge of RCLK
DS21348/DS21Q348
CCR3 (02H): COMMON CONTROL REGISTER 3
(MSB) (LSB)
TUA1 ATUA1 TAOZ TPRBSE TLCE LIRST IBPV IBE
SYMBOL POSITION DESCRIPTION
TUA1 CCR3.7 Transmit Unframed All Ones. The polarity of this bit is set such that the
device will transmit an all ones pattern on power-up or device reset. This
bit must be set to a one to allow the device to transmit data. The
transmission of this data pattern is always timed off of the JACLK (See
Figure 1-1).
0 = transmit all ones at TTIP and TRING
1 = transmit data normally
ATUA1 CCR3.6 Automatic Transmit Unframed All Ones. Automatically transmit an
unframed all ones pattern at TTIP and TRING during a receive carrier loss
(RCL) condition or receive all ones condition.
0 = disabled
1 = enabled
TAOZ CCR3.5 Transmit Alternate Ones and Zeros. Transmit a …101010… pattern at
TTIP and TRING. The transmission of this data pattern is always timed
off of TCLK (Figure 1-1).
0 = disabled
1 = enabled
TPRBSE CCR3.4 Transmit PRBS Enable. Transmit a 215 - 1 (E1) or a 220 - 1 (T1) PRBS at
TTIP and TRING (Figure 1-3).
0 = disabled
1 = enabled
TLCE CCR3.3 Transmit Loop Code Enable. Enables the transmit side to transmit the
loop up code in the Transmit Code Definition registers (TCD1 and
TCD2). See Section 4 and Figure 1-3 for details.
0 = disabled
1 = enabled
LIRST CCR3.2 Line Interface Reset. Setting this bit from a zero to a one will initiate an
internal reset that resets the clock recovery state machine and re-centers
the jitter attenuator. Normally this bit is only toggled on power-up. Must
be cleared and set again for a subsequent reset.
IBPV CCR3.1 Insert BPV. A 0 to 1 transition on this bit will cause a single BiPolar
Violation (BPV) to be inserted into the transmit data stream. Once this bit
has been toggled from a 0 to a 1, the device waits for the next occurrence
of three consecutive ones to insert the BPV. This bit must be cleared and
set again for a subsequent error to be inserted (Figure 1-3).
IBE CCR3.0 Insert Bit Error. A 0 to 1 transition on this bit will cause a single logic
error to be inserted into the transmit data stream. This bit must be cleared
and set again for a subsequent error to be inserted (Figure 1-3).
DS21348/DS21Q348
4.1 Device Power-Up and Reset
The DS21348 will reset itself upon power-up setting all writeable registers to 00h and clear the status and
information registers. CCR3.7 (TUA1) = 0 results in the LIU transmitting unframed all ones. After the
power supplies have settled following power-up, initialize all control registers to the desired settings, then
toggle the LIRST bit (CCR3.2). At anytime, the DS21348 can be reset to the default settings by bringing
HRST (pin 29) low (level triggered) or by powering down and powering up again.
CCR4 (03H): COMMON CONTROL REGISTER 4
(MSB) (LSB)
L2 L1 L0 EGL JAS JABDS DJA TPD
SYMBOL POSITION DESCRIPTION
L2 CCR4.7 Line Build Out Select Bit 2. Sets the transmitter build out; see Table 7-1
for E1 and Table 7-2 for T1.
L1 CCR4.6 Line Build Out Select Bit 1. Sets the transmitter build out; see Table 7-1
for E1 and Table 7-2 for T1.
L0 CCR4.5 Line Build Out Select Bit 0. Sets the transmitter build out; see Table 7-1
for E1 and Table 7-2 for T1.
EGL CCR4.4 Receive Equalizer Gain Limit. This bit controls the sensitivity of the
receive equalizer. See Table 4-2.
JAS CCR4.3 Jitter Attenuator Select.
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
JABDS CCR4.2 Jitter Attenuator Buffer Depth Select.
0 = 128 bits
1 = 32 bits (use for delay-sensitive applications)
DJA CCR4.1 Disable Jitter Attenuator.
0 = jitter attenuator enabled
1 = jitter attenuator disabled
TPD CCR4.0 Transmit Power-Down.
0 = normal transmitter operation
1 = powers down the transmitter and tri-states the TTIP and TRING pins
Table 4-2. Receive Equalizer Sensitivity Settings
EGL
(CCR4.4)
ETS
(CCR1.7)
RECEIVE
SENSITIVITY 0 (E1) -12dB (short haul) 0 (E1) -43dB (long haul) 1 (T1) -30dB (limited long haul) 1 (T1) -36dB (long haul)
DS21348/DS21Q348
CCR5 (04H): COMMON CONTROL REGISTER 5
(MSB) (LSB)
BPCS1 BPCS0 MM1 MM0 RSCLKE TSCLKE RT1 RT0
SYMBOL POSITION DESCRIPTION
BPCS1 CCR5.7 Backplane Clock Select 1. See Table 4-3 for details.
BPCS0 CCR5.6 Backplane Clock Select 0. See Table 4-3 for details
MM1 CCR5.5 Monitor Mode 1. See Table 4-4.
MM0 CCR5.4 Monitor Mode 0. See Table 4-4.
RSCLKE CCR5.3 Receive Synchronization Clock Enable.
This control bit determines whether the line receiver should handle normal
T1/E1 signals or a synchronization signal.
E1 mode:
0 = receive normal E1 signal (Section 6 of G.703)
1 = receive 2.048MHz synchronization signal (Section 10 of G.703)
T1 mode:
0 = receive normal T1 signal
1 = receive 1.544MHz synchronization signal
TSCLKE CCR5.2 Transmit Synchronization Clock Enable.
This control bit determines whether the transmitter should transmit normal
T1/E1 signals or a synchronized signal.
E1 mode:
0 = transmit normal E1 signal (Section 6 of G.703)
1 = transmit 2.048MHz synchronization signal (Section 10 of G.703)
T1 mode:
0 = transmit normal T1 signal
1 = transmit 1.544MHz synchronization signal
RT1 CCR5.1 Receive Termination 1. See Table 4-5 for details.
RT0 CCR5.0 Receive Termination 0. See Table 4-5 for details.
DS21348/DS21Q348
Table 4-3. Backplane Clock Select
BPCS1
(CCR5.7)
BPCS0
(CCR5.6)
BPCLK
FREQUENCY
0 0 16.384MHz
0 1 8.192MHz
1 0 4.096MHz
1 1 2.048MHz
Table 4-4. Monitor Gain Settings
MM1
(CCR5.5)
MM0
(CCR5.4)
INTERNAL LINEAR
GAIN BOOST
0 0 Normal operation
(no boost)
0 1 20dB
1 0 26dB
1 1 32dB
Table 4-5. Internal Rx Termination Select
RT1
(CCR5.1)
RT0
(CCR5.0)
INTERNAL RECEIVE
TERMINATION CONFIGURATION
0 0 Internal receive-side termination disabled
0 1 Internal receive-side 120Ω enabled
1 0 Internal receive-side 100Ω enabled
1 1 Internal receive-side 75Ω enabled
DS21348/DS21Q348
CCR6 (05H): COMMON CONTROL REGISTER 6
(MSB) (LSB)
LLB RLB ARLBE ALB RJAB ECRS2 ECRS1 ECRS0
SYMBOL POSITION DESCRIPTION
LLB CCR6.7 Local Loopback. In Local Loopback (LLB), transmit data will be looped back
to the receive path passing through the jitter attenuator if it is enabled. Data in
the transmit path will act as normal. See Figure 1-1 and Section 6.2.2 for
details.
0 = loopback disabled
1 = loopback enabled
RLB CCR6.6 Remote Loopback. In Remote Loopback (RLB), data output from the
clock/data recovery circuitry will be looped back to the transmit path passing
through the jitter attenuator if it is enabled. Data in the receive path will act as
normal while data presented at TPOS and TNEG will be ignored.
See Figure 1-1 and Section 6.2.1 for details.
0 = loopback disabled
1 = loopback enabled
ARLBE CCR6.5 Automatic Remote Loopback Enable and Reset. When this bit is set high,
the device will automatically go into remote loopback when it detects loop up
code programmed into the Receive Loop-Up Code Definition Registers
(RUPCD1 and RUPCD2) for a minimum of 5 seconds and it will also set the
RIR2.1 status bit. Once in a RLB state, it will remain in this state until it has
detected the loop code programmed into the Receive Loop-Down Code
Definition Registers (RDNCD1 and RDNCD2) for a minimum of 5 seconds at
which point it will force the device out of RLB and clear RIR2.1. The
automatic RLB circuitry can be reset by toggling this bit from a 1 to a 0. The
action of the automatic remote loopback circuitry is logically ORed with the
RLB (CCR6.6) control bit (i.e., either one can cause a RLB to occur).
ALB CCR6.4 Analog Loopback. In Analog Loopback (ALB), signals at TTIP and TRING
will be internally connected to RTIP and RRING. The incoming signals, from
the line, at RTIP and RRING will be ignored. The signals at TTIP and TRING
will be transmitted as normal. See Figure 1-1 and Section 6.2.3 for more details.
0 = loopback disabled
1 = loopback enabled
RJAB CCR6.3 RCLK Jitter Attenuator Bypass. This control bit allows the receive recovered
clock and data to bypass the jitter attenuation while still allowing the BPCLK
output to use the jitter attenuator. See Figure 1-1 and Section 7.3 for details.
0 = disabled
1 = enabled
ECRS2 CCR6.2 Error Count Register Select 2. See Section 6.4 for details.
ECRS1 CCR6.1
Error Count Register Select 1. See Section 6.4 for details.
DS21348/DS21Q348
5. STATUS REGISTERS
There are three registers that contain information on the current real-time status of the device, Status
Register (SR) and Receive Information Registers 1 and 2 (RIR1/RIR2). When a particular event has
occurred (or is occurring), the appropriate bit in one of these three registers will be set to a one. Some of
the bits in SR, RIR1, and RIR2 are latched bits and some are real time bits. The register descriptions
below list which status bits are latched and which are real time bits. For latched status bits, when an event
or an alarm occurs the bit is set to a one and will remain set until the user reads that bit. The bit will be
cleared when it is read and it will not be set again until the event has occurred again. Two of the latched
status bits (RUA1 and RCL) will remain set after reading if the alarm is still present.
The user will always precede a read of any of the three status registers with a write. The byte written to
the register will inform the DS21348 which bits the user wishes to read and have cleared. The user will
write a byte to one of these registers with a one in the bit positions to be read and a zero in the other bit
positions. When a one is written to a bit location, that location will be updated with the latest information.
When a zero is written to a bit position, that bit position will not be updated and the previous value will
be held. A write to the status and information registers will be immediately followed by a read of the
same register. The read result should be logically ANDed with the mask byte that was just written and
this value should be written back into the same register to insure that bit does indeed clear. This second
write step is necessary because the alarms and events in the status registers occur asynchronously with
respect to their access via the parallel port. This write-read-write scheme allows an external
microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the
register. This operation is key in controlling the DS21348 with higher-order software languages.
The bits in the SR register have the unique ability to initiate a hardware interrupt via the INT output pin.
Each of the alarms and events in the SR can be either masked or unmasked from the interrupt pin via the
Interrupt Mask Register (IMR). The interrupts caused by the RCL, RUA1, and LOTC bits in SR act
differently than the interrupts caused by the other status bits in SR. The RCL, RUA1 and LOTC bits will
force the INT pin low whenever they change state (i.e., go active or inactive). The INT pin will be
allowed to return high (if no other interrupts are present) when the user reads the alarm bit that caused the
interrupt to occur even if the alarm is still present. The other status bits in SR can force the INT pin low
when they are set. The INT pin will be allowed to return high (if no other interrupts are present) when the
user reads the event bit that caused the interrupt to occur.
Table 5-1. Received Alarm Criteria
ALARM E1/T1 SET CRITERIA CLEAR CRITERIA
RUA1 E1 Less than 2 zeros in two frames (512 bits) More than 2 zeros in two frames (512
bits)
RUA1 T1 Over a 3ms window, five or fewer zeros
are received
Over a 3ms window, six or more zeros
are received
RCL1 E1 255 (or 2048)2 consecutive zeros received
(G.775)
In 255 bit times, at least 32 ones are
received
RCL1 T1 192 (or 1544)2 consecutive zeros are
received
14 or more ones out of 112 possible
bit positions are received starting with
the first one received
DS21348/DS21Q348
SR (06H): STATUS REGISTER
(MSB) (LSB)
LUP LDN LOTC RUA1 RCL TCLE TOCD PRBSD
SYMBOL POSITION DESCRIPTION
LUP
(latched)
SR.7 Loop-Up Code Detected. Set when the loop-up code defined in registers
RUPCD1 and RUPCD2 is being received. See Section 4 for details.
LDN
(latched)
SR.6 Loop-Down Code Detected. Set when the loop-down code defined in
registers RDNCD1 and RDNCD2 is being received. See Section 4 for
details.
LOTC
(real time)
SR.5 Loss of Transmit Clock. Set when the TCLK pin has not transitioned for
5µsec (±2µs). Will force the LOTC pin high.
RUA1
(latched)
SR.4 Receive Unframed All Ones. Set when an unframed all ones code is
received at RRING and RTIP. See Table 5-1 for details.
RCL
(latched)
SR.3 Receive Carrier Loss. Set when a receive carrier loss condition exists at
RRING and RTIP. See Table 5-1 for details.
TCLE
(real time)
SR.2 Transmit Current Limit Exceeded. Set when the 50mA (RMS) current
limiter is activated whether the current limiter is enabled or not.
TOCD
(real time)
SR.1 Transmit Open Circuit Detect. Set when the device detects that the TTIP
and TRING outputs are open circuited.
PRBSD
(real time)
SR.0 PRBS Detect. Set when the receive-side detects a 215 - 1 (E1) or a 220 - 1
(T1) Pseudo-Random Bit Sequence (PRBS).
DS21348/DS21Q348
IMR (07H): INTERRUPT MASK REGISTER
(MSB) (LSB)
LUP LDN LOTC RUA1 RCL TCLE TOCD PRBSD
SYMBOL POSITION DESCRIPTION
LUP IMR.7 Loop-Up Code Detected.
0 = interrupt masked
1 = interrupt enabled
LDN IMR.6 Loop-Down Code Detected.
0 = interrupt masked
1 = interrupt enabled
LOTC IMR.5 Loss of Transmit Clock.
0 = interrupt masked
1 = interrupt enabled
RUA1 IMR.4 Receive Unframed All Ones.
0 = interrupt masked
1 = interrupt enabled
RCL IMR.3 Receive Carrier Loss.
0 = interrupt masked
1 = interrupt enabled
TCLE IMR.2 Transmit Current Limiter Exceeded.
0 = interrupt masked
1 = interrupt enabled
TOCD IMR.1 Transmit Open Circuit Detect.
0 = interrupt masked
1 = interrupt enabled
PRBSD IMR.0 PRBS Detection.
0 = interrupt masked
1 = interrupt enabled
