DS2045L-100# Fast Delivery |IC PHOENIX CO.,LIMITED

DS2045L-100# ,3.3V Single-Piece 1Mb Nonvolatile SRAMApplicationsRAID Systems and Servers POS TerminalsIndustrial Controllers Data-Acquisition SystemsPi ..
DS2045W-100# ,3.3V Single-Piece 1Mb Nonvolatile SRAMApplicationsRAID Systems and Servers POS TerminalsIndustrial Controllers Data-Acquisition SystemsPi ..
DS2045Y-100# ,Single-Piece 1Mb Nonvolatile SRAMFeatures2♦ Single-Piece, Reflowable, 27mm PBGA PackageThe DS2045 is a 1Mb reflowable nonvolatile (N ..
DS2045Y-70# ,Single-Piece 1Mb Nonvolatile SRAMDS2045Y/ABRev 4; 10/06DS2045Y/AB Single-Piece 1MbNonvolatile SRAM
DS2050W-100# ,3.3V Single-Piece 4Mb Nonvolatile SRAMApplicationsRAID Systems and Servers POS TerminalsIndustrial Controllers Routers/SwitchesPin Config ..
DS2064 ,8K x 8 Static RAMFEATURES PIN ASSIGNMENT• Low power CMOS designNC 1 28 VCC• Standby current2 27A12 WE50 nA max at t ..

DS2045L-100#
3.3V Single-Piece 1Mb Nonvolatile SRAM
General Description
The DS2045L is a 1Mb reflowable nonvolatile (NV)
SRAM, which consists of a static RAM (SRAM), an NV
controller, and an internal rechargeable manganese
lithium (ML) battery. These components are encased in
a surface-mount module with a 256-ball BGA footprint.
Whenever VCCis applied to the module, it recharges the
ML battery, powers the SRAM from the external power
source, and allows the contents of the SRAM to be mod-
ified. When VCC is powered down or out-of-tolerance,
the controller write-protects the SRAM’s contents and
powers the SRAM from the battery. The DS2045L also
contains a power-supply monitor output, RST, which can
be used as a CPU supervisor for a microprocessor.
Applications
RAID Systems and ServersPOS Terminals
Industrial ControllersData-Acquisition Systems
GamingFire Alarms
Router/SwitchesPLCs
FeaturesSingle-Piece, Reflowable, 27mm2BGA Package
FootprintInternal ML Battery and ChargerUnconditionally Write-Protects SRAM when VCC
is Out-of-ToleranceAutomatically Switches to Battery Supply when
VCC Power Failures OccurInternal Power-Supply Monitor Detects Power Fail
Below Nominal VCC (3.3V)Reset Output can be used as a CPU Supervisor
for a MicroprocessorIndustrial Temperature Range (-40°C to +85°C)UL Recognized
DS2045L
DS2045L 3.3V Single-Piece 1Mb
Nonvolatile SRAM
Rev 3; 10/06
Ordering Information
Pin Configuration appears at end of data sheet.
PARTTEMP RANGEPIN-PACKAGESPEED (ns)SUPPLY TOLERANCE
DS2045L-100#-40°C to +85°C256 Ball 27mm2 BGA Module1003.3V ±0.3V
Typical Operating Circuit
P4.0
P3.6
P3.7
P1.0–7
AD0–AD7
P4.4
P2.0–7
P3.2RST
A8–15
A0–7
A16
DQ0–7
8 BITS
8 BITS
8 BITS
(CE0)
(INT0)
MICROPROCESSOR
DS2045L
128k x 8
NV SRAM
(WR)
(RD)
#Denotes a RoHS-compliant device that may include lead that is exempt under the RoHS requirements.
DS2045L
DS2045L 3.3V Single-Piece 1Mb
Nonvolatile SRAM
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
(TA= -40°C to +85°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage on Any Pin Relative to Ground.................-0.3V to +4.6V
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range...............................-40°C to +85°C
Soldering Temperature.....................See IPC/JEDEC J-STD-020
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Supply VoltageVCC3.03.33.6V
Input Logic 1VIH2.2VCCV
Input Logic 0VIL00.4V
CAPACITANCE
(TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Input CapacitanceCINNot tested7pF
Input/Output CapacitanceCOUTNot tested7pF
DC ELECTRICAL CHARACTERISTICS
(VCC= 3.3V ±0.3V, TA= -40°C to +85°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Input Leakage CurrentIIL-1.0+1.0µA
I/O Leakage CurrentIIOCE = VCC-1.0+1.0µA
Output-Current HighIOHAt 2.4V-1.0mA
Output-Current LowIOLAt 0.4V2.0mA
Output-Current Low RSTIOL RSTAt 0.4V (Note 1)10.0mA
ICCS1CE = 2.2V0.52Standby CurrentICCS2CE = VCC - 0.2V0.21mA
Operating CurrentICCO1tRC = 200ns, outputs open50mA
Write Protection VoltageVTP2.82.93.0V
DS2045L
DS2045L 3.3V Single-Piece 1Mb
Nonvolatile SRAM
POWER-DOWN/POWER-UP TIMING
(TA= -40°C to +85°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
VCC Fail Detect to CE and WE InactivetPD(Note 7)1.5µs
VCC Slew from VTP to 0VtF150µs
VCC Slew from 0V to VTPtR150µs
VCC Valid to CE and WE InactivetPU2ms
VCC Valid to End of Write ProtectiontREC125ms
VCC Fail Detect to RST ActivetRPD(Note 1)3.0µs
VCC Valid to RST InactivetRPU(Note 1)225350525ms
DATA RETENTION
(TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Expected Data-Retention Time (Per Charge)tDR(Note 8)1116Weeks
AC ELECTRICAL CHARACTERISTICS
(VCC= 3.3V ±0.3V, TA= -40°C to +85°C.)
DS2045L-100PARAMETERSYMBOLCONDITIONSMINMAXUNITS
Read Cycle TimetRC100ns
Access TimetACC100ns
OE to Output ValidtOE50ns
CE to Output ValidtCO100ns
OE or CE to Output ActivetCOE(Note 2)5ns
Output High Impedance from
Deselection
tOD(Note 2)35ns
Output Hold from Address ChangetOH5ns
Write Cycle TimetWC100ns
Write Pulse WidthtWP(Note 3)75ns
Address Setup TimetAW0ns
tWR1(Note 4)5Write Recovery TimetWR2(Note 5)20ns
Output High Impedance from WEtODW(Note 2)35ns
Output Active from WEtOEW(Note 2)5ns
Data Setup TimetDS(Note 6)40ns
tDH1(Note 4)0Data Hold TimetDH2(Note 5)20ns
Input Pulse Levels:VIL= 0.0V, VIH= 2.7V
Input Pulse Rise and Fall Times:5ns
Input and Output Timing Reference Level:1.5V
Output Load:1 TTL Gate + CL(100pF) including scope and jig
AC TEST CONDITIONS
DS2045L
DS2045L 3.3V Single-Piece 1Mb
Nonvolatile SRAM
Read Cycle
OUTPUT
DATA VALID
tRC
tACC
tCO
tOE
tOH
tOD
tODtCOE
tCOE
VIHVIH
VIL
VOH
VOL
VOH
VOL
VIL
VIH
ADDRESSES
DOUT
(SEE NOTE 9.)
VIH
VIHVIH
VIH
VIL
VIL
VIL
DS2045L
DS2045L 3.3V Single-Piece 1Mb
Nonvolatile SRAM
Write Cycle 1
DATA IN STABLE
ADDRESSES
DOUT
DIN
tWC
VIH
VIH
VIH
VIH
VIL
VIL
VIL
HIGH
IMPEDANCE
VIH
VIH
VIL
VIL
VIH
VIL
VIL
VIL
VIL
tAW
tWP
tOEW
tDH1tDS
tODW
tWR1
(SEE NOTES 2, 3, 4, 6, 10–13.)
Write Cycle 2
tWC
tAW
tDH2tDS
tCOEtODW
tWPtWR2
VIH
VIL
VIHADDRESSES
DOUT
DIN
VIL
VIH
VIL
VIH
VIL
VIL
VIL
VIL
VIH
VIH
VIL
VIH
DATA IN STABLE
VIL
VIH
VIL
(SEE NOTES 2, 3, 5, 6, 10–13.)
DS2045L
DS2045L 3.3V Single-Piece 1Mb
Nonvolatile SRAM
Power-Down/Power-Up Condition
tDR
tPU
tPD
tRPUtRPD
SLEWS WITH
VCC
VOL
VIH
VOL
tREC
VCC
VTP
~2.5V
CE,
RST
BACKUP CURRENT
SUPPLIED FROM
LITHIUM BATTERY
(SEE NOTES 1, 7.)
Note 1:RSTis an open-drain output and cannot source current. An external pullup resistor should be connected to this pin to real-
ize a logic-high level.
Note 2:These parameters are sampled with a 5pF load and are not 100% tested.
Note 3:tWPis specified as the logical AND of CEand WE. tWPis measured from the latter of CEor WEgoing low to the earlier ofor WEgoing high.
Note 4:tWR1and tDH1are measured from WEgoing high.
Note 5:tWR2and tDH2are measured from CEgoing high.
Note 6:tDSis measured from the earlier of CEor WEgoing high.
Note 7:In a power-down condition, the voltage on any pin can not exceed the voltage on VCC.
Note 8:The expected tDRis defined as accumulative time in the absence of VCCstarting from the time power is first applied by the
user. Minimum expected data-retention time is based on a maximum of two +230°C convection solder reflow exposures,
followed by a fully charged cell. Full charge occurs with the initial application of VCCfor a minimum of 96 hours. This para-
meter is assured by component selection, process control, and design. It is not measured directly in production testing.
Note 9:WEis high for a read cycle.
Note 10:OE= VIHor VIL. If OE= VIHduring write cycle, the output buffers remain in a high-impedance state.
Note 11:If the CElow transition occurs simultaneously with or latter than the WElow transition, the output buffers remain in a high-
impedance state during this period.
Note 12:If the CEhigh transition occurs prior to or simultaneously with the WEhigh transition, the output buffers remain in a high-
impedance state during this period.
Note 13:If WEis low or the WElow transition occurs prior to or simultaneously with the CElow transition, the output buffers remain
in a high-impedance state during this period.
Note 14:DS2045L BGA modules are recognized by Underwriters Laboratory (UL) under file E99151.

Partno	Mfg	Dc	Qty	Available	Descript
DS2045L-100# \|DS2045L100#	MAIXM	N/a	1500	avai	3.3V Single-Piece 1Mb Nonvolatile SRAM