DS2009 ,512 x 9 FIFO ChipPIN DESCRIPTION
W - WRITE
A - READ
ATs - RESET
FL/RT - First Load/Retransmit
00.3 - Data In
0 ..
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DS2009
512 x 9 FIFO Chip
DS2009
@ALLA§
DS2009
512 x 9 FIFO Chip
SEMICONDUCTOR
FEATURES PIN ASSIGNMENT
q . -. . - - . -
First In, first out memory based architecture w E let 28
q Flexible 512 x 9 organization 08': 2 27
D312 a 26
. Low-power HCMOS technology D2C 4 25
D1C 5 24
. Asynchronous and simultaneous read/write 2°C 6 23
LI d 7 22
q Bidirectional applications FF E 5 21
00C g 20
. Fully expandable by word width or depth 011: 10 19
02:1 11 18
. Empty and full warning flags 0an 12 17
08:113 16:04 RRtauitr,'tR
. Half-full flag capability in single-device mode GNDC! 14 15 ii CY C3 5 a © t3
. Retransmit capability
. High performance
. Available in 35 ns, 50 ns, 65 ns, 80 ns, and 120 ns
access times
q Optional industrial temperature range -40°C to +85°C
available, designated N
DESCRIPTION
The D82009 512 x 9 FIFO Chip implements a first-in,
first-out algorithm featuring asynchronous read/write
operations, full, empty and haIf-full flags, and unlimited
expansion capability in both word size and depth. The
main application ofthe DS2009 is as a rate buffer, sourc-
ing and absorbing data at different rates (e.g., interfac-
ing fast processors and slow peripherals). The full and
empty flags are provided to prevent data overflow and
underflow, A half-full flag is available in the single-de-
28-Pin DIP(800 and 600 Mil) 32-Pin PLCC
See Mech. Drawings See Mech. Drawmg
Pgs. 964 & 966 Pg. 979
BIN DESCRIPTION
w - WRITE
A - READ
ATS - RESET
A7A'i' - First Load/Retransmit
Do 8 - Data In
00 8 - Data Out
W - Expansion In
X0/HF - Expansion Out/Half Full
W: - Full Flag
Ele - Empty Flag
Vcc - 5 Volts
GND - Ground
NC - No Connect
vice and width-expansion configurations. The data is
loaded and emptied on a first-in, first-out (FIFO) basis,
and the latency for the retrieval of data is approximately
one load cycle (write). Since the writes and reads are
internally sequential, thereby requiring no address infor-
mation, the pinout definition will serve this and future
higher-density devices. The ninth bit is provided to sup-
port control or parity functions.
EELHLBU nuaqeua GS' C:
Copyright © 1993 Dallas Semiconductor Corporation
Printed in USA.
OPERATION
Unlike conventional shift register-based FlFOs, the
D82009 employs a memory-based architecture where-
in a byte written into the device does not ripple through.
Instead, a byte written into the DS2009 is stored at a
specific location where it remains until over-written. The
byte can be read and re-read as often as desired.
Twin address pointers (ring counters) automatically
generate the address required for each write and read
operation. The empty/full flag circuit prevents illogical
operations, such as reading unwritten bytes (reading
while empty) or over-writing unread bytes (writing while
full). Once a byte stored at a given address has been
read, it can be over-written.
Address pointers automatically loop back to address
zero after reaching address 511 . The empty/full status
of the FIFO is therefore a function of the distance be-
tween the pointers, not of their absolute location. As
BLOCK DIAGRAM Figure 1
long as the pointers do not catch one another, the FIFO
can be written and read continuously without ever be-
coming full or empty.
Resetting the FIFO simply resets the address pointers
to address zero. Pulsing retransmit resets the read ad-
dress pointerwithout affecting the write address pointer.
With conventional FIFOs, implementation of a larger
FIFO is accomplished by cascading the individual Fi-
FOs. The penalty of cascading is often unacceptable
rippIe-throughdelays. The D82009 allows implements
tion of very large FlFOs with no timing penalties. The
memory-based architecture of the DS2009 can connect
the read, write, data in, and data out lines ofthe DS2009
in parallel. The write and read control circuits ofthe indi-
vidual FIFOs are then automatically enabled and dis-
abled through the expansion in and expansion out pins
as appropriate (see the "Expansion Timing" section for
a more complete discussion).
thrth, / l / t> ara,
—> A-----
INPUT OUTPUT
BUFFER BUFFER
- WRITE READ -
w -tr WRITE -i-,, ADDRESS ----> 512 x9 A-- ADDRESS Rt-o- A- R
CONTROL POINTER MEMORYARRAY POINTER CONTROL
A t t A
- FLAG
FF < o LOGIC _ tr E
EXPANSION LOGIC -
XI ---------------+ tr X0/HF
----------> I
RESET/REI’RANSMIT -
RS 9 LOGIC 4 FURT
051994 2/14
E EELHLBU 00091393 5%l III
