DS1996L-F5 ,64kbit Memory iButtonTMFEATURES§ Unique, factory-lasered and tested 64-bit§ Easily affixed with self-stick adhesiveregistr ..
DS1E-ML2-DC3V , HIGHLY SENSITIVE 1500 V FCC SURGE WITHSTANDING MINIATURE RELAY
DS1E-ML2-DC5V , HIGHLY SENSITIVE 1500 V FCC SURGE WITHSTANDING MINIATURE RELAY
DS1E-S-DC12V , HIGHLY SENSITIVE 1500 V FCC SURGE WITHSTANDING MINIATURE RELAY
DS1E-S-DC48V , HIGHLY SENSITIVE 1500 V FCC SURGE WITHSTANDING MINIATURE RELAY
DS1E-S-DC48V , HIGHLY SENSITIVE 1500 V FCC SURGE WITHSTANDING MINIATURE RELAY
DS1996L-F5
64kbit Memory iButtonTM
SPECIAL FEATURES65536 bits of read/write nonvolatile memoryOverdrive mode boosts communicationspeed to 142k bits per second256-bit scratchpad ensures integrity of data
transferMemory partitioned into 256-bit pages for
packetizing data§ Data integrity assured with strict read/write
protocolsOperating temperature range from -40°C to
+70°COver 10 years of data retention
F5 MICROCANTM
COMMON iButton FEATURESUnique, factory-lasered and tested 64-bit
registration number (8-bit family code + 48-
bit serial number 8-bit CRC tester) assuresabsolute traceability because no two parts are
alikeMultidrop controller for MicroLANDigital identification and information by
momentary contact§ Chip-based data carrier compactly stores
informationData can be accessed while affixed to objectEconomically communicates to bus master
with a single digital signal at 16.3k bits persecondStandard 16 mm diameter and 1-WireTM
protocol ensure compatibility with iButton
family§ Button shape is self-aligning with cup-
shaped probesDurable stainless steel case engraved with
registration number withstands harsh
environments
All dimensions are shown in millimetersEasily affixed with self-stick adhesive
backing, latched by its flange, or locked with
a ring pressed onto its rimPresence detector acknowledges when reader
first applies voltage§ Meets UL#913 (4th Edit); Intrinsically Safe
Apparatus, Approved under Entity Concept
for use in Class I, Division 1, Group A, B, C
and D Locations (application pending)
ORDERING INFORMATIONDS1996L-F5F5 MicroCan
EXAMPLES OF ACCESSORIESDS9096PSelf-Stick Adhesive Pad
DS9101Multi-Purpose Clip
DS9093RAMounting Lock Ring
DS9093FSnap-In FobDS9092iButton Probe64kbit Memory iButtonTM
DATA
GROUND
YYWW REGISTERED RR0C000000FBC52B
17.35
DS1996
iButton DESCRIPTIONThe DS1996 Memory iButton is a rugged read/write data carrier that acts as a localized database that can
be easily accessed with minimal hardware. The nonvolatile memory offers a simple solution to storing
and retrieving vital information pertaining to the object to which the iButton is attached. Data is
transferred serially via the 1-Wire protocol which requires only a single data lead and a ground return.
The scratchpad is an additional page that acts as a buffer when writing to memory. Data is first written tothe scratchpad where it can be read back. After the data has been verified, a copy scratchpad command
will transfer the data to memory. This process ensures data integrity when modifying the memory. A 48-
bit serial number is factory lasered into each DS1996 to provide a guaranteed unique identity which
allows for absolute traceability. The durable MicroCan package is highly resistant to environmental
hazards such as dirt, moisture, and shock. Its compact button-shaped profile is self-aligning with matingreceptacles, allowing the DS1996 to be easily used by human operators. Accessories permit the DS1996
to be mounted on almost any surface including plastic key fobs, photo-ID badges and printed circuit
boards. Applications include access control, work-in-progress tracking, electronic travelers, storage of
calibration constants, and debit tokens.
OVERVIEWThe block diagram in Figure 1 shows the relationships between the major control and memory sections of
the DS1996. The DS1996 has three main data components: 1) 64-bit lasered ROM, 2) 256-bit scratchpad
and 3) 65536-bit SRAM. The hierarchial structure of the 1-Wire protocol is shown in Figure 2. The bus
master must first provide one of the six ROM Function Commands, 1)Read ROM, 2) Match ROM, 3)
Search ROM, 4) Skip ROM, 5) Overdrive-Skip ROM or Overdrive-Match ROM. Upon completion of anoverdrive ROM command byte executed at standard speed, the device will enter Overdrive mode where
all subsequent communication occurs at a higher speed. The protocol required for these ROM Function
Commands is described in Figure 9. After a ROM Function Command is successfully executed, the
memory functions become accessible and the master may provide any one of the four memory function
commands. The protocol for these memory function commands is described in Figure 7. All data read andwritten least significant bit first.
PARASITE POWERThe block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry ”steals” power
whenever the data line is high. The data line will provide sufficient power as long as the specified timing
and voltage requirements are met. The advantages of parasite power are two-fold: 1) by parasiting off thisinput, lithium is conserved and 2) if the lithium is exhausted for any reason, the ROM may still be read
normally.
64-BIT LASERED ROMEach DS1996 contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family
code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits.
(Figure 3.)
The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates
as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the Dallas 1-
Wire Cyclic Redundancy Check is available in the Book of DS19xx iButton Standards.
The shift register bits are initialized to zero. Then starting with the least significant bit of the family code,
one bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial number
DS1996
DS1996 BLOCK DIAGRAM Figure 1
DS1996
HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2
64-BIT LASERED ROM Figure 3MSB LSB MSB LSB MSB LSB
1-WIRE CRC GENERATOR Figure 4OTHER
DS1996
MEMORYThe memory map in Figure 5 shows a 32-byte page called the scratchpad and additional 32-byte pages
called memory. The DS1996 contains 256 pages which comprise the 65536-bit SRAM. The scratchpad is
an additional page that acts as a buffer when writing to memory.
ADDRESS REGISTERS AND TRANSFER STATUSBecause of the serial data transfer, the DS1996 employs three address registers, called TA1, TA2 and E/S
(Figure 6). Registers TA1 and TA2 must be loaded with the target address to which the data will bewritten or from which data will be sent to the master upon a Read command. Register E/S acts like a byte
counter and Transfer Status register. It is used to verify data integrity with Write commands. Therefore,
the master only has read access to this register. The lower five bits of the E/S register indicate the address
of the last byte that has been written to the scratchpad. This address is called Ending Offset. Bit 5 of the
E/S register, called PF or ”partial byte flag,” is set if the number of data bits sent by the master is not aninteger multiple of 8. Bit 6, OF or ”Overflow,” is set if more bits are sent by the master than can be stored
in the scratchpad. Note that the lowest five bits of the target address also determine the address within the
scratchpad, where intermediate storage of data will begin. This address is called byte offset. If the target
address for a Write command is 13CH for example, then the scratchpad will store incoming databeginning at the byte offset 1CH and will be full after only four bytes. The corresponding ending offset in
this example is 1FH. For best economy of speed and efficiency, the target address for writing should
point to the beginning of a new page, i.e., the byte offset will be 0. Thus the full 32-byte capacity of the
scratchpad is available, resulting also in the ending offset of 1FH. However, it is possible to write one or
several contiguous bytes somewhere within a page. The ending offset together with the Partial andOverflow Flag is mainly a means to support the master checking the data integrity after a Write
command. The highest valued bit of the E/S register, called AA or Authorization Accepted, acts as a flag
to indicate that the data stored in the scratchpad has already been copied to the target memory address.
Writing data to the scratchpad clears this flag.
WRITING WITH VERIFICATIONTo write data to the DS1996, the scratchpad has to be used as intermediate storage. First the master issuesthe Write Scratchpad command to specify the desired target address, followed by the data to be written to
the scratchpad. In the next step, the master sends the Read Scratchpad command to read the scratchpad
and to verify data integrity. As preamble to the scratchpad data, the DS1996 sends the requested target
address TA1 and TA2 and the contents of the E/S register. If one of the flags OF or PF is set, data did notarrive correctly in the scratchpad. The master does not need to continue reading; it can start a new trial to
write data to the scratchpad. Similarly, a set AA flag indicates that the Write command was not
recognized by the iButton. If everything went correctly, all three flags are cleared and the ending offset
indicates the address of the last byte written to the scratchpad. Now the master can continue verifying
every data bit. After the master has verified the data, it has to send the Copy Scratchpad command. Thiscommand must be followed exactly by the data of the three address registers TA1, TA2 and E/S as the
master has read them verifying the scratchpad. As soon as the iButton has received these bytes, it will
copy the data to the requested location beginning at the target address.
MEMORY FUNCTION COMMANDSThe “Memory Function Flow Chart” (Figure 7) describes the protocols necessary for accessing the
memory. An example follows the flowchart. The communication between master and DS1996 takes place
either at regular speed (default, OD=0) or at Overdrive Speed (OD=1). If not explicitely set into theOverdrive Mode the DS1996 assumes regular speed.
DS1996
Write Scratchpad Command [0FH]After issuing the write scratchpad command, the master must first provide the 2-byte target address,
followed by the data to be written to the scratchpad. The data will be written to the scratchpad starting at
the byte offset (T4:T0). The ending offset (E4: E0) will be the byte offset at which the bus master has
stopped writing data.
Read Scratchpad Command [AAH]This command is used to verify scratchpad data and target address. After issuing the read scratchpadcommand, the master begins reading. The first two bytes will be the target address. The next byte will be
the ending offset/data status byte (E/S) followed by the scratchpad data beginning at the byte offset (T4:
T0). The master may read data until the end of the scratchpad after which the data read will be all logic
1’s.
DS1996 MEMORY MAP Figure 5
ADDRESS REGISTERS Figure 6
DS1996
MEMORY FUNCTION FLOW CHART Figure 7
DS1996
MEMORY FUNCTION EXAMPLESExample: Write two data bytes to memory locations 0026h and 0027h (the seventh and eighth bytes of
page 1). Read entire memory.
TA2 AUTHORIZATION CODE
E/S
DS1996
Copy Scratchpad [55H]This command is used to copy data from the scratchpad to memory. After issuing the copy scratchpad
command, the master must provide a 3-byte authorization pattern which is obtained by reading the
scratchpad for verification. This pattern must exactly match the data contained in the three address
registers (TA1, TA2, E/S, in that order). If the pattern matches, the AA (Authorization Accepted) flag
will be set and the copy will begin. A logic 0 will be transmitted after the data has been copied until areset pulse is issued by the master. Any attempt to reset the part will be ignored while the copy is in
progress. Copy typically takes 30 µs.
The data to be copied is determined by the three address registers. The scratchpad data from the
beginning offset through the ending offset, will be copied to memory, starting at the target address.Anywhere from 1 to 32 bytes may be copied to memory with this command. Whole bytes are copied
even if only partially written. The AA flag will be cleared only by executing a write scratchpad
command.
Read Memory [F0H]The read memory command may be used to read the entire memory. After issuing the command, themaster must provide the 2-byte target address. After the two bytes, the master reads data beginning from
the target address and may continue until the end of memory, at which point logic 1’s will be read. It is
important to realize that the target address registers will contain the address provided. The ending
offset/data status byte is unaffected.
The hardware of the DS1996 provides a means to accomplish error-free writing to the memory section.
To safeguard reading data in the 1-Wire environment and to simultaneously speed up data transfers, it is
recommended to packetize data into data packets of the size of one memory page each. Such a packet
would typically store a 16-bit CRC with each page of data to ensure rapid, error-free data transfers that
eliminate having to read a page multiple times to determine if the received data is correct or not. (See theBook of DS19xx iButton Standards, Chapter 7 for the recommended file structure to be used with the 1-
Wire environment.)
1–WIRE BUS SYSTEMThe 1-Wire bus is a system which has a single bus master and one or more slaves. In all instances the
DS1996 is a slave device. The bus master is typically a microcontroller. The discussion of this bussystem is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire
signaling (signal types and timing). A 1-Wire protocol defines bus transactions in terms of the bus state
during specified time slots that are initiated on the falling edge of sync pulses from the bus master. For a
more detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton Standards.
HARDWARE CONFIGURATIONThe 1-Wire bus has only a single line by definition; it is important that each device on the bus be able todrive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open
drain connection or 3-state outputs. The 1-Wire port of the DS1996 is open drain with an internal circuit
equivalent to that shown in Figure 8. A multidrop bus consists of a 1-Wire bus with multiple slaves
attached. At regular speed the 1-Wire bus has a maximum data rate of 16.3k bits per second. The speed
can be boosted to 142k bits per second by activating the Overdrive Mode. The 1-Wire bus requires a
pullup resistor of approximately 5 kW.
