DS1990A-F5 ,Serial Number iButtonFEATURES GROUND§ Unique, factory-lasered and tested 64-bitTMregistration number (8-bit family code ..
DS1990A-F5+ ,iButton Serial NumberELECTRICAL CHARACTERISTICS(T = -40°C to +85°C.)APARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IO PI ..
DS1990A-F5+ ,iButton Serial NumberApplicationsa Single Digital Signal at 16.3kbpsAccess Control♦ Button Shape is Self-Aligning with C ..
DS1990A-F5+ ,iButton Serial NumberFeaturesgle data lead and a ground return. Every DS1990A isfactory lasered with a guaranteed unique ..
DS1990R-F3# ,Serial Number iButtonELECTRICAL CHARACTERISTICS(T = -40°C to +85°C.)APARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IO PI ..
DS1990R-F5# ,Serial Number iButtonApplications♦ Button Shape is Self-Aligning with Cup-ShapedAccess ControlProbesWork-In-Progress Tra ..
DS1990A-F5
Serial Number iButton
DS1990A SPECIAL FEATURESUpgrade of DS1990 allows multiple Serial
Number iButtons to reside on a common bus§ Unique 48–bit serial numberLow-cost electronic key for access control8-bit CRC for checking data integrityCan be read in less than 5 msOperating temperature range of -40°C to
+85°C
COMMON iButton FEATURESUnique, factory-lasered and tested 64-bit
registration number (8-bit family code + 48-
bit serial number + 8-bit CRC tester) assures
absolute traceability because no two parts arealikeMultidrop controller for MicroLANDigital identification by momentary contactChip-based data carrier compactly stores
information§ Data can be accessed while affixed to an
objectEconomically communicates to bus master
with a single digital signal at 16.3k bits per
second§ Standard 16 mm diameter and 1-WireTM
protocol ensure compatibility with iButton
familyButton shape is self-aligning with cup-
shaped probes§ Durable stainless steel case engraved with
registration number withstands harsh
environmentsEasily affixed with self-stick adhesive
backing, latched by its flange, or locked witha ring pressed onto its rimPresence detector acknowledges when reader
first applies voltageMeets UL#913 (4th Edit.); Intrinsically Safe
Apparatus, Approved under Entity Concept
F3 MICROCANTM
F5 MICROCANTMAll dimensions shown in millimeters
ORDERING INFORMATIONDS1990A-F3 F3 MicroCan
DS1990A-F5 F5 MicroCan
EXAMPLES OF ACCESSORIESDS9096P Self-Stick Adhesive Pad
DS9101 Multi-Purpose Clip
DS9093RA Mounting Lock Ring
DS9093F Snap-In Fob
DS9092 iButton Probe
Serial Number iButtonTMDATA
GROUND
YYWW REGISTERED RR01
000000FBC52B
DATA
GROUND
c1993
YYWW REGISTERED RR01
000000FBD8B3
17.35
DS1990A
iButton DESCRIPTIONThe DS1990A Serial Number iButton is a rugged data carrier that acts as an electronic registration
number for automatic identification. The DS1990A consists of a factory-lasered, 64-bit ROM thatincludes an unique 48-bit serial number, an 8-bit CRC and an 8-bit Family Code (01h). Data is transferred
serially via the 1-Wire protocol which requires only a single data lead and a ground return. The DS1990A
is fully compatible with the DS1990 Serial Number iButton but provides the additional 1-Wire protocol
capability that allows the Search ROM command to be interpreted by the DS1990A and therefore allows
multiple DS1990A devices to reside on a single data line.
The durable MicroCan package is highly resistant to environmental hazards such as dirt, moisture and
shock. Its compact coin-shaped profile is self-aligning with mating receptacles, allowing the DS1990A to
be used easily by human operators. Accessories permit the DS1990A to be mounted on plastic key tabs,
photo ID badges, printed circuit boards or any smooth surface of an object. Applications include accesscontrol, work-in-progress tracking, tool management and inventory control.
OPERATIONThe DS1990A’s internal ROM is accessed via a single data line. The 48-bit serial number, 8-bit familycode and 8-bit CRC are retrieved using the Dallas 1-Wire protocol. This protocol defines bus transactions
in terms of the bus state during specified time slots that are initiated on the falling edge of sync pulses
from the bus master. All data is read and written least significant bit first.
1-WIRE BUS SYSTEMThe 1-Wire bus is a system which has a single bus master system and one or more slaves. In all instances,
the DS1990A is a slave device. The bus master is typically a microcontroller. The discussion of this bus
system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire
signaling (signal type and timing). For a more detailed protocol description, refer to Chapter 4 of theBook of DS19xx iButton Standards.
Hardware ConfigurationThe 1-Wire bus has only a single line by definition; it is important that each device on the bus be able todrive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have an
open drain connection or 3-state outputs. The DS1990A is an open drain part with an internal circuit
equivalent to that shown in Figure 2. The bus master can be the same equivalent circuit. If a bidirectional
pin is not available, separate output and input pins can be tied together. The bus master requires a pullup
resistor at the master end of the bus, with the bus master circuit equivalent to the one shown in Figure 3.
The value of the pullup resistor should be approximately 5 kW for short line lengths. A multidrop bus
consists of a 1-Wire bus with multiple slaves attached. The 1-Wire bus has a maximum data rate of 16.3k
bits per second.
The idle state for the 1-Wire bus is high. If, for any reason, a transaction needs to be suspended, the bus
MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low
for more than 120 ms, one or more of the devices on the bus may be reset.
DS1990A
DS1990A MEMORY MAP Figure 1MSB LSB MSB LSB MSB LSB
DS1990A EQUIVALENT CIRCUIT Figure 2
BUS MASTER CIRCUIT Figure 3
DS1990A
TRANSACTION SEQUENCEThe sequence for accessing the DS1990A via the 1-Wire port is as follows:InitializationROM Function CommandRead Data
INITIALIZATIONAll transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence
consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the
slave(s).
The presence pulse lets the bus master know that the DS1990A is on the bus and is ready to operate. For
more details, see the “1-Wire Signaling” section.
ROM FUNCTION COMMANDSOnce the bus master has detected a presence, it can issue one of the four ROM function commands. All
ROM function commands are eight bits long. A list of these commands follows (refer to flowchart in
Figure 4):
Read ROM [33h] or [0Fh]This command allows the bus master to read the DS1990A’s 8-bit family code, unique 48-bit serial
number, and 8-bit CRC. This command can only be used if there is a single DS1990A on the bus. If morethan one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same
time (open drain will produce a wired-AND result). The DS1990A Read ROM function will occur with a
command byte of either 33h or 0Fh in order to ensure compatibility with the DS1990, which will only
respond to a 0Fh command word with its 64-bit ROM data.
Match ROM [55h] / Skip ROM [CCh]The complete 1-Wire protocol for all Dallas Semiconductor iButtons contains a Match ROM and a SkipROM command. (See the Book of DS19xx iButton Standards.) Since the DS1990A contains only the 64-
bit ROM with no additional data fields, the Match ROM and Skip ROM are not applicable and will cause
no further activity on the 1-Wire bus if executed. The DS1990A does not interfere with other 1-Wire parts
on a multidrop bus that do respond to a Match ROM or Skip ROM (example DS1990A and DS1994 on
the same bus).
Search ROM [F0h]When a system is initially brought up, the bus master might not know the number of devices on the 1-
Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process
of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The ROM search processis the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the
desired value of that bit. The bus master performs this simple 3-step routine on each bit of the ROM.
After one complete pass, the bus master knows the contents of the ROM in one device. The remaining
number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the
Book of DS19xx iButton Standards for a comprehensive discussion of a ROM search, including an actual
DS1990A
ROM FUNCTIONS FLOW CHART Figure 4
DS1990A
1-WIRE SIGNALINGThe DS1990A requires strict protocols to ensure data integrity. The protocol consists of four types of
signaling on one line: Reset sequence with Reset Pulse and Presence Pulse, write 0, write 1 and read data.
All these signals except presence pulse are initiated by the bus master.
The initialization sequence required to begin any communication with the DS1990A is shown in Figure 5.A Reset Pulse followed by a Presence Pulse indicates the DS1990A is ready to send or receive data given
the correct ROM command.
The bus master transmits (TX ) a reset pulse ( a low signal for a minimum of 480 ms). The bus master thenreleases the line and goes into receive mode (RX ). The 1-Wire bus is pulled to a high state via the
5 kW pullup resistor. After detecting the rising edge on the data contact, the DS1990A waits (tPDH , 15-60
ms) and then transmits the presence pulse (tPDL , 60-240 ms).
READ/WRITE TIME SLOTSThe definitions of write and read time slots are illustrated in Figure 6. All time slots are initiated by themaster driving the data line low. The falling edge of the data line synchronizes the DS1990A to the
master by triggering a delay circuit in the DS1990A. During write time slots, the delay circuit determines
when the DS1990A will sample the data line. For a read data time slot, if a “0” is to be transmitted, the
delay circuit determines how long the DS1990A will hold the data line low overriding the 1 generated by
the master. If the data bit is a “1”, the iButton will leave the read data time slot unchanged.
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 5480 ms £ tRSTL < ¥ *
480 ms £ tRSTH < ¥ (includes recovery time)
15 ms £ tPDH < 60 ms
60 ms £ tPDL < 240 msIn order not to mask interrupt signaling by other devices on the 1-Wire bus, tRSTL + tR should always
be less than 960 ms.
