DS1982-F5+ ,iButton 1Kb Add-OnlyFEATURES COMMON iButton
DS1990A-F5 ,Serial Number iButtonFEATURES GROUND§ Unique, factory-lasered and tested 64-bitTMregistration number (8-bit family code ..
DS1990A-F5+ ,iButton Serial NumberELECTRICAL CHARACTERISTICS(T = -40°C to +85°C.)APARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IO PI ..
DS1990A-F5+ ,iButton Serial NumberApplicationsa Single Digital Signal at 16.3kbpsAccess Control♦ Button Shape is Self-Aligning with C ..
DS1990A-F5+ ,iButton Serial NumberFeaturesgle data lead and a ground return. Every DS1990A isfactory lasered with a guaranteed unique ..
DS1990R-F3# ,Serial Number iButtonELECTRICAL CHARACTERISTICS(T = -40°C to +85°C.)APARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IO PI ..
DS1982-F3#-DS1982-F3+-DS1982-F5#-DS1982-F5+
iButton 1Kb Add-Only
SPECIAL FEATURES 1024 bits Electrically Programmable Read-
Only Memory (EPROM) communicates with
the economy of one signal plus ground EPROM partitioned into four 256-bit pages for
randomly accessing packetized data Each memory page can be permanently write-
protected to prevent tampering Device is an “add only” memory where
additional data can be programmed into
EPROM without disturbing existing data Architecture allows software to patch data by
superseding an old page in favor of a newly
programmed page Reduces control, address, data, power, and
programming signals to a single data pin 8-bit family code specifies DS1982
communications requirements to reader Reads over a wide voltage range of 2.8V to
6.0V from -40°C to +85°C; programs at 11.5V
to 12.0V from -40°C to +50°C
ORDERING INFORMATION DS1982-F3+ F3 MicroCan
DS1982-F5+ F5 MicroCan
+Denotes a lead(Pb)-free/RoHS-compliant product.
EXAMPLES OF ACCESSORIES DS9096P Self-Stick Adhesive Pad
DS9101 Multi-Purpose Clip
DS9093RA Mounting Lock Ring
DS9093F Snap-In Fob
DS9092 iButton Probe
F3 MicroCan
COMMON iButton FEATURES Unique, factory-lasered and tested 64-bit
registration number (8-bit family code + 48-bit
serial number + 8-bit CRC tester) assures
absolute traceability because no two parts are
alike Multidrop controller for MicroLAN Digital identification and information by
momentary contact Chip-based data carrier compactly stores
information Data can be accessed while affixed to object Economically communicates to bus master
with a single digital signal at 16.3kbps Standard 16mm diameter and 1-Wire® protocol
ensure compatibility with iButton® family Button shape is self-aligning with cup-shaped
probes Durable stainless steel case engraved with
registration number withstands harsh
environments Easily affixed with self-stick adhesive backing,
latched by its flange, or locked with a ring
pressed onto its rim Presence detector acknowledges when reader
first applies voltage
F5 MicroCan
DS1982
1Kb Add-Only iButton19-4891; Rev 8/09
iButton and 1-Wire are registered trademarks of Maxim Integrated Products, Inc.
DS1982
iButton DESCRIPTION The DS1982 1Kb Add-Only iButton is a rugged read/write data carrier that identifies and stores relevant
information about the product or person to which it is attached. This information can be accessed with
minimal hardware, for example, a single port pin of a microcontroller. The DS1982 consists of a factory-
lasered registration number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit Family
Code (09h) plus 1Kb of EPROM that is user-programmable. The power to program and read the DS1982
is derived entirely from the 1-Wire communication line. Data is transferred serially via the 1-Wire
protocol that requires only a single data lead and a ground return. The entire device can be programmed
and then write-protected if desired. Alternatively, the part may be programmed multiple times with new
data being appended to, but not overwriting, existing data with each subsequent programming of the
device. Note: Individual bits can be changed only from a logical 1 to a logical 0, never from a logical 0 to
a logical 1. A provision is also included for indicating that a certain page or pages of data are no longer
valid and have been replaced with new or updated data that is now residing at an alternate page address.
This page address redirection allows software to patch data and enhance the flexibility of the device as a
standalone database. The 48-bit serial number that is factory-lasered into each DS1982 provides a
guaranteed unique identity that allows for absolute traceability. The durable MicroCan package is highly
resistant to harsh environments such as dirt, moisture, and shock. Its compact button-shaped profile is
self-aligning with cup-shaped receptacles, allowing the DS1982 to be used easily by human operators or
automatic equipment. Accessories permit the DS1982 to be mounted on printed circuit boards, plastic key
fobs, photo-ID badges, ID bracelets, and many other objects. Applications include work-in-progress
tracking, electronic travelers, access control, storage of calibration constants, and debit tokens.
OVERVIEW The block diagram in Figure 1 shows the relationships between the major control and memory sections of
the DS1982. The DS1982 has three main data components: 1) 64-bit lasered ROM, 2) 1024-bit EPROM,
and 3) EPROM Status Bytes. The device derives its power for read operations entirely from the 1-Wire
communication line by storing energy on an internal capacitor during periods of time when the signal line
is high and continues to operate off of this “parasite” power source during the low times of the 1-Wire
line until it returns high to replenish the parasite (capacitor) supply. During programming, 1-Wire
communication occurs at normal voltage levels and then is pulsed momentarily to the programming
voltage to cause the selected EPROM bits to be programmed. The 1-Wire line must be able to provide 12
volts and 10 milliamperes to adequately program the EPROM portions of the part. Whenever
programming voltages are present on the 1-Wire line a special high voltage detect circuit within the
DS1982 generates an internal logic signal to indicate this condition. The hierarchical structure of the 1-
Wire protocol is shown in Figure 2. The bus master must first provide one of the four ROM function
commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM. These commands operate on
the 64-bit lasered ROM portion of each device and can singulate a specific device if many are present on
the 1-Wire line as well as indicate to the bus master how many and what types of devices are present. The
protocol required for these ROM function commands is described in Figure 9. After a ROM function
command is successfully executed, the memory functions that operate on the EPROM portions of the
DS1982 become accessible and the bus master may issue any one of the five memory function commands
specific to the DS1982 to read or program the various data fields. The protocol for these memory function
commands is described in Figure 6. All data is read and written least significant bit first.
DS1982
64-BIT LASERED ROM
Each DS1982 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code.
The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits (see Figure 3).
The 64-bit ROM and ROM Function Control section allow the DS1982 to operate as a 1-Wire device and
follow the 1-Wire protocol detailed in the section “1-Wire Bus System.” The memory functions required
to read and program the EPROM sections of the DS1982 are not accessible until the ROM function
protocol has been satisfied. This protocol is described in the ROM functions flow chart (Figure 9). The
1-Wire bus master must first provide one of four ROM function commands: 1) Read ROM, 2) Match
ROM, 3) Search ROM, or 4) Skip ROM. After a ROM function sequence has been successfully executed,
the bus master may then provide any one of the memory function commands specific to the DS1982
(Figure 6).
The 1-Wire CRC of the lasered ROM is generated using the polynomial X8 + X5 + X4 + 1. Additional
information about the Maxim 1-Wire Cyclic Redundancy Check is available in the Book of DS19xx
iButton Standards. The shift register acting as the CRC accumulator is initialized to 0. Then starting with
the least significant bit of the family code, 1 bit at a time is shifted in. After the 8th bit of the family code
has been entered, then the serial number is entered. After the 48th bit of the serial number has been
entered, the shift register contains the CRC value. Shifting in the 8 bits of CRC should return the shift
register to all 0s.
DS1982
DS1982 BLOCK DIAGRAM Figure 1
DS1982
HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2
64-BIT LASERED ROM Figure 3
8-Bit CRC Code 48- Bit Serial Number 8- Bit Family Code (09h)
MSB LSB MSB LSB MSB LSB
1-WIRE CRC GENERATOR Figure 4
BUS
MASTER
OTHER
DEVICES
DS 1982
COMMAND AVAILABLE DATA FIELD
LEVEL: COMMANDS: AFFECTED:
READ ROM 64-BIT ROM
MATCH ROM 64-BIT ROM
SEARCH ROM 64-BIT ROM
SKIP ROM N/A
WRITE MEMORY 1024-BIT EPROM
WRITE STATUS BYTE EPROM STATUS BYTES
READ MEMORY 1024-BIT EPROM
READ STATUS BYTE EPROM STATUS BYTES
READ DATA/GENERATE 1024-BIT EPROM
8-BIT CRC
1-WIRE ROM FUNCTION
COMMANDS (SEE FIGURE 9)
DS1982-SPECIFIC
MEMORY FUNCTION
COMMANDS
(SEE FIGURE 6)
DS1982
1024-BIT EPROM
The memory map in Figure 5 shows the 1024-bit EPROM section of the DS1982 that is configured as
four pages of 32 bytes each. The 8-bit scratchpad is an additional register that acts as a buffer when
programming the memory. Data is first written to the scratchpad and then verified by reading an 8-bit
CRC from the DS1982 that confirms proper receipt of the data. If the buffer contents are correct, a
programming voltage should be applied and the byte of data will be written into the selected address in
memory. This process ensures data integrity when programming the memory. The details for reading and
programming the 1024-bit EPROM portion of the DS1982 are given in the "Memory Function
Commands" section.
EPROM STATUS BYTES
In addition to the 1024 bits of data memory the DS1982 provides 64 bits of status memory accessible
with separate commands.
The EPROM Status Bytes can be read or programmed to indicate various conditions to the software
interrogating the DS1982. The first byte of the EPROM status memory contains the Write-Protect Page
bits that inhibit programming of the corresponding page in the 1024-bit main memory area if the
appropriate write protection bit is programmed. Once a bit has been programmed in the Write-Protect
Page byte, the entire 32-byte page that corresponds to that bit can no longer be altered but may still be
read.
The next 4 bytes of the EPROM Status Memory contain the Page Address Redirection Bytes that indicate
if one or more of the pages of data in the 1024-bit EPROM section have been invalidated and redirected
to the page address contained in the appropriate redirection byte. The hardware of the DS1982 makes no
decisions based on the contents of the Page Address Redirection Bytes. These additional bytes of status
EPROM allow for the redirection of an entire page to another page address, indicating that the data in the
original page is no longer considered relevant or valid. With EPROM technology, bits within a page can
be changed from a logical 1 to a logical 0 by programming, but cannot be changed back. Therefore, it is
not possible to simply rewrite a page if the data requires changing or updating, but with space permitting,
an entire page of data can be redirected to another page within the DS1982 by writing the one’s
complement of the new page address into the Page Address Redirection Byte that corresponds to the
original (replaced) page.
This architecture allows the user’s software to make a “data patch” to the EPROM by indicating that a
particular page or pages should be replaced with those indicated in the Page Address Redirection Bytes.
If a Page Address Redirection Byte has a FFH value, the data in the main memory that corresponds to that
page is valid. If a Page Address Redirection Byte has some other hex value, the data in the page
corresponding to that redirection byte is invalid, and the valid data can now be found at the one’s
complement of the page address indicated by the hex value stored in the associated Page Address
Redirection Byte. A value of FDH in the redirection byte for page 1, for example, would indicate that the
updated data is now in page 2. The details for reading and programming the EPROM status memory
portion of the DS1982 are given in the Memory Function Commands section.
DS1982
MEMORY FUNCTION COMMANDS
The “Memory Function Flow Chart” (Figure 6) describes the protocols necessary for accessing the
various data fields within the DS1982. The Memory Function Control section, 8-bit scratchpad, and the
Program Voltage Detect circuit combine to interpret the commands issued by the bus master and create
the correct control signals within the device. A 3-byte protocol is issued by the bus master. It is comprised
of a command byte to determine the type of operation and 2 address bytes to determine the specific
starting byte location within a data field. The command byte indicates if the device is to be read or
written. Writing data involves not only issuing the correct command sequence but also providing a 12-
volt programming voltage at the appropriate times. To execute a write sequence, a byte of data is first
loaded into the scratchpad and then programmed into the selected address. Write sequences always occur
a byte at a time. To execute a read sequence, the starting address is issued by the bus master and data is
read from the part beginning at that initial location and continuing to the end of the selected data field or
until a reset sequence is issued. All bits transferred to the DS1982 and received back by the bus master
are sent least significant bit first.
DS1982 MEMORY MAP Figure 5
PAGE 0
32 BYTES
PAGE 1
32 BYTES
PAGE 2
32 BYTES
PAGE 3
32 BYTES EPROM STATUS BYTES
ADDRESS: 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h
(MSB) (LSB)
BIT 0 WRITE PROTECT PAGE 0
BIT 1 WRITE PROTECT PAGE 1
BIT 2 WRITE PROTECT PAGE 2
BIT 3 WRITE PROTECT PAGE 3
BIT 4-7 BITMAP OF USED PAGES (RESERVED FOR TMEX)
8-BIT SCRATCHPAD
1024-BIT
EPROM
STARTING
ADDRESS
0000h
0020h
0040h
0060h
DS1982
MEMORY FUNCTION FLOW CHART Figure 6
DS1982
MEMORY FUNCTION FLOW CHART (cont’d) Figure 6
DS1982
MEMORY FUNCTION FLOW CHART (cont’d) Figure 6
DS1982
READ MEMORY [F0h]
The Read Memory command is used to read data from the 1024-bit EPROM data field. The bus master
follows the command byte with a 2-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting
byte location within the data field. An 8–bit CRC of the command byte and address bytes is computed by
the DS1982 and read back by the bus master to confirm that the correct command word and starting
address were received. If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and
the entire sequence must be repeated. If the CRC received by the bus master is correct, the bus master
issues read time slots and receives data from the DS1982 starting at the initial address and continuing
until the end of the 1024-bit data field is reached or until a Reset Pulse is issued. If reading occurs
through the end of memory space, the bus master may issue eight additional read time slots and the
DS1982 will respond with an 8-bit CRC of all data bytes read from the initial starting byte through the
last byte of memory. After the CRC is received by the bus master, any subsequent read time slots will
appear as logical 1s until a Reset Pulse is issued. Any reads ended by a Reset Pulse prior to reaching the
end of memory will not have the 8-bit CRC available.
Typically a 16-bit CRC would be stored with each page of data to ensure rapid, error-free data transfers
that eliminate having to read a page multiple times to determine if the received data is correct or not. (See
Book of DS19xx iButton Standards, Chapter 7 for the recommended file structure to be used with the
1-Wire environment.) If CRC values are imbedded within the data, a Reset Pulse may be issued at the end
of memory space during a Read Memory command.
READ STATUS [AAh]
The Read Status command is used to read data from the EPROM Status data field. The bus master
follows the command byte with a two-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a
starting byte location within the data field. An 8–bit CRC of the command byte and address bytes is
computed by the DS1982 and read back by the bus master to confirm that the correct command word and
starting address were received. If the CRC read by the bus master is incorrect, a Reset Pulse must be
issued and the entire sequence must be repeated. If the CRC received by the bus master is correct, the bus
master issues read time slots and receives data from the DS1982 starting at the supplied address and
continuing until the end of the EPROM Status data field is reached. At that point the bus master will
receive an 8-bit CRC that is the result of shifting into the CRC generator all of the data bytes from the
initial starting byte through the final factory-programmed byte that contains the 00h value.
This feature is provided since the EPROM Status information may change over time making it impossible
to program the data once and include an accompanying CRC that will always be valid. Therefore, the
Read Status command supplies an 8-bit CRC that is based on and always is consistent with the current
data stored in the EPROM Status data field.
After the 8-bit CRC is read, the bus master will receive logical 1s from the DS1982 until a Reset Pulse is
issued. The Read Status command sequence can be exited at any point by issuing a Reset Pulse.
READ DATA/GENERATE 8-BIT CRC [C3h]
The Read Data/Generate 8-bit CRC command is used to read data from the 1024-bit EPROM memory
field. The bus master follows the command byte with a two-byte address (TA1=(T7:T0), TA2=(T15:T8))
that indicates a starting byte location within the data field. An 8-bit CRC of the command byte and
address bytes is computed by the DS1982 and read back by the bus master to confirm that the correct
command word and starting address were received. If the CRC read by the bus master is incorrect, a
DS1982
initial address and continuing until the end of a 32-byte page is reached. At that point the bus master will
send eight additional read time slots and receive an 8-bit CRC that is the result of shifting into the CRC
generator all of the data bytes from the initial starting byte to the last byte of the current page. Once the
8-bit CRC has been received, data is again read from the 1024-bit EPROM data field starting at the next
page. This sequence will continue until the final page and its accompanying CRC are read by the bus
master. Thus each page of data can be considered to be 33 bytes long, the 32 bytes of user-programmed
EPROM data and an 8-bit CRC that gets generated automatically at the end of each page.
This type of read differs from the Read Memory command that simply reads each page until the end of
address space is reached. The Read Memory command only generates an 8-bit CRC at the end of memory
space that often might be ignored, since in many applications the user would store a 16-bit CRC with the
data itself in each page of the 1024-bit EPROM data field at the time the page was programmed. The
Read Data/Generate 8-bit CRC command provides an alternate read capability for applications that are
“bit-oriented” rather than “page-oriented” where the 1024-bit EPROM information may change over time
within a page boundary, making it impossible to program the page once and include an accompanying
CRC that will always be valid. Therefore, the Read Data/Generate 8-Bit CRC command concludes each
page with the DS1982 generating and supplying an 8-bit CRC that is based on and therefore is always
consistent with the current data stored in each page of the 1024-bit EPROM data field. After the 8-bit
CRC of the last page is read, the bus master will receive logical 1s from the DS1982 until a Reset Pulse is
issued. The Read Data/Generate 8-Bit CRC command sequence can be exited at any point by issuing a
Reset Pulse.
WRITE MEMORY [0Fh]
The Write Memory command is used to program the 1024–bit EPROM data field. The bus master will
follow the command byte with a two byte starting address (TA1=(T7:T0), TA2=(T15:T8)) and a byte of
data (D7:D0). An 8-bit CRC of the command byte, address bytes, and data byte is computed by the
DS1982 and read back by the bus master to confirm that the correct command word, starting address, and
data byte were received.
The highest starting address within the DS1982 is 007FH. If the bus master sends a starting address
higher than this, the nine most significant address bits are set to 0 by the internal circuitry of the chip.
This will result in a mismatch between the CRC calculated by the DS1982 and the CRC calculated by the
bus master, indicating an error condition.
If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must
be repeated. If the CRC received by the bus master is correct, a programming pulse (12 volts on the 1-
Wire bus for 480 s) is issued by the bus master. Prior to programming, the entire unprogrammed
1024-bit EPROM data field will appear as logical 1s. For each bit in the data byte provided by the bus
master that is set to a logical 0, the corresponding bit in the selected byte of the 1024–bit EPROM will be
programmed to a logical 0 after the programming pulse has been applied at that byte location.
After the 480 s programming pulse is applied and the data line returns to a 5-volt level, the bus master
issues eight read time slots to verify that the appropriate bits have been programmed. The DS1982
responds with the data from the selected EPROM address sent least significant bit first. This byte contains
the logical AND of all bytes written to this EPROM data address. If the EPROM data byte contains 1s in
bit positions where the byte issued by the master contains 0s, a Reset Pulse should be issued and the
current byte address should be programmed again. If the DS1982 EPROM data byte contains 0s in the
