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DS1977-F5 |DS1977F5MAIXMN/a1500avai32KB EEPROM iButton


DS1977-F5 ,32KB EEPROM iButtonFeaturesThe DS1977 is a 32Kbyte EEPROM in a rugged,• 32KB EEPROM memoryiButton enclosure. Access to ..
DS1977-F5# ,iButton 32KB EEPROMAPPLICATIONS and Absolute Traceability Because No Two Parts Maintenance/Inspection Data Storage are ..
DS1982-F3# ,iButton 1Kb Add-OnlyFEATURES  1024 bits Electrically Programmable Read- Unique, factory-lasered and tested 64-bit Onl ..
DS1982-F3+ ,iButton 1Kb Add-Only19-4891; Rev 8/09 DS1982 1Kb Add-Only iButton SPECIAL
DS1982-F5# ,iButton 1Kb Add-OnlyApplications include work-in-progress tracking, electronic travelers, access control, storage of ca ..
DS1982-F5+ ,iButton 1Kb Add-OnlyFEATURES COMMON iButton


DS1977-F5
32KB EEPROM iButton
General Description
The DS1977 is a 32Kbyte EEPROM in a rugged,
iButton enclosure. Access to the memory can bepassword-protected with different passwords for read-only and full access. Data is transferred serially viathe 1-Wire protocol, which requires only a single datalead and a ground return. Every DS1977 is factory-
lasered with a guaranteed unique 64-bit registrationnumber that allows for absolute trace-ability. Thedurable stainless steel iButton package is highlyresistant to environmental hazards such as dirt andshock. Accessories permit the DS1977 iButton to be
mounted on almost any object, including containers,pallets and bags.
Applications
Maintenance and Inspection of equipmentMedical Information / HealthData Shuttle for Fleet Management and Vendingapplications
Ordering Information
Features
32KB EEPROM memoryDurable, stainless-steel iButton packageBuilt-in multi-drop controller ensures
compatibility with other Dallas Semiconductor
1-Wire net products
Unique factory lasered 64-bit registration
number assures error free device selection
and absolute part identity
Supports Overdrive modeOperating range: 2.8V to 5.25V, -40 to +85°C
Pin Configuration

GND
© 1993
YYWW REGISTERED RR21
15C000FBC52BCC xx
1-Wire
15C000FBC52BF5 iButton
DS1977
32KB EEPROM iButton
ROM ID field
Like all 1-Wire devices, the DS1977 has a 64-bit lasered ROM identification field.
Figure 1. 64-BIT LASERED ROM

MSBLSB
MSBLSBMSBLSBMSB LSB
Figure 2. Command Hierarchy
Figure 3. Device Memory Map
Read Access Password, Addresses 7FC0h to 7FC7h
The Read Access Password provides access to the function Read Memory. No password applieswhen reading from or writing to the scratchpad. If passwords are enabled (EPW = AAh, seePassword Control Register), the 64-bit data pattern that the 1-Wire master has to transmit with the
command flow is compared to the passwords stored in the DS1977 iButton. If the passwordmatches, access is granted.
Read/Write Access Password, Addresses 7FC8h to 7FCFh

The Read/Write Access Password provides access to the functions Read Memory and CopyScratchpad. No password applies when reading from or writing to the scratchpad. If passwords
are enabled (EPW = AAh, see Password Control Register), the 64-bit data pattern that the 1-Wiremaster has to transmit with the command flow is compared to the passwords stored in the
DS1977 iButton. If the password matches, access is granted.
Setting up a password is done essentially in the same way as writing data to the user data
memory, only the address is different. Before changing passwords, disable passwords. Whensetting up a password, make sure that all 8 bytes of the password are defined. Otherwise the new
password may be unknown. Since they are located in the same memory page, both passwordscan be redefined at the same time. Always verify the scratchpad before sending the copyscratchpad command. Before enabling passwords, check whether the new password has been
successfully written to the EEPROM chip. See "Verify Password" command for details. After anew password is successfully copied from the scratchpad to its memory location, erase the
scratchpad by filling it with new data. Otherwise a copy of the password will remain accessiblethrough the scratchpad until the iButton is disconnected from the 1-Wire line.
Password Control Register
Version Register (DS1977)
Figure 4. ADDRESS REGISTERS

TARGET ADDRESS (TA1)
TARGET ADDRESS (TA2)
ENDING ADDRESS WITHDATA STATUS (E/S)
(READ ONLY)
Address Registers and Transfer Status

Because of the serial data transfer, the DS1977 iButton employs three address registers, calledTA1, TA2 and E/S (Figure ). Registers TA1 and TA2 must be loaded with the target address to
which the data will be written or from which data will be sent to the 1-Wire master upon a Readcommand. Register E/S acts like a byte counter and Transfer Status register. It is used to verifydata integrity with write commands. Therefore, the 1-Wire master only has read access to this
register. The lower six bits of the E/S register indicate the address of the last byte that has beenwritten to the scratchpad. This address is called Ending Offset. Bit 6 of the E/S register, called PF,
is set if the number of data bits sent by the 1-Wire master is not an integer multiple of 8 or if thedata in the scratchpad is not valid due to a loss of power. A valid write to the scratchpad will clearthe PF bit. Note that the lowest six bits of the target address also determine the address within the
scratchpad, where intermediate storage of data will begin. This address is called byte offset. If thetarget address (TA1) for a Write command is 103Ch for example, then the scratchpad will store
incoming data beginning at the byte offset 3Ch and will be full after only four bytes. Thecorresponding ending offset in this example is 3Fh. For best economy of speed and efficiency, thetarget address for writing should point to the beginning of a new page, i.e., the byte offset will be
0. Thus the full 64-byte capacity of the scratchpad is available, resulting also in the ending offsetof 3Fh. However, it is possible to write one or several contiguous bytes somewhere within a page.
The ending offset together with the Partial Flag support the 1-Wire master checking the dataintegrity after a Write command. The highest valued bit of the E/S register, called AA is valid onlyif the PF flag reads 0. If PF is 0 and AA is 1, a copy has taken place. The AA bit is cleared when
the device receives a write scratchpad command.
Writing With Verification
To write data to the DS1977 iButton, the scratchpad has to be used as intermediate storage. Firstthe 1-Wire master issues the Write Scratchpad command to specify the desired target address,
followed by the data to be written to the scratchpad. Under certain conditions (see WriteScratchpad command) the 1-Wire master will receive an inverted CRC16 of the command,
address and data at the end of the write scratchpad command sequence. Knowing this CRCvalue, the 1-Wire master can compare it to the value it has calculated itself to decide if thecommunication was successful and proceed to the Copy Scratchpad command. If the 1-Wire
master could not receive the CRC16, it has to send the Read Scratchpad command to read backthe scratchpad to verify data integrity. As preamble to the scratchpad data, the DS1977 iButton
repeats the target address TA1 and TA2 and sends the contents of the E/S register. If the PF flagis set, data did not arrive correctly in the scratchpad or there was a loss of power since data waslast written to the scratchpad. The 1-Wire master does not need to continue reading; it can start a
new trial to write data to the scratchpad. Similarly, a set AA flag together with a cleared PF flagindicates that the Write command was not recognized by the device. If everything went correctly,
both flags are cleared and the ending offset indicates the address of the last byte written to thescratchpad. Now the 1-Wire master can continue reading and verifying every data byte. After the1-Wire master has verified the data, it has to send the Copy Scratchpad command. This
command must be followed exactly by the data of the three address registers TA1, TA2 and E/S.The 1-Wire master may obtain the contents of these registers by reading the scratchpad or derive
it from the target address and the amount of data to be written. As soon as the DS1977 iButtonhas received these bytes correctly and the 1-Wire master has provided an acceptable password,the DS1977 will copy the scratchpad data to the requested location beginning at the target
address.
Memory and Control Functions

The DS1977 supports the following functions:Write Scratchpad (iButton version only)Read Scratchpad (iButton version only)Copy Scratchpad with Password (iButton version only)Read Memory with Password (iButton version only)Verify Password (iButton version only)
The following pages provide a short discussion of these functions. For the detailed flow charts
refer to Figure . The TA1, TA2, E/S logic is described in section
Address Registers andTransfer Status.
Write Scratchpad Command [0Fh]

After issuing the write scratchpad command, the 1-Wire master must first provide the 2-bytetarget address, followed by the data to be written to the scratchpad. The data will be written to the
scratchpad starting at the byte offset (T5:T0). The ending offset (E5: E0) will be the byte offset atwhich the 1-Wire master stops writing data. Only full data bytes are accepted. If the last data byte
is incomplete its content will be ignored and the partial byte flag PF will be set. When writing to apassword address, internal circuitry of the chip will force the 3 least significant address bits to 0.Only full 8-byte passwords are accepted. The ending offset will be 07 or 0F, depending on the
password(s) to be changed.
When executing the Write Scratchpad command the CRC generator inside the DS1977 iButton(see Figure ) calculates a CRC over the entire data stream, starting at the command code andending at the last data byte sent by the 1-Wire master. This CRC is generated using the CRC16
polynomial by first clearing the CRC generator and then shifting in the command code (0FH) ofthe Write Scratchpad command, the Target Addresses TA1 and TA2 as supplied by the 1-Wire
master and all the data bytes. The 1-Wire master may end the Write Scratchpad command at anytime. However, if the ending offset is 3Fh, the 1-Wire master may send 16 read time slots and willreceive the CRC generated by the DS1977 iButton.
The memory address range of the DS1977 iButton is 0000h to 7FFFh (see Figure ). There is no
user-access to the address range 7FD1h to 7FFFh. If the 1-Wire master sends a target addresshigher than this, the internal circuitry of the chip will set the most significant address bit to zero asit is shifted into the internal address register. The Read Scratchpad command will reveal the
target address as it will be used by the DS1977 iButton. The 1-Wire master will identify suchaddress modifications by comparing the target address read back to the target address
transmitted. If the 1-Wire master does not read the scratchpad, a subsequent copy scratchpadcommand will not work since the most significant bits of the target address the 1-Wire mastersends will not match the value the DS1977 iButton expects.
Read Scratchpad Command [AAh]

This command is used to verify scratchpad data and target address. After issuing the read
scratchpad command, the 1-Wire master begins reading. The first two bytes will be the targetaddress. The next byte will be the ending offset/data status byte (E/S) followed by the scratchpad
data beginning at the byte offset (T5: T0). The 1-Wire master may read data until the end of thescratchpad. If the master generates additional times slots, it will read a CRC16 of the commandcode, target address, E/S byte and scratchpad data starting at the byte offset, which is determined
by the target address.
Copy Scratchpad with Password [99h]

This command is used to copy data from the scratchpad to memory. After issuing the copyscratchpad command, the 1-Wire master must provide a 3-byte authorization pattern, which canbe obtained by reading the scratchpad for verification. This pattern must exactly match the data
contained in the three address registers (TA1, TA2, E/S, in that order). Next the master must senda valid write access password, or, if passwords are not enabled, 8 dummy bytes. Now the master
must provide power by bypassing the 1-Wire pull-up resistor with an electronic switch, generatinga "strong pull-up". If authorization pattern and password are accepted, the AA (AuthorizationAccepted) flag will be set and the copy will begin. Copy takes 10ms maximum during which the
voltage on the 1-Wire bus must not fall below 2.8V. After the copy is completed, the master turnsoff the strong pull-up and begins reading from the 1-Wire. A pattern of alternating 1’s and 0’s will
indicate that the copy command was executed successfully. If the copy command was disturbeddue to lack of power or for other reasons, the master will read a constant stream of FFh bytes untilit sends a 1-Wire reset pulse.
The data to be copied is determined by the three address registers (TA1, TA2, E/S). The
scratchpad data from the beginning offset through the ending offset will be copied to memory,starting at the target address. Anywhere from 1 to 64 bytes may be copied to memory with thiscommand. When updating a password, instead of the password written to the scratchpad a
scrambled password is written to the memory location of the respective password.
After the DS1977 has received the password, the 1-Wire master must activate the strong pull-up.
Read Memory with Password [69h]

The read memory command may be used to read the entire memory, except for the passwords.After issuing the command, the master must provide the 2-byte target address. Next the mastermust send a valid read access password, or, if passwords are not enabled, 8 dummy bytes. Now
the master must provide power by bypassing the 1-Wire pull-up resistor with an electronic switch,generating a "strong pull-up". If the password was accepted, EEPROM data beginning at the
specified target address and ending at the page boundary will be loaded into the scratchpadstarting at the beginning offset. This transfer takes 5 ms maximum during which the voltage onthe 1-Wire bus must not fall below 2.8V. After the transfer is completed, the master turns off the
strong pull-up and begins reading from the 1-Wire. When the end of the memory page (end ofscratchpad) is reached, the master will receive a CRC16 of the command, target address and
page data. If the master wants to read more data and the end of the memory is not yet reached, it
the scratchpad from where the master can read it by issuing read time slots. This loop of strongpull-up and reading 64 bytes can be repeated until the end of the memory is reached, at which
point the master will read logic 1's.
After the DS1977 has received the password, the 1-Wire master must activate the strong pull-up.
Verify Password [C3h]

This command allows the user to verify whether the process of updating a password was
successful, eliminating the risk of a weak programming of the memory cells that actually store thepassword. First disable the use of passwords. Then using Write Scratchpad, Read Scratchpad
and Copy Scratchpad, write the new password to its respective memory location. Now use VerifyPassword to double-check whether the password reads correctly from the EEPROM memory. TheVerify Password command does not reveal the password, neither in the clear nor in its scrambled
form, as it is stored in memory. Instead, the user will learn whether the password transmitted withthis command, after having passed the scrambler, matches the password read from the memory.
If the match is successful, it is safe to again enable passwords.
Read Version Command [CCh]
This command allows the 1-Wire master to read the chip revision code of the DS1977. After
issuing the command code, the master sends two 00h-bytes to access the version register. Withthe next 16 time slots the master receives two copies of the content of the version register.
Additional read-time slots will read logic 1's. Only the upper 3 bits of the version register are valid.The lower 5 bits will all read 0.
ROM Functions

The DS1977 supports the following ROM functions:
• Read ROM
• Match ROM
• Search ROM
• Skip ROM
• ResumeOverdrive Skip ROMOverdrive Match ROMThese functions are implemented in the same way as with other 1-Wire devices.
For the detailed flow charts refer to Figure .
Figure 5-1. Memory Function Flow Chart, Part 1
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