DS1977-F5# ,iButton 32KB EEPROMAPPLICATIONS and Absolute Traceability Because No Two Parts Maintenance/Inspection Data Storage are ..
DS1982-F3# ,iButton 1Kb Add-OnlyFEATURES 1024 bits Electrically Programmable Read- Unique, factory-lasered and tested 64-bit Onl ..
DS1982-F3+ ,iButton 1Kb Add-Only19-4891; Rev 8/09 DS1982 1Kb Add-Only iButton SPECIAL
DS1982-F5# ,iButton 1Kb Add-OnlyApplications include work-in-progress tracking, electronic travelers, access control, storage of ca ..
DS1982-F5+ ,iButton 1Kb Add-OnlyFEATURES COMMON iButton
DS1990A-F5 ,Serial Number iButtonFEATURES GROUND§ Unique, factory-lasered and tested 64-bitTMregistration number (8-bit family code ..
DS1977-F5#
iButton 32KB EEPROM
iButton DESCRIPTION The DS1977 is a 32KB EEPROM in a rugged,
iButton® enclosure. Access to the memory can be
password-protected with different passwords for
read-only and full access. Data is transferred serially
through the 1-Wire® protocol, which requires only a
single data lead and a ground return. Every DS1977
is factory lasered with a guaranteed unique 64-bit
registration number that allows for absolute
traceability. The durable stainless-steel iButton
package is highly resistant to environmental hazards
such as dirt, moisture, and shock. Accessories permit
the DS1977 iButton to be mounted on almost any
object, including containers, pallets, and bags.
APPLICATIONS Maintenance/Inspection Data Storage
Medical Data Carrier
Health Data Carrier
Audit Data Storage and Carrier
F5 MicroCAN GND
17.35FC37
000000FBC52B
1-Wire
All dimensions are shown in millimeters.
SPECIAL FEATURES 32KB EEPROM Organized as Pages of 64 Bytes
Each Optional Password Protection with Different 64-
Bit Passwords for Read and Full Access Communicates to Host with a Single Digital
Signal at Up to 15.3kbps at Standard Speed or
Up to 125kbps in Overdrive Mode Using 1-Wire
Protocol Operating Range: 2.8V to 5.25V, -40°C to +85°C Minimum 100k Write Cycles Endurance 15kV Built-in ESD Protection
COMMON iButton FEATURES Unique Factory-Lasered 64-Bit Registration
Number Assures Error-Free Device Selection
and Absolute Traceability Because No Two Parts
are Alike Built-In Multidrop Controller for 1-Wire Net Chip-Based Data Carrier Stores Digital
Identification and Information, Armored in a
Durable Stainless-Steel Case Data can be Accessed While Affixed to Object Button Shape is Self-Aligning with Cup-Shaped
Probes Easily Affixed with Self-Stick Adhesive Backing,
Latched by its Flange, or Locked with a Ring
Pressed onto its Rim Presence Detector Acknowledges when Reader
First Applies Voltage
ORDERING INFORMATION
PART TEMP RANGE PACKAGE DS1977-F5# -40°C to +85°C F5 iButton
#Denotes a RoHS-compliant device that may include lead(Pb) that
is exempt under the RoHS requirements.
EXAMPLES OF ACCESSORIES
PART DESCRIPTION DS9096P Self-Stick Adhesive Pad
DS9101 Multipurpose Clip
DS9093RA Mounting Lock Ring
DS9093A Snap-In Fob
DS9092 iButton Probe
iButton and 1-Wire are registered trademarks of Maxim
Integrated Products, Inc.
19-4890; Rev 11/09
DS1977
Password-Protected 32KB EEPROM iButton
DS1977
PHYSICAL SPECIFICATION Size See mechanical drawing
Weight DS1977 Ca. 3.3g
ABSOLUTE MAXIMUM RATINGS I/O Voltage to GND -0.3V, +5.5V
I/O Sink Current 20mA
Junction Temperature +150°C
Storage Temperature Range -40°C to +85°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device.
ELECTRICAL CHARACTERISTICS (VPUP = 2.8V to 5.25V, TA = -40°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I/O Pin General Data 1-Wire Pullup
Resistance RPUP (Notes 1, 2) 0.6 2.2 kΩ
Input Capacitance CIO (Note 3) 5 nF
Input Load Current IL I/O pin at VPUP 1 10 μA
High-to-Low Switching
Threshold VTL (Notes 4, 5) 0.5 3.2 V
Input Low Voltage VIL (Notes 1, 6) 0.30 V
Low-to-High Switching
Threshold VTH (Notes 4, 7) 0.7 3.4 V
Switching Hysteresis VHY (Note 8) 0.15 N/A V
Output-Low Voltage at
4mA VOL (Note 9) 0.4 V
Recovery Time tREC
Standard speed, RPUP= 2.2kΩ
(Note 1) 5
μs
Overdrive speed, RPUP= 2.2kΩ
(Note 1) 2
Overdrive speed, directly prior
to reset pulse; RPUP= 2.2kΩ
(Note 1)
Rising-Edge Hold-off
Time tREH Standard speed (Note 10) 0.5 5 μs Overdrive speed (Note 10) 0.5 2
Timeslot Duration tSLOT Standard speed (Note 1) 65 μs Overdrive speed (Note 1) 8
I/O Pin, 1-Wire Reset, Presence Detect Cycle Reset Low Time tRSTL Standard speed (Note 1) 480 640 μs Overdrive Speed (Note 1) 48 80
Presence Detect High
Time tPDH Standard speed (Note 11) 15 60 μs Overdrive speed (Note 11) 2.5 6.5
Presence Detect Fall
Time tFPD
Standard speed, VPUP > 4.5V
(Note 12) 1.5 5
μs Standard speed (Note 12) 1.5 8
Overdrive speed (Note 12) 0.15 1
Presence Detect Low
Time tPDL Standard speed 60 240 μs Overdrive speed 8 24
DS1977
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Presence Detect
Sample Time tMSP
Standard speed, VPUP > 4.5V
(Note 1) 65 75
μs Standard speed (Note 1) 68 75
Overdrive speed (Note 1) 7.5 10.5
I/O Pin, 1-Wire Write Write-0 Low Time tW0L Standard speed (Notes 1, 13) 60 120 μs Overdrive speed (Notes 1, 13) 6 16
Write-1 Low Time tW1L Standard speed (Notes 1, 13) 5 15 μs Overdrive speed (Notes 1, 13) 1 2
I/O Pin, 1-Wire Read Read Low Time tRL Standard speed (Notes 1, 14) 5 15 - δ μs Overdrive speed (Notes 1, 14) 1 2 - δ
Read Sample Time tMSR
Standard speed,
VPUP > 4.5V (Notes 1, 14) tRL + δ 20
μs Standard speed (Notes 1, 14) tRL + δ 15
Overdrive speed (Notes 1, 14) tRL + δ 2
I/O Pin, Strong Pullup Strong Pullup Read tSPUR (Note 1) 2.64 ms
Strong Pullup Write tSPUW (Note 1) 22.46 ms
Strong Pullup password
verification tSPUV (Note 1) 0.62 ms
EEPROM Programming Current ILPROG 7 mA
Write/Erase Cycles NCYCLE 100k —
Data Retention tRET 10 years
Note 1: System requirement.
Note 2: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The
specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded
systems, an active pullup such as that found in the DS2480B may be required.
Note 3: Capacitance on the data pin could be 5nF when power is first applied.
Note 4: VTL and VTH are functions of the internal supply voltage, which is a function of VPUP and the 1-Wire recovery times. The VTH and VTL
maximum specifications are valid at VPUPMAX (5.25V). In any case, VTL < VTH < VPUP.
Note 5: Voltage below which, during a falling edge on I/O, a logic '0' is detected.
Note 6: The voltage on I/O needs to be less or equal to VILMAX whenever the master drives the line low.
Note 7: Voltage above which, during a rising edge on I/O, a logic '1' is detected.
Note 8: After VTH is crossed during a rising edge on I/O, the voltage on I/O has to drop by VHY to be detected as logic '0'.
Note 9: The I-V characteristic is linear for voltages less than 1V.
Note 10: The earliest recognition of a negative edge is possible at tREH after VTH has been reached before.
Note 11: Highlighted numbers are NOT in compliance with the published iButton standards. See comparison table below.
Note 12: Interval during the negative edge on I/O at the beginning of a Presence Detect pulse between the time at which the voltage is 90%
of VPUP and the time at which the voltage is 10% of VPUP.
Note 13: ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to VTH. The actual maximum
duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε respectively.
Note 14: δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to the input-high threshold of
the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.
Parameter
Name
Standard Values DS1977 Values
Standard Speed Overdrive Speed Standard Speed Overdrive Speed
min max min max min max min max tSLOT (incl. tREC) 61μs (undef.) 7μs (undef.) 65μs1) (undef.) 8μs1) (undef.)
tRSTL 480μs (undef.) 48μs 80μs 480μs 640μs 48μs 80μs
tPDH 15μs 60μs 2μs 6μs 15μs 60μs 2.5μs 6.5μs
tPDL 60μs 240μs 8μs 24μs 60μs 240μs 8μs 24μs
tW0L 60μs 120μs 6μs 16μs 60μs 120μs 6μs 16μs
1) Intentional change, longer recovery time requirement due to modified 1-Wire front end.
DS1977
APPLICATION The DS1977 is an ideal device to store maintenance and inspection data of equipment or medical- and health-
related data in digitally readable format. Due to its small size and rugged enclosure the device can be carried with a
keyring to provide critical data in case of an emergency. The DS1977 can also serve as data shuttle to transport
fleet management and vending machine data to an access point for upload into a remote server for further
processing. Software for communication with the DS1977 is available for free download from the iButton website.
OVERVIEW The block diagram in Figure 1 shows the relationships between the major control and memory sections of the
DS1977. The device has four main data components: 1) 64-bit lasered ROM, 2) 512-bit scratchpad and buffer, 3)
32KB EEPROM, and 4) two password buffers. The passwords can only be written and verified, but never be read.
The hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first provide one of the
seven ROM function commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5) Overdrive-Skip
ROM, 6) Overdrive-Match ROM or 7) Resume. Upon completion of an Overdrive ROM command byte executed at
standard speed, the device will enter Overdrive mode, where all subsequent communication occurs at a higher
speed. The protocol required for these ROM function commands is described in Figure 9. After a ROM function
command is successfully executed, the memory and control functions become accessible and the master may
provide any one of the six available commands. The protocol for these memory and control function commands is
described in Figure 7. All data is read and written least significant bit first.
Figure 1. DS1977 BLOCK DIAGRAM 32KB
EEPROM
MEMORY
FUNCTION
CONTROL
64-BYTE
SCRATCHPAD
AND BUFFER
POWER
CONTROL
CRC16
GENERATOR
I/O ROM FUNCTION
CONTROL
64-BIT
LASERED ROM
MEMORY
ACCESS
SECURITY
CONTROL
DS1977
Figure 2. HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL 1-Wire NETOTHER
DEVICES
BUS
MASTER
DS1977AVAILABLE
COMMANDS:
COMMAND
LEVEL:
DATA FIELD
AFFECTED:
1-Wire ROM FUNCTION
COMMANDS
READ ROM
MATCH ROM
SEARCH ROM
SKIP ROM
RESUME
OVERDRIVE SKIP
OVERDRIVE MATCH
64-BIT ROM, RC-FLAG
64-BIT ROM, RC-FLAG
64-BIT ROM, RC-FLAG
RC-FLAG
RC-FLAG
RC-FLAG, OD-FLAG
64-BIT ROM, RC-FLAG, OD-FLAG
DS1977-SPECIFIC
MEMORY FUNCTION
COMMANDS
WRITE SCRATCHPAD
READ SCRATCHPAD
COPY SCRATCHPAD
W/PW
READ MEMORY W/PW
VERIFY PASSWORD
READ VERSION
64-BYTE SCRATCHPAD
64-BYTE SCRATCHPAD
DATA MEMORY, PASSWORDS,
PASSWORD ENABLE BYTE
DATA MEMORY, PASSWORDS,
PASSWORD ENABLE BYTE
PASSWORDS
VERSION REGISTER
64-BIT LASERED ROM Each DS1977 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next
48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. See Figure 3 for details. The 1-
Wire CRC is generated using a polynomial generator consisting of a Shift and XOR gates as shown in Figure 4.
The polynomial is X8 + X5 + X4 + 1. Additional information about the 1-Wire Cyclic Redundancy Check is available
in Application Note 27 and in the Book of DS19xx iButton Standards.
The Shift register bits are initialized to 0. Then starting with the least significant bit of the family code, one bit at a
time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After the th bit of the serial number has been entered, the Shift register contains the CRC value. Shifting in the 8 bits of
CRC returns the Shift register to all 0s.
Figure 3. 64-BIT LASERED ROM MSB LSB
8-BIT
CRC CODE 48-BIT SERIAL NUMBER 8-BIT FAMILY
CODE (37h)
MSB LSB MSB LSB MSB LSB
DS1977
Figure 4. 1-WIRE CRC GENERATOR 0X1X2X3X4X5X6X7X8
POLYNOMIAL = X8 + X5 + X4 + 1st
STAGEnd
STAGErd
STAGEth
STAGEth
STAGEth
STAGEth
STAGEth
STAGE
INPUT DATA
MEMORY The memory map of the DS1977 is shown in Figure 5. The 32KB of general-purpose EEPROM are located in
pages 0 through 510. The passwords and the Password Control register take 17 bytes of page 511. The remaining
bytes of page 511 are not accessible to the user. The scratchpad is an additional page that acts as a buffer when
writing to the EEPROM memory or setting up a password, and when reading from the EEPROM.
Figure 5. DS1977 MEMORY MAP 64-Byte Intermediate Storage Scratchpad ADDRESS
0000h to
003Fh
64-Byte User EEPROM Page 0
0040h to
7F7Fh
64-Byte User EEPROM Pages 1
To 509
7F80h to
7FBFh
64-Byte User EEPROM Page 510
7FC0h to
7FC7h
Read Access Password (A) 7FC8h to
7FCFh
Full Access Password (B) 7FD0h
Password Control Register 7FD1h to
7FFFh
(No Function; Will Read FFh, Cannot be Written)
SECURITY BY PASSWORD The DS1977 is designed to use two passwords that control read access and full access. No password applies
when reading from or writing to the scratchpad. Setting up a password or enabling/disabling the password checking
is done in the same way as writing data to a memory location, only the address is different. Since they are located
in the same memory page, both passwords can be redefined at the same time. Before changing passwords,
disable passwords. When setting up a password, make sure that all 8 bytes of the password are defined.
Otherwise the new password may be unknown. Always verify the scratchpad before issuing the copy scratchpad
command. After a new password is successfully copied from the scratchpad to its memory location, erase the
DS1977
Read Access Password This password only applies to the function "Read Memory with Password”. If passwords are enabled (EPW = AAh,
see Password Control register), the 64-bit data pattern that the 1-Wire master has to transmit with the command
flow is compared to the passwords stored in the DS1977 iButton. The DS1977 delivers the requested data only if
the password transmitted by the master was correct or if password checking is not enabled.
Read Access Password Register ADDR b7 b6 b5 b4 b3 b2 b1 b0
7FC0h RP7 RP6 RP5 RP4 RP3 RP2 RP1 RP0
7FC1h RP15 RP14 RP13 RP12 RP11 RP10 RP9 RP8
— — —
7FC6h RP55 RP54 RP53 RP52 RP51 RP50 RP49 RP48
7FC7h RP63 RP62 RP61 RP60 RP59 RP58 RP57 RP56
There is only write access to this register. The Read Access Password needs to be transmitted exactly in the
sequence RP0, RP1… RP62, RP63.
Full Access Password This password applies to the functions "Read Memory with Password” and "Copy Scratchpad with Password”. If
passwords are enabled (EPW = AAh, see Password Control register), the 64-bit data pattern that the 1-Wire
master has to transmit with the command flow is compared to the passwords stored in the DS1977 iButton. The
DS1977 executes the command only if the password transmitted by the master was correct or if password
checking is not enabled.
Full Access Password Register ADDR b7 b6 b5 b4 b3 b2 b1 b0
7FC8h FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP0
7FC9h FP15 FP14 FP13 FP12 FP11 FP10 FP9 FP8
— — —
7FCEh FP55 FP54 FP53 FP52 FP51 FP50 FP49 FP48
7FCFh FP63 FP62 FP61 FP60 FP59 FP58 FP57 FP56
There is only write access to this register. The Full Access Password needs to be transmitted exactly in the
sequence FP0, FP1… FP62, FP63.
Password Control Register The data pattern stored in the Password Control Register determines whether password checking is enabled. If
password checking is enabled, the password transmitted is compared to the passwords stored in the device.
Reading from or writing to the scratchpad does not require a password.
Password Control Register Bitmap ADDR b7 b6 b5 b4 b3 b2 b1 b0
7FD0h EPW
Register Details
BIT DESCRIPTION BIT(S) DEFINITION EPW: Enable Passwords b0 to b7 This byte enables or disables the password protection, which applies
to reading from and writing to the memory except for the scratchpad.
If the EPW bits form a pattern of 10101010 (AAh), the device will
execute these commands only if the correct password is transmitted.
The default pattern of EPW is different from AAh.
DS1977
passwords, check whether the new password has been successfully installed. See Verify Password command for
details. Once enabled, changing the passwords or disabling password checking requires the knowledge of the
current full-access password.
VERSION REGISTER The DS1977 includes a read-only Version register, which is not a component of the memory map. Therefore, a
special command is used to read this register. The Chip Revision number enables application software to
automatically use the appropriate software driver in case of different logical behavior.
Version Register Bitmap b7 b6 b5 b4 b3 b2 b1 b0
VER2 VER1 VER0 0 0 0 0 0
Bits 0 to 4 have no function. They always read 0.
Register Details
BIT DESCRIPTION BIT(S) DEFINITION (N/A) b0 to b4 These bits are all 0.
VER: Chip Revision
Indicator
b5 to b7 Chip revision code. The initial version of the DS1977 will have all
revision bits set to 0.
Figure 6. ADDRESS REGISTERS Target Address (TA1) T7 T6 T5 T4 T3 T2 T1 T0
Target Address (TA2) T15 T14 T13 T12 T11 T10 T9 T8
Ending Address with
Data Status (E/S)
(Read Only)
AA PF E5 E4 E3 E2 E1 E0
ADDRESS REGISTERS AND TRANSFER STATUS Because of the serial data transfer, the DS1977 employs three address registers, called TA1, TA2, and E/S (Figure
6). Registers TA1 and TA2 must be loaded with the target address to which the data will be written or from which
data will be sent to the master upon a Read command. Register E/S acts like a byte counter and Transfer Status
register. It is used to verify data integrity with write commands. Therefore, the master only has read access to this
register. The lower six bits of the E/S register indicate the address of the last byte that has been written to the
scratchpad. This address is called Ending Offset. Bit 6 of the E/S register, called PF, is set if the number of data
bits sent by the master is not an integer multiple of 8 or if the data in the scratchpad is not valid due to a loss of
power. A valid write to the scratchpad will clear the PF bit. Note that the lowest six bits of the target address also
determine the address within the scratchpad, where intermediate storage of data will begin. This address is called
byte offset. If the target address for a Write command is 103Ch for example, then the scratchpad will store
incoming data beginning at the byte offset 3Ch and will be full after only four bytes. The corresponding ending
offset in this example is 3Fh. For best economy of speed and efficiency, the target address for writing should point
to the beginning of a new page, i.e., the byte offset will be 0. Thus the full 64-byte capacity of the scratchpad is
available, resulting also in the ending offset of 3Fh. However, it is possible to write one or several contiguous bytes
somewhere within a page. The ending offset together with the Partial Flag support the master checking the data
integrity after a Write command. The highest valued bit of the E/S register, called AA is valid only if the PF flag
reads 0. If PF is 0 and AA is 1, a copy has taken place. The AA bit is cleared when the device receives a write
scratchpad command.
DS1977
WRITING WITH VERIFICATION To write data to the DS1977 , the scratchpad has to be used as intermediate storage. First the master issues the
Write Scratchpad command to specify the desired target address, followed by the data to be written to the
scratchpad. Under certain conditions (see Write Scratchpad command) the master will receive an inverted CRC16
of the command, address and data at the end of the write scratchpad command sequence. Knowing this CRC
value, the master can compare it to the value it has calculated itself to decide whether the communication was
successful and proceed to the Copy Scratchpad command. If the master could not receive the CRC16, it has to
send the Read Scratchpad command to read back the scratchpad to verify data integrity. As preamble to the
scratchpad data, the DS1977 repeats the target address TA1 and TA2 and sends the contents of the E/S register.
If the PF flag is set, data did not arrive correctly in the scratchpad or there was a loss of power since data was last
written to the scratchpad. The master does not need to continue reading; it can start a new trial to write data to the
scratchpad. Similarly, a set AA flag together with a cleared PF flag indicates that the Write command was not
recognized by the device. If everything went correctly, both flags are cleared and the ending offset indicates the
address of the last byte written to the scratchpad; the master can continue reading and verifying every data byte.
After the master has verified the data, it has to send the Copy Scratchpad command. This command must be
followed exactly by the data of the three address registers TA1, TA2, and E/S. The master may obtain the contents
of these registers by reading the scratchpad or derive it from the target address and the amount of data to be
written. As soon as the DS1977 has received these bytes correctly and the master has provided an acceptable
password, the DS1977 will copy the scratchpad data to the requested location beginning at the target address.
MEMORY FUNCTION COMMANDS The “Memory Function Flow Chart” (Figure 7) describes the protocols necessary for accessing the memory and the
special function registers of the DS1977. Examples on how to use these functions to operate the DS1977 are
included at the end of this document, preceding the Electrical Characteristics section. The communication between
master and DS1977 takes place either at standard speed (default, OD = 0) or at Overdrive Speed (OD = 1). If not
explicitly set into the Overdrive mode the DS1977 assumes regular speed.
Write Scratchpad Command [0Fh] This command is used to specify the target address and to write data to the scratchpad for verification before the
transfer to the EEPROM can be initiated. After issuing the write scratchpad command, the master must first provide
the 2-byte target address, followed by the data to be written to the scratchpad. The data will be written to the
scratchpad starting at the byte offset (T5:T0). The ending offset (E5: E0) will be the byte offset at which the master
stops writing data. Only full data bytes are accepted. If the last data byte is incomplete its content will be ignored
and the partial byte flag PF will be set. When writing to a password address, internal circuitry of the chip will force
the 3 least significant address bits to 0. Only full 8-byte passwords are accepted. The ending offset will be 07 or 0F,
depending on the password(s) to be changed.
When executing the Write Scratchpad command the CRC generator inside the DS1977 (Figure 13) calculates an
inverted CRC over the entire data stream, starting at the command code and ending at the last data byte sent by
the master. This CRC is generated using the CRC16 polynomial by first clearing the CRC generator and then
shifting in the command code (0FH) of the Write Scratchpad command, the Target Addresses TA1 and TA2 as
supplied by the master and all the data bytes. The master may end the Write Scratchpad command at any time.
However, if the ending offset is 3Fh, the master may send 16 read-time slots and will receive the CRC generated
by the DS1977 .
The memory address range of the DS1977 is 0000h to 7FFFh (Figure 5). There is no user-access to the address
range 7FD1h to 7FFFh. If the master sends a target address higher than this, the internal circuitry of the chip will
set the most significant address bit to zero as it is shifted into the internal address register. The Read Scratchpad
command will reveal the target address as it will be used by the DS1977 . The master will identify such address
modifications by comparing the target address read back to the target address transmitted. If the master does not
read the scratchpad, a subsequent copy scratchpad command will not work since the most significant bits of the
target address the master sends will not match the value the DS1977 expects.
Read Scratchpad Command [AAh]
DS1977
Regardless of the actual ending offset the master may continue reading data until the end of the scratchpad after
which it will receive an inverted CRC16 of the command code, Target Addresses TA1 and TA2, the E/S byte, and
the scratchpad data starting at the byte offset, which is determined by the target address. After the CRC is read,
the bus master will read logical 1s from the DS1977 until a reset pulse is issued.
Copy Scratchpad with Password [99h] This command is used to transfer data from the scratchpad to the memory. After issuing the copy scratchpad
command, the master must provide a 3-byte authorization pattern, which can be obtained by reading the
scratchpad for verification. This pattern must exactly match the data contained in the three address registers (TA1,
TA2, E/S, in that order). Next the master must send a valid full-access password, or, if passwords are not enabled,
8 dummy bytes. Now the master must provide power by bypassing the 1-Wire pullup resistor with an electronic
switch, generating a "strong pullup". If authorization pattern and password are accepted, the AA (Authorization
Accepted) flag will be set and the copy will begin. Copy takes 10ms maximum during which the voltage on the 1-
Wire bus must not fall below 2.8V. After the copy is completed, the master turns off the strong pullup and begins
reading from the 1-Wire. A pattern of alternating 1’s and 0’s will indicate that the copy command was executed
successfully. If the copy command was disturbed due to lack of power or for other reasons (see Figure 7-2, "strong
pullup valid"), the master will read a constant stream of FFh bytes until it sends a 1-Wire reset pulse. In this case
the destination memory may be incompletely programmed requiring a write scratchpad and copy scratchpad be
repeated to ensure proper programming of the EEPROM. This requires careful consideration when designing
application software that writes to the DS1977 in an intermittent contact environment.
The data to be copied is determined by the three address registers (TA1, TA2, E/S). The scratchpad data from the
beginning offset through the ending offset will be copied to memory, starting at the target address. Anywhere from
1 to 64 bytes may be copied to memory with this command.
Read Memory with Password [69h] This command is used to read the entire memory, except for the passwords. After issuing the command, the
master must provide the 2-byte target address. Next the master must send a valid read access password, or, if
passwords are not enabled, 8 dummy bytes. Now the master must provide power by bypassing the 1-Wire pullup
resistor with an electronic switch, generating a "strong pullup". If the password was accepted, EEPROM data
beginning at the specified target address and ending at the page boundary will be loaded into the scratchpad
starting at the beginning offset. This transfer takes 5 ms maximum during which the voltage on the 1-Wire bus must
not fall below 2.8V. After the transfer is completed, the master turns off the strong pullup and begins reading from
the 1-Wire. When the end of the memory page (end of scratchpad) is reached, the master will receive an inverted
CRC16 of the command, target address and page data. If the master wants to read more data and the end of the
memory is not yet reached, it again has to activate the strong pullup. This will transfer a full 64-byte page of
memory data to the scratchpad from where the master can read it by issuing read-time slots. This transfer only
takes place if the DS1977 receives enough power through the 1-Wire line (see Figure 7-3, "strong pullup valid").
The loop of strong pullup and reading 64 bytes can be repeated until the end of the memory is reached, at which
point the master will read logic 1's.
Verify Password [C3h] This command allows the user to verify whether the process of updating a password was successful, eliminating
the risk of a weak programming of the memory cells that actually store the password. The command allows
verifying one password at a time. After issuing the command code, the master must send the memory address of
the password to be verified. Next the master transmits the password itself and generates a strong pullup to provide
the power for the password comparison. This takes 5ms maximum, during which the voltage on the 1-Wire bus
must not fall below 2.8V. After the comparison is completed, the master turns off the strong pullup and begins
reading from the 1-Wire line. A pattern of alternating 1's and 0's indicates that the verification was successful, i. e.,
the password supplied by the master matches the one stored in the DS1977. If the passwords do not match, the
master will read a constant stream of FFh bytes until it sends a reset pulse.
Before changing a password, first disable the use of passwords. Then using Write Scratchpad, Read Scratchpad
and Copy Scratchpad, write the new password to its respective memory location. Now use Verify Password to
double-check whether the password reads correctly from the EEPROM memory. If the verification is successful, it
DS1977
Figure 7-1. MEMORY/CONTROL FUNCTION FLOW CHART Master TX Memory
Function Command
0Fh
Write
Scratchpad
Master TX
TA1 (T7:T0), TA2 (T15:T8)
DS1977 sets Scratch-
pad Offset = (T5:T0)
and Clears (PF, AA)
Master TX Data Byte
to Scratchpad Offset
DS1977 sets (E5:E0)
= Scratchpad Offset
Master
TX Reset
Scratch-
pad Offset =
3Fh
Master RX CRC16 of
Command, Address Data
DS1977 Incre-
ments Scratch-
pad Offset
Master RX "1"s
Master
TX Reset
Master
TX Reset
Partial
Byte Written
PF = 1
AAh
Read
Scratchpad
Master RX
TA1 (T7:T0)
Master RX
TA2 (T15:T8)
Master RX Ending
Offset with Data
Status (E/S)
Master
TX Reset
Scratch-
pad Offset =
3Fh
Master RX CRC16 of
Command, Address Data,
E/S Byte, and Data Starting
at the Target Address
DS1977 Incre-
ments Scratch-
pad Offset
Master RX "1"s
Master
TX Reset
DS1977 sets Scratch-
pad Offset = (T5:T0)
Master RX Data Byte
from Scratchpad Offset
From ROM Functions
Flow Chart (Figure 9)
Address of
Password
DS1977 sets Scratchpad
Offset = (T5:T3,0,0,0) and
Clears (PF, AA, T2:T0)
Master TX one or both
8-byte passwords
To Figure 7nd Part
From Figure 7nd
DS1977
Figure 7-2. MEMORY/CONTROL FUNCTION FLOW CHART 99h
Copy Scrpad.
[w/PW]
Master TX
E/S Byte
Authorization
Code Match
DS1977 Copies Scratchpad
Data or Data from Password
Holding Register (if Password
Address) to Memory
Strong Pull-
up Valid
Master
TX Reset
AA = 1
Master TX
TA1 (T7:T0), TA2 (T15:T8)
Master TX
64-Bits [Password]
Password
Accepted
DS1977 TX "0"
DS1977 TX "1"
Master
TX Reset
Master
TX Reset
Master RX "1"s
Authorization
Code
Master Activates
Strong Pullup
Address of
Password
Read-
Access
Passw.
Save to Read
Password Holding
RegisterN
Save to Full-
Access Password
Holding Register
More data
in SP
To Figure 7rd Part
From Figure 7
From Figure 7st Part
To Figure 7
NOTE: The strong pullupmust be activated within
40μs after the last bit of the
password is transmitted.
Pullup duration: see tSPUW
DS1977
Figure 7-3. MEMORY/CONTROL FUNCTION FLOW CHART 69h
Read Mem.
[w/PW]
Master TX
64-Bits [Password]
Master
TX Reset
CRC OK
Master RX "1"s
DS1977 sets Memory
Address = (T15:T0)
Master RX Data Byte
from Memory Address or
FFh if Password Address
Master TX
TA1 (T7:T0), TA2 (T15:T8)
Password
Accepted
DS1977 Incre-
ments Address
Counter
End of Page
Master RX CRC16 of
Command, Address, Datast Pass); CRC16 of Data
(Subsequent Passes)
End of
Memory
Master TX
Reset
Decision made
by DS1977
Decision made
by Master
Master Activates
Strong Pullup
DS1977 Incre-
ments Address
Counter
Master Activates
Strong Pullup
Strong pull-
up validN
Master
TX Reset
To Figure 7th Part
From Figure 7th
From Figure 7nd Part
To Figure 7nd
NOTE: The strong pullupmust be activated within
40μs after the last bit of the
password is transmitted.
Pullup duration: see tSPUR
To continue reading the next
memory page, the strong
pullup must be activated
within 40μs after the last bit
of the CRC16 is read.
See
Note
DS1977
Figure 7-4. MEMORY/CONTROL FUNCTION FLOW CHART Master TX
TA1 (T7:T0), TA2 (T15:T8)
C3h
Verify
Password
Master TX
Password to verify
DS1977 sets Memory
Address = (T15:T3, 0, 0, 0)
Password
Match
Master Activates
Strong Pullup
Master
TX Reset
Address of
Password
Master RX
AAh byte
Master RX
FFh byte
Master
TX Reset
From Figure 7rd Part
To Figure 7
CCh
Read
Version
Master TX
two bytes 00h
Master RX two copies
of Version Register
NOTE: The strong pullupmust be activated within
40μs after the last bit of the
password is transmitted.
Pullup duration: see tSPUV
DS1977
Read Version Command [CCh]
This command allows the master to read the chip revision code of the DS1977. After issuing the command code,
the master sends two 00h-bytes to access the version register. With the next 16 time slots the master receives two
copies of the content of the version register. Additional read-time slots will read logic 1's. Only the upper 3 bits of
the version register are valid. The lower 5 bits will all read 0.
1-Wire BUS SYSTEM The 1-Wire bus is a system, which has a single bus master and one or more slaves. In all instances the DS1977 is
a slave device. The bus master is typically a microcontroller or PC. For small configurations the 1-Wire
communication signals can be generated under software control using a single port pin. A second port pin is
required to control the strong pullup to supply power for the commands Copy Scratchpad with Password, Read
Memory with Password and Verify Password. Alternatively, the DS2480B 1-Wire line driver chip or serial port
adapters based on this chip (DS9097U series) are can be used. This simplifies the hardware design and frees the
microprocessor from responding in real-time.
The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence,
and 1-Wire signaling (signal types and timing). The 1-Wire protocol defines bus transactions in terms of the bus
state during specific time slots that are initiated on the falling edge of sync pulses from the bus master. For a more
detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton Standards.
HARDWARE CONFIGURATION The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at
the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open drain or tri-state
outputs. The 1-Wire port of the DS1977 is open-drain with an internal circuit equivalent to that shown in Figure 8.
A multi-drop bus consists of a 1-Wire bus with multiple slaves attached. At standard speed the 1-Wire bus has a
maximum data rate of 15.3 kbits per second. The speed can be boosted to 125 kbits per second by activating the
Overdrive mode. The value of the pullup resistor primarily depends on the network size and load conditions. For
most applications the optimal value of the pullup resistor will be approximately 2.2kΩ for standard speed and 1.5kΩ
for Overdrive speed.
The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be
left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 16μs
(Overdrive speed) or more than 120μs (standard speed), one or more devices on the bus may be reset.
TRANSACTION SEQUENCE The protocol for accessing the DS1977 through the 1-Wire port is as follows: Initialization ROM Function Command Memory Function Command Transaction/Data
Illustrations of the transaction sequence for the various memory function commands are found later in this
document.
INITIALIZATION All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a
reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence
pulse lets the bus master know that the DS1977 is on the bus and is ready to operate. For more details, see the 1-
Wire Signaling section.
1-Wire ROM FUNCTION COMMANDS
