DS18S20-PAR Fast Delivery |IC PHOENIX CO.,LIMITED

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DS1921 ,High-Resolution Thermochron iButtonblock diagram in Figure 1 shows the relationships between the major control and memory sections of ..
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DS1921G ,Thermochron iButtonElectrical Characteristics(V = +2.8V to +5.25V, T = -40°C to +85°C.)PUP APARAMETER SYMBOL CONDITION ..
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DS18S20-PAR
Parasite-Power Digital Thermometer
FEATURESUnique 1-Wire® interface requires only one
port pin for communicationDerives power from data line (“parasite
power”)—does not need a local power supplyMulti-drop capability simplifies distributed
temperature sensing applicationsRequires no external components0.5C accuracy from –10°C to +85°CMeasures temperatures from –55°C to
+100°C (–67°F to +212°F)9-bit thermometer resolutionConverts temperature in 750 ms (max.)User–definable non-volatile temperature
alarm settingsAlarm search command identifies and
addresses devices whose temperature is
outside of programmed limits (temperature
alarm condition)Ideal for use in remote sensing applications
(e.g., temperature probes) that do not have a
local power source
PIN ASSIGNMENT
PIN DESCRIPTION
GND- Ground- Data In/Out- No Connect
DESCRIPTION
The DS18S20-PAR digital thermometer provides 9–bit centigrade temperature measurements and has an
alarm function with nonvolatile user-programmable upper and lower trigger points. The DS18S20-PAR
does not need an external power supply because it derives power directly from the data line (“parasite
power”). The DS18S20-PAR communicates over a 1-Wire bus, which by definition requires only one
data line (and ground) for communication with a central microprocessor. It has an operating temperature
range of –55°C to +100°C and is accurate to 0.5C over a range of –10°C to +85°C.
Each DS18S20-PAR has a unique 64-bit identification code, which allows multiple DS18S20-PARs to
function on the same 1–wire bus; thus, it is simple to use one microprocessor to control many
DS18S20-PARs distributed over a large area. Applications that can benefit from this feature include
HVAC environmental controls, temperature monitoring systems inside buildings, equipment or
DS18S20-PAR
1-Wire Parasite-Power
Digital Thermometer

TO-92
(DS18S20-PAR)
(BOTTOM VIEW)
DALLAS
18S20P
GNDNC
DS18S20-PAR
DETAILED PIN DESCRIPTIONS Table 1
PINSYMBOLDESCRIPTIONGNDGround.
2DQData Input/Output pin. Open-drain 1-Wire interface pin. Also provides power
to the device when used in parasite power mode (see “Parasite Power” section.)
3NCNo Connect. Doesn’t connect to internal circuit.
OVERVIEW
The DS18S20-PAR uses Dallas’ exclusive 1-Wire bus protocol that implements bus communication
using one control signal. The control line requires a weak pullup resistor since all devices are linked to
the bus via a 3-state or open-drain port (the DQ pin in the case of the DS18S20-PAR). In this bus system,
the microprocessor (the master device) identifies and addresses devices on the bus using each device’s
unique 64-bit code. Because each device has a unique code, the number of devices that can be addressed
on one bus is virtually unlimited. The 1-Wire bus protocol, including detailed explanations of the
commands and “time slots,” is covered in the 1-WIRE BUS SYSTEM section of this datasheet.
An important feature of the DS18S20-PAR is its ability to operate without an external power supply.
Power is instead supplied through the 1-Wire pullup resistor via the DQ pin when the bus is high. The
high bus signal also charges an internal capacitor (CPP), which then supplies power to the device when the
bus is low. This method of deriving power from the 1-Wire bus is referred to as “parasite power.”
Figure 1 shows a block diagram of the DS18S20-PAR, and pin descriptions are given in Table 1. The
64-bit ROM stores the device’s unique serial code. The scratchpad memory contains the 2-byte
temperature register that stores the digital output from the temperature sensor. In addition, the scratchpad
provides access to the 1-byte upper and lower alarm trigger registers (TH and TL). The TH and TL
registers are nonvolatile (EEPROM), so they will retain their data when the device is powered down.
DS18S20-PAR BLOCK DIAGRAM Figure 1
CPP
VPU
4.7K
64-BIT ROM
AND
1-wire PORT
INTERNAL VDD
PARASITE POWER
CIRCUITMEMORY CONTROL
LOGIC
SCRATCHPAD
8-BIT CRC GENERATOR
TEMPERATURE SENSOR
ALARM HIGH TRIGGER (TH)
REGISTER (EEPROM)
ALARM LOW TRIGGER (TL)
REGISTER (EEPROM)GND
DS18S20-PAR
DS18S20-PAR
PARASITE POWER
The DS18S20-PAR’s parasite power circuit allows the DS18S20-PAR to operate without a local external
power supply. This ability is especially useful for applications that require remote temperature sensing or
that are very space constrained. Figure 1 shows the DS18S20-PAR’s parasite-power control circuitry,
which “steals” power from the 1-Wire bus via the DQ pin when the bus is high. The stolen charge
powers the DS18S20-PAR while the bus is high, and some of the charge is stored on the parasite power
capacitor (CPP) to provide power when the bus is low.
The 1-Wire bus and CPP can provide sufficient parasite power to the DS18S20-PAR for most operations
as long as the specified timing and voltage requirements are met (refer to the DC ELECTRICAL
CHARACTERISTICS and the AC ELECTRICAL CHARACTERISTICS sections of this data sheet).
However, when the DS18S20-PAR is performing temperature conversions or copying data from the
scratchpad memory to EEPROM, the operating current can be as high as 1.5 mA. This current can cause
an unacceptable voltage drop across the weak 1-Wire pullup resistor and is more current than can be
supplied by CPP. To assure that the DS18S20-PAR has sufficient supply current, it is necessary to
provide a strong pullup on the 1-Wire bus whenever temperature conversions are taking place or data is
being copied from the scratchpad to EEPROM. This can be accomplished by using a MOSFET to pull
the bus directly to the rail as shown in Figure 2. The 1-Wire bus must be switched to the strong pullup
within 10 s (max) after a Convert T [44h] or Copy Scratchpad [48h] command is issued, and the bus
must be held high by the pullup for the duration of the conversion (tconv) or data transfer (twr = 10 ms).
No other activity can take place on the 1-Wire bus while the pullup is enabled.
SUPPLYING THE DS18S20-PAR DURING TEMPERATURE CONVERSIONS
Figure 2
OPERATION – MEASURING TEMPERATURE
The core functionality of the DS18S20-PAR is its direct-to-digital temperature sensor. The temperature
sensor output has 9-bit resolution, which corresponds to 0.5C steps. The DS18S20-PAR powers-up in a
low-power idle state; to initiate a temperature measurement and A-to-D conversion, the master must issue
a Convert T [44h] command. Following the conversion, the resulting thermal data is stored in the 2-byte
temperature register in the scratchpad memory and the DS18S20-PAR returns to its idle state. The
DS18S20-PAR output data is calibrated in degrees centigrade; for Fahrenheit applications, a lookup table
or conversion routine must be used. The temperature data is stored as a 16-bit sign-extended two’s
complement number in the temperature register (see Figure 3). The sign bits (S) indicate if the
temperature is positive or negative: for positive numbers S = 0 and for negative numbers S = 1. Table 2
gives examples of digital output data and the corresponding temperature reading.
Resolutions greater than 9 bits can be calculated using the data from the temperature, COUNT REMAIN
VPU
VPU
4.7K
1-Wire Bus
Micro-
processor
DS18S20-PAR
GNDDQ
To Other
1-Wire Devices
DS18S20-PAR
16 (10h). After reading the scratchpad, the TEMP_READ value is obtained by truncating the 0.5C bit
(bit 0) from the temperature data (see Figure 3). The extended resolution temperature can then be
calculated using the following equation:PERCOUNT
REMAINCOUNTCPERCOUNTREADTEMPETEMPERATUR____25.0_
TEMPERATURE REGISTER FORMAT Figure 3
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0
LS Byte262524232221202-1
bit 15bit 14bit 13bit 12bit 11bit 10bit 9bit 8
MS ByteSSSSSSSS
TEMPERATURE/DATA RELATIONSHIP Table 2
TEMPERATUREDIGITAL OUTPUT
(Binary)
DIGITAL OUTPUT
(Hex)
+85.0°C*0000 0000 1010 101000AAh
+25.0°C0000 0000 0011 00100032h
+0.5°C0000 0000 0000 00010001h
0°C0000 0000 0000 00000000h
-0.5°C1111 1111 1111 1111FFFFh
-25.0°C1111 1111 1100 1110FFCEh
-55.0°C1111 1111 1001 0010FF92h
*The power-on reset value of the temperature register is +85°C
OPERATION – ALARM SIGNALING
After the DS18S20-PAR performs a temperature conversion, the temperature value is compared to the
user-defined two’s complement alarm trigger values stored in the 1-byte TH and TL registers (see Figure
4). The sign bit (S) indicates if the value is positive or negative: for positive numbers S = 0 and for
negative numbers S = 1. The TH and TL registers are nonvolatile (EEPROM) so they will retain data
when the device is powered down. TH and TL can be accessed through bytes 2 and 3 of the scratchpad as
explained in the MEMORY section of this datasheet.
TH AND TL REGISTER FORMAT Figure 4
bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 06252525222120
Only bits 8 through 1 of the temperature register are used in the TH and TL comparison since TH and TL
are 8-bit registers. If the result of a temperature measurement is higher than TH or lower than TL, an
alarm condition exists and an alarm flag is set inside the DS18S20-PAR. This flag is updated after every
temperature measurement; therefore, if the alarm condition goes away, the flag will be turned off after the
next temperature conversion.
The master device can check the alarm flag status of all DS DS18S20-PARs on the bus by issuing an
DS18S20-PAR
so the master can determine exactly which DS18S20-PARs have experienced an alarm condition. If an
alarm condition exists and the TH or TL settings have changed, another temperature conversion should be
done to validate the alarm condition.
64-BIT LASERED ROM CODE
Each DS18S20-PAR contains a unique 64–bit code (see Figure 5) stored in ROM. The least significant 8
bits of the ROM code contain the DS18S20-PAR’s 1–wire family code: 10h. The next 48 bits contain a
unique serial number. The most significant 8 bits contain a cyclic redundancy check (CRC) byte that is
calculated from the first 56 bits of the ROM code. A detailed explanation of the CRC bits is provided in
the CRC GENERATION section. The 64–bit ROM code and associated ROM function control logic
allow the DS18S20-PAR to operate as a 1–wire device using the protocol detailed in the 1-WIRE BUS
SYSTEM section of this datasheet.
64-BIT LASERED ROM CODE Figure 5
8-BIT CRC48-BIT SERIAL NUMBER8-BIT FAMILY CODE (10h)
MEMORY
The DS18S20-PAR’s memory is organized as shown in Figure 6. The memory consists of an SRAM
scratchpad with nonvolatile EEPROM storage for the high and low alarm trigger registers (TH and TL).
Note that if the DS18S20-PAR alarm function is not used, the TH and TL registers can serve as general-
purpose memory. All memory commands are described in detail in the DS18S20-PAR FUNCTION
COMMANDS section.
Byte 0 and byte 1 of the scratchpad contain the LSB and the MSB of the temperature register,
respectively. These bytes are read-only. Bytes 2 and 3 provide access to TH and TL registers. Bytes 4
and 5 are reserved for internal use by the device and cannot be overwritten; these bytes will return all 1s
when read. Bytes 6 and 7 contain the COUNT REMAIN and COUNT PER ºC registers, which can be
used to calculate extended resolution results as explained in the OPERATION – MEASURING
TEMPERATURE section. Byte 8 of the scratchpad is read-only and contains the cyclic redundancy
check (CRC) code for bytes 0 through 7 of the scratchpad. The DS18S20-PAR generates this CRC using
the method described in the CRC GENERATION section.
Data is written to bytes 2 and 3 of the scratchpad using the Write Scratchpad [4Eh] command; the data
must be transmitted to the DS18S20-PAR starting with the least significant bit of byte 2. To verify data
integrity, the scratchpad can be read (using the Read Scratchpad [BEh] command) after the data is
written. When reading the scratchpad, data is transferred over the 1-Wire bus starting with the least
significant bit of byte 0. To transfer the TH and TL data from the scratchpad to EEPROM, the master
must issue the Copy Scratchpad [48h] command.
Data in the EEPROM registers is retained when the device is powered down; at power-up the EEPROM
data is reloaded into the corresponding scratchpad locations. Data can also be reloaded from EEPROM
to the scratchpad at any time using the Recall E2 [B8h] command. The master can issue “read time slots”
(see the 1-WIRE BUS SYSTEM section) following the Recall E2 command and the DS18S20-PAR will
indicate the status of the recall by transmitting 0 while the recall is in progress and 1 when the recall is
done.
MSBMSBLSBLSBLSBMSB
DS18S20-PAR
DS18S20-PAR MEMORY MAP Figure 6
SCRATCHPAD (Power-up State)
byte 0Temperature LSB (AAh)
byte 1Temperature MSB (00h)EEPROM
byte 2TH Register or User Byte 1*TH Register or User Byte 1
byte 3TL Register or User Byte 2*TL Register or User Byte 2
byte 4Reserved (FFh)
byte 5Reserved (FFh)
byte 6COUNT REMAIN (0Ch)
byte 7COUNT PER °C (10h)
byte 8CRC*
*Power-up state depends on value(s) stored
in EEPROM
CRC GENERATION
CRC bytes are provided as part of the DS18S20-PAR’s 64-bit ROM code and in the 9th byte of the
scratchpad memory. The ROM code CRC is calculated from the first 56 bits of the ROM code and is
contained in the most significant byte of the ROM. The scratchpad CRC is calculated from the data
stored in the scratchpad, and therefore it changes when the data in the scratchpad changes. The CRCs
provide the bus master with a method of data validation when data is read from the DS18S20-PAR. To
verify that data has been read correctly, the bus master must re-calculate the CRC from the received data
and then compare this value to either the ROM code CRC (for ROM reads) or to the scratchpad CRC (for
scratchpad reads). If the calculated CRC matches the read CRC, the data has been received error free. The
comparison of CRC values and the decision to continue with an operation are determined entirely by the
bus master. There is no circuitry inside the DS18S20-PAR that prevents a command sequence from
proceeding if the DS18S20-PAR CRC (ROM or scratchpad) does not match the value generated by the
bus master.
The equivalent polynomial function of the CRC (ROM or scratchpad) is: CRC = X8 + X5 + X4 + 1
The bus master can re-calculate the CRC and compare it to the CRC values from the DS18S20-PAR
using the polynomial generator shown in Figure 7. This circuit consists of a shift register and XOR gates,
and the shift register bits are initialized to 0. Starting with the least significant bit of the ROM code or the
least significant bit of byte 0 in the scratchpad, one bit at a time should shifted into the shift register.
After shifting in the 56th bit from the ROM or the most significant bit of byte 7 from the scratchpad, the
polynomial generator will contain the re-calculated CRC. Next, the 8-bit ROM code or scratchpad CRC
from the DS18S20-PAR must be shifted into the circuit. At this point, if the re-calculated CRC was
correct, the shift register will contain all 0s. Additional information about the Dallas 1-Wire cyclic
redundancy check is available in Application Note 27 entitled “Understanding and Using Cyclic
Redundancy Checks with Dallas Semiconductor Touch Memory Products.”
CRC GENERATOR Figure 7
XORXORXOR
INPUT
(85°C)
DS18S20-PAR
1-WIRE BUS SYSTEM
The 1-Wire bus system uses a single bus master to control one or more slave devices. The DS18S20-
PAR is always a slave. When there is only one slave on the bus, the system is referred to as a “single-
drop” system; the system is “multi-drop” if there are multiple slaves on the bus. All data and commands
are transmitted least significant bit first over the 1-Wire bus.
The following discussion of the 1-Wire bus system is broken down into three topics: hardware
configuration, transaction sequence, and 1-Wire signaling (signal types and timing).
HARDWARE CONFIGURATION
The 1-Wire bus has by definition only a single data line. Each device (master or slave) interfaces to the
data line via an open drain or 3–state port. This allows each device to “release” the data line when the
device is not transmitting data so the bus is available for use by another device. The 1-Wire port of the
DS18S20-PAR (the DQ pin) is open drain with an internal circuit equivalent to that shown in Figure 8.
The 1-Wire bus requires an external pullup resistor of approximately 5 k; thus, the idle state for the 1-
Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle
state if the transaction is to resume. Infinite recovery time can occur between bits so long as the 1-Wire
bus is in the inactive (high) state during the recovery period. If the bus is held low for more than 480 s,
all components on the bus will be reset. In addition, to assure that the DS18S20-PAR has sufficient
supply current during temperature conversions, it is necessary to provide a strong pullup (such as a
MOSFET) on the 1-Wire bus whenever temperature conversions or EEPROM writes are taking place (as
described in the PARASITE POWER section).
HARDWARE CONFIGURATION Figure 8
TRANSACTION SEQUENCE
The transaction sequence for accessing the DS18S20-PAR is as follows:
Step 1.Initialization
Step 2.ROM Command (followed by any required data exchange)
5 µA
Typ.
DS18S20-PAR 1-WIRE PORT
100
MOSFET
Pin
VPU
4.7K
RX = RECEIVE
TX = TRANSMIT
1-wire bus
VPU
Micro-
processorStrong
Pullup
DS18S20-PAR
It is very important to follow the transaction sequence every time the DS18S20-PAR is accessed, as the
DS18S20-PAR will not respond if any steps in the sequence are missing or out of order. Exceptions to
this rule are the Search ROM [F0h] and Alarm Search [ECh] commands. After issuing either of these
ROM commands, the master must return to Step 1 in the sequence.
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence
consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the
slave(s). The presence pulse lets the bus master know that slave devices (such as the DS18S20-PAR) are
on the bus and are ready to operate. Timing for the reset and presence pulses is detailed in the
1-WIRE SIGNALING section.
ROM COMMANDS
After the bus master has detected a presence pulse, it can issue a ROM command. These commands
operate on the unique 64–bit ROM codes of each slave device and allow the master to single out a
specific device if many are present on the 1-Wire bus. These commands also allow the master to
determine how many and what types of devices are present on the bus or if any device has experienced an
alarm condition. There are five ROM commands, and each command is 8 bits long. The master device
must issue an appropriate ROM command before issuing a DS18S20-PAR function command. A
flowchart for operation of the ROM commands is shown in Figure 9.
SEARCH ROM [F0h]
When a system is initially powered up, the master must identify the ROM codes of all slave devices on
the bus, which allows the master to determine the number of slaves and their device types. The master
learns the ROM codes through a process of elimination that requires the master to perform a Search ROM
cycle (i.e., Search ROM command followed by data exchange) as many times as necessary to identify all
of the slave devices. If there is only one slave on the bus, the simpler Read ROM command (see below)
can be used in place of the Search ROM process. For a detailed explanation of the Search ROM
procedure, refer to the iButton® Book of Standards at www.ibutton.com/ibuttons/standard.pdf. After
every Search ROM cycle, the bus master must return to Step 1 (Initialization) in the transaction sequence.
READ ROM [33h]
This command can only be used when there is one slave on the bus. It allows the bus master to read the
slave’s 64-bit ROM code without using the Search ROM procedure. If this command is used when there
is more than one slave present on the bus, a data collision will occur when all the slaves attempt to
respond at the same time.
MATCH ROM [55h]
The match ROM command followed by a 64–bit ROM code sequence allows the bus master to address a
specific slave device on a multi-drop or single-drop bus. Only the slave that exactly matches the 64–bit
ROM code sequence will respond to the function command issued by the master; all other slaves on the
bus will wait for a reset pulse.
SKIP ROM [CCh]
The master can use this command to address all devices on the bus simultaneously without sending out
any ROM code information. For example, the master can make all DS18S20-PARs on the bus perform
simultaneous temperature conversions by issuing a Skip ROM command followed by a Convert T [44h]
command. Note, however, that the Skip ROM command can only be followed by the Read Scratchpad
[BEh] command when there is one slave on the bus. This sequence saves time by allowing the master to
DS18S20-PAR
read from the device without sending its 64–bit ROM code. This sequence will cause a data collision on
the bus if there is more than one slave since multiple devices will attempt to transmit data simultaneously.
ALARM SEARCH [ECh]
The operation of this command is identical to the operation of the Search ROM command except that
only slaves with a set alarm flag will respond. This command allows the master device to determine if
any DS18S20-PARs experienced an alarm condition during the most recent temperature conversion.
After every Alarm Search cycle (i.e., Alarm Search command followed by data exchange), the bus master
must return to Step 1 (Initialization) in the transaction sequence. Refer to the OPERATION – ALARM
SIGNALING section for an explanation of alarm flag operation.
DS18S20-PAR FUNCTION COMMANDS
After the bus master has used a ROM command to address the DS18S20-PAR with which it wishes to
communicate, the master can issue one of the DS18S20-PAR function commands. These commands
allow the master to write to and read from the DS18S20-PAR’s scratchpad memory, initiate temperature
conversions and determine the power supply mode. The DS18S20-PAR function commands, which are
described below, are summarized in Table 4 and illustrated by the flowchart in Figure 10.
CONVERT T [44h]
This command initiates a single temperature conversion. Following the conversion, the resulting thermal
data is stored in the temperature register, COUNT REMAIN register and COUNT PER °C register in the
scratchpad memory, and the DS18S20-PAR returns to its low-power idle state. Within 10 s (max) after
this command is issued the master must enable a strong pullup on the 1-Wire bus for the duration of the
conversion (tconv) as described in the PARASITE POWER section.
WRITE SCRATCHPAD [4Eh]
This command allows the master to write 2 bytes of data to the DS18S20-PAR’s scratchpad. The first
byte is written into the TH register (byte 2 of the scratchpad), and the second byte is written into the TL
register (byte 3 of the scratchpad). Data must be transmitted least significant bit first. Both bytes MUST
be written before the master issues a reset, or the data may be corrupted.
READ SCRATCHPAD [BEh]
This command allows the master to read the contents of the scratchpad. The data transfer starts with the
least significant bit of byte 0 and continues through the scratchpad until the 9th byte (byte 8 – CRC) is
read. If only part of the scratchpad contents is required, the master may issue a reset to terminate reading
at any time.
COPY SCRATCHPAD [48h]
This command copies the contents of the scratchpad TH and TL registers (bytes 2 and 3) to EEPROM.
Within 10 s (max) after this command is issued the master must enable a strong pullup on the 1-Wire
bus for at least 10 ms as described in the PARASITE POWER section.
RECALL E2 [B8h]
This command recalls the alarm trigger values (TH and TL) from EEPROM and places the data in bytes 2
and 3, respectively, in the scratchpad memory. The master device can issue “read time slots” (see the 1-
WIRE BUS SYSTEM section) following the Recall E2 command and the DS18S20-PAR will indicate the
status of the recall by transmitting 0 while the recall is in progress and 1 when the recall is done. The
recall operation happens automatically at power-up, so valid data is available in the scratchpad as soon as
power is applied to the device.
DS18S20-PAR
DS18S20-PAR FUNCTION COMMAND SET Table 4
CommandDescriptionProtocol
1-Wire Bus Activity
After Command is IssuedNotes
TEMPERATURE CONVERSION COMMANDS
Convert TInitiates temperature
conversion.
44hNone1
MEMORY COMMANDS
Read ScratchpadReads the entire scratchpad
including the CRC byte.
BEhDS18S20-PAR transmits up
to 9 data bytes to master.
Write ScratchpadWrites data into scratchpad
bytes 2 and 3 (TH and TL).
4EhMaster transmits 2 data
bytes to DS18S20-PAR.
Copy ScratchpadCopies TH and TL data from the
scratchpad to EEPROM.
48hNone1
Recall E2Recalls TH and TL data from
EEPROM to the scratchpad.
B8hDS18S20-PAR transmits
recall status to master.
NOTES:
1. The master must enable a strong pullup on the 1-Wire bus during temperature conversions and copies
from the scratchpad to EEPROM. No other bus activity may take place during this time.
2. The master can interrupt the transmission of data at any time by issuing a reset.
3. Both bytes must be written before a reset is issued.

Partno	Mfg	Dc	Qty	Available	Descript
DS18S20-PAR \|DS18S20PAR	MAIXM	N/a	1500	avai	Parasite-Power Digital Thermometer