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DS1876
SFP Controller with Dual LDD Interface
SFP Controller with Dual LDD Interface
DS1876
General Description
The DS1876 controls and monitors all functions for
dual transmitter modules. The memory map is based
on SFF-8472. The DS1876 supports APC and modula-
tion control and eye safety functionality for two laser
drivers. It continually monitors for high output current,
high bias current, and low and high transmit power to
ensure that laser shutdown for eye safety requirements
are met without adding external components. Six ADC
channels monitor VCC, temperature, and four external
monitor inputs that can be used to meet all monitoring
requirements.
Applications
Dual Tx Video SFP Modules
Ordering Information
FeaturesMeets All SFF-8472 Transmitter Control and
Monitoring RequirementsSix Analog Monitor Channels: Temperature, VCC,
PMON1, BMON1, PMON2, BMON2 PMON_ and BMON_ Support Internal and External Calibration Scalable Dynamic Range Internal Direct-to-Digital Temperature Sensor Alarm and Warning Flags for All Monitored ChannelsSix Quick Trips for Fast Monitoring of Critical
Functions for Laser SafetyFour 10-Bit Delta-Sigma Outputs Each Controlled by 72-Entry Temperature Lookup Table (LUT)Digital I/O Pins: Six Inputs, Five OutputsComprehensive Fault Measurement System with
Maskable Laser Shutdown CapabilityFlexible, Two-Level Password Scheme Provides
Three Levels of Security256 Additional Bytes Located at A0h Slave
AddressTransmitter 1 is Accessed at A2h Slave AddressTransmitter 2 is Accessed at B2h Slave AddressI2C-Compatible Interface+2.85V to +3.9V Operating Voltage Range-40NC to +95NC Operating Temperature Range28-Pin TQFN (5mm x 5mm x 0.8mm) Package
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
*EP = Exposed pad.
PARTTEMP RANGEPIN-PACKAGE
DS1876T+-40NC to +95NC28 TQFN-EP*
DS1876T+T&R-40NC to +95NC28 TQFN-EP*
SFP Controller with Dual LDD Interface
DS1876
TABLE OF CONTENTS
Absolute Maximum Ratings ......................................................................5
Recommended Operating Conditions ..............................................................5
DC Electrical Characteristics .....................................................................5
MOD_, APC_ Electrical Characteristics.............................................................6
Analog Quick-Trip Characteristics .................................................................6
Analog Voltage Monitoring Characteristics ..........................................................6
Digital Thermometer Characteristics ...............................................................7
AC Electrical Characteristics .....................................................................7
Quick-Trip Timing Characteristics..................................................................7
I2C AC Electrical Characteristics..................................................................7
Nonvolatile Memory Characteristics................................................................8
Typical Operating Characteristics .................................................................9
Pin Configuration .............................................................................10
Pin Description...............................................................................10
Block Diagram ...............................................................................11
Typical Operating Circuit .......................................................................12
Detailed Description...........................................................................12
DACs During Power-Up ......................................................................12
DACs as a Function of Transmit Disable (TXD1, TXD2)..............................................13
Quick-Trip Timing ...........................................................................13
Monitors and Fault Detection ..................................................................14
Monitors ................................................................................14
Six Quick-Trip Monitors and Alarms...........................................................14
Six ADC Monitors and Alarms...............................................................14
ADC Timing .............................................................................15
Right-Shifting ADC Result ..................................................................15
Low-Voltage Operation .......................................................................15
Delta-Sigma Outputs.........................................................................16
Digital I/O Pins..............................................................................18
IN1, RSEL, OUT1, RSELOUT................................................................18
TXF1, TXF2, TXFOUT, TXD1, TXD2, TXDOUT1, TXDOUT2 ........................................18
Transmit Fault (TXFOUT) Output.............................................................19
Die Identification ............................................................................19
I2C Communication ...........................................................................19
I2C Definitions..............................................................................19
I2C Protocol................................................................................21
SFP Controller with Dual LDD Interface
DS1876
Memory Organization..........................................................................22
Shadowed EEPROM.........................................................................23
Register Descriptions..........................................................................24
Memory Map Access Codes ..................................................................24
Memory Addresses A0h, A2h, and B2h..........................................................24
Lower Memory Register Map ..................................................................25
Table 01h Register Map ......................................................................25
Table 02h Register Map ......................................................................26
Table 04h Register Map ......................................................................26
Table 05h Register Map ......................................................................27
Table 06h Register Map ......................................................................27
Auxiliary Memory A0h Register Map ............................................................27
Lower Memory Register Descriptions............................................................28
Table 01h Register Descriptions................................................................40
Table 02h Register Descriptions................................................................44
Table 04h Register Descriptions................................................................64
Table 06h Register Descriptions................................................................65
Auxiliary Memory A0h Register Descriptions ......................................................68
Applications Information........................................................................69
Power-Supply Decoupling.....................................................................69
SDA and SCL Pullup Resistors.................................................................69
Package Information...........................................................................69
TABLE OF CONTENTS (continued)
SFP Controller with Dual LDD Interface
DS1876
LIST OF FIGURES
Figure 1. Power-Up Timing......................................................................13
Figure 2. TXD1, TXD2 Timing....................................................................13
Figure 3. Quick-Trip Sample Timing...............................................................14
Figure 4. ADC Round-Robin Timing...............................................................15
Figure 5. Low-Voltage Hysteresis Example .........................................................16
Figure 6. Recommended RC Filter for DAC Outputs in Voltage Mode and Current Sink Mode.................16
Figure 7. 3-Bit (8-Position) Delta-Sigma Example ....................................................17
Figure 8. DAC OFFSET LUTs....................................................................17
Figure 9. Logic Diagram 1 ......................................................................18
Figure 10. Logic Diagram 2 .....................................................................18
Figure 11a. TXFOUT Nonlatched Operation ........................................................19
Figure 11b. TXFOUT Latched Operation ...........................................................19
Figure 12. I2C Timing..........................................................................20
Figure 13. Example I2C Timing ..................................................................21
Figure 14. Memory Map........................................................................23
LIST OF TABLES
Table 1. Acronyms ............................................................................13
Table 2. ADC Default Monitor Full-Scale Ranges ....................................................14
SFP Controller with Dual LDD Interface
DS1876
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Voltage Range on PMON_, BMON_, RSEL,
IN1, TXF_, and TXD_ Pins
Relative to Ground ...............................-0.5V to (VCC + 0.5V)*
Voltage Range on VCC, SDA, SCL,
OUT1, RSELOUT, and TXFOUT Pins
Relative to Ground ...............................................-0.5V to +6V
Continuous Power Dissipation
28-Pin TQFN (derate 34.5mW/°C) above +70°C ....2758.6mW
Operating Temperature Range ..........................-40NC to +95NC
Programming Temperature Range .......................0NC to +95NC
Storage Temperature Range ............................-55NC to +125NC
Soldering Temperature .........................Refer to the IPC/JEDEC
J-STD-020 Specification.
RECOMMENDED OPERATING CONDITIONS
(TA = -40NC to +95NC, unless otherwise noted.)
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS
*Subject to not exceeding +6V.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Main Supply VoltageVCC(Note 1)+2.85+3.9V
High-Level Input Voltage
(SDA, SCL) VIH:10.7 x
VCC
VCC +
0.3V
Low-Level Input Voltage
(SDA, SCL)VIL:1-0.30.3 x
VCCV
High-Level Input Voltage
(TXD_, TXF_, RSEL, IN1)VIH:22.0VCC +
0.3V
Low-Level Input Voltage
(TXD_, TXF_, RSEL, IN1)VIL:2-0.3+0.8V
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Supply CurrentICC(Notes 1, 2)2.510mA
Output Leakage (SDA, OUT1,
RSELOUT, TXFOUT)ILO1FA
Low-Level Output Voltage
(SDA, OUT1, RSELOUT,
TXDOUT_, MOD_, APC_,
TXFOUT)
VOL
IOL = 4mA0.4
IOL = 6mA0.6
High-Level Output Voltage
(MOD_, APC_, TXDOUT_)VOHIOH = 4mAVCC -
0.4V
TXDOUT_ Before EEPROM
Recall10100nA
MOD_, APC_ Before RecallFigure 110100nA
Input Leakage Current
(SCL, TXD_, RSEL, IN1, TXF_)ILI1FA
Digital Power-On ResetPOD1.02.2V
Analog Power-On ResetPOA2.02.75V
SFP Controller with Dual LDD Interface
DS1876
MOD_, APC_ ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.)
ANALOG VOLTAGE MONITORING CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.)
ANALOG QUICK-TRIP CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Main Oscillator Frequency fOSC5MHz
Delta-Sigma Input-Clock
FrequencyfDSfOSC/2MHz
Reference Voltage Input (REFIN)VREFINMinimum 0.1FF to GND 2VCCV
Output Range 0VREFIN V
Output ResolutionSee the Delta-Sigma Outputs section for
details10Bits
Output ImpedanceRDS35100I
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
ADC Resolution 13Bits
Input/Supply Accuracy
(BMON_, PMON_, VCC) ACCAt factory setting 0.250.5%FS
Update Rate for Temperature,
BMON_, PMON_, VCC tRR6478ms
Input/Supply Offset
(BMON_, PMON_, VCC)VOS(Note 3)05LSB
Factory Setting (Note 4)BMON_, PMON_2.5VVCC 6.5536
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
TXP HI, TXP LO Full-Scale
Voltage2.507V
HBIAS Full-Scale Voltage1.25V
PMON_ Input Resistance355065kΩ
Resolution8Bits
ErrorTA = +25°C±2%FS
Integral Nonlinearity-1+1LSB
Differential Nonlinearity-1+1LSB
Temperature Drift-2.5+2.5%FS
Offset-5+10mV
SFP Controller with Dual LDD Interface
DS1876
DIGITAL THERMOMETER CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.)
AC ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.)
QUICK-TRIP TIMING CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.)
I2C AC ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA = -40NC to +95NC, timing referenced to VIL(MAX) and VIH(MIN), unless otherwise noted. See the I2C
Communication section.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Thermometer ErrorTERR-40NC to +95NC-3+3NC
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
TXD_ Enable tOFFFrom TXD_5Fs
Recovery from TXD_ Disable
(Figure 2)tONFrom TXD_1ms
Fault Reset Time (to TXFOUT = 0)
tINITR1From TXD_ 131tINITR2On power-up or TXD_, when VCC LO
alarm is detected (Note 5)161
Fault Assert Time (to TXFOUT = 1)tFAULTAfter HTXP_, LTXP_, HBATH_1.610.5Fs
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Output-Enable Time Following POAtINIT20ms
Sample Time per Quick-Trip
ComparisontREP1.6Fs
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SCL Clock FrequencyfSCL(Note 6)0400kHz
Clock Pulse-Width LowtLOW1.3Fs
Clock Pulse-Width HightHIGH0.6Fs
Bus Free Time Between STOP and
START ConditiontBUF1.3Fs
START Hold TimetHD:STA 0.6Fs
START Setup TimetSU:STA0.6Fs
Data Out Hold TimetHD:DAT00.9Fs
Data In Setup TimetSU:DAT100ns
Rise Time of Both SDA and SCL
Signals tR(Note 7)20 +
0.1CB300ns
Fall Time of Both SDA and SCL
SignalstF(Note 7)20 +
0.1CB300ns
STOP Setup Time tSU:STO0.6Fs
Capacitive Load for Each Bus LineCB400pF
SFP Controller with Dual LDD Interface
DS1876
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.85V to +3.9V, unless otherwise noted.)
Note 1: All voltages are referenced to ground. Current into the IC is positive, and current out of the IC is negative.
Note 2: Inputs are at supply rail. Outputs are not loaded.
Note 3: This parameter is guaranteed by design.
Note 4: Full scale is user programmable.
Note 5: A temperature conversion is completed and MOD1 DAC, MOD2 DAC, APC1 DAC, and APC2 DAC values are recalled
from the LUT and VCC has been measured to be above VCC LO alarm, if the VCC LO alarm is enabled.
Note 6: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C stan-
dard mode.
Note 7: CB—Total capacitance of one bus line in pF.
Note 8: EEPROM write begins after a STOP condition occurs.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
EEPROM Write CyclesAt +25NC200,000
At +85NC50,000
SFP Controller with Dual LDD Interface
DS1876
Typical Operating Characteristics
(VCC = 3.3V, TA = +25°C, unless otherwise noted.)
PMON1/2 AND BMON1/2 INL
DS1876 toc06
PMON1/2 AND BMON1/2 INL (LSB)
USING FACTORY-PROGRAMMED FULL-SCALE
VALUE OF 2.5V
PMON1/2 AND BMON1/2 DNL
DS1876 toc05
PMON1/2 AND BMON1/2 DNL (LSB)
USING FACTORY-PROGRAMMED FULL-SCALE
VALUE OF 2.5V
APC1/2 AND MOD1/2 DAC INL
DS1876 toc04
DAC POSITION (DEC)
APC1/2 AND MOD1/2 DAC INL (LSB)
APC1/2 AND MOD1/2 DAC DNL
DS1876 toc03
DAC POSITION (DEC)
APC1/2 AND MOD1/2 DAC DNL (LSB)
SUPPLY CURRENT vs. TEMPERATURE
DS1876 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)3510-15
DAC POSITIONS = 1FFh
SDA = SCL = VCC
VCC = 3.9V
VCC = 3.3V
VCC = 2.85V
SUPPLY CURRENT vs. SUPPLY VOLTAGE
DS1876 toc01
VCC (V)
SUPPLY CURRENT (mA)
SDA = SCL = VCC
DACs AT 1FFh
+95°C
+25°C
-40°C
SFP Controller with Dual LDD Interface
DS1876
Pin Configuration
Pin Description
THIN QFN
(5mm × 5mm × 0.8mm)TOP VIEW
SCL
TXFOUT
TXF1
IN1
TXD1
RSELOUT
MOD1GNDTXDOUT2GNDV
N.C.2
APC15672119171615
VCC
TXF2
BMON2
PMON2
TXDOUT1
RSEL
SDA
MOD28OUT1GND
APC213PMON1TXD214BMON1REFIN
DS1876
*EP
+*EXPOSED PAD.
PINNAMEFUNCTIONRSELOUTRate-Select OutputSCLI2C Serial-Clock InputSDAI2C Serial-Data Input/OutputTXFOUTTransmit Fault Output, Open
DrainTXF1Transmit Fault Input 1IN1
Digital Input. General-purpose
input, AS1 in SFF-8079, or RS1
in SFF-8431. TXD1Transmit Disable Input 1
8, 18, 21GNDGround ConnectionRSELRate-Select InputTXDOUT1Transmit Disable Output 1PMON2External Monitor Input PMON2
and HTXP2/LTXP2 Quick Trip BMON2External Monitor Input BMON2
and HBATH2 Quick TripPMON1External Monitor Input PMON1
and HTXP1/LTXP1 Quick Trip
PINNAMEFUNCTIONBMON1External Monitor Input BMON1
and HBATH1 Quick TripN.C.No Connection
16, 26VCCPower-Supply InputTXDOUT2Transmit Disable Output 2MOD2MOD2 DAC, Delta-Sigma OutputMOD1MOD1 DAC, Delta-Sigma OutputREFINReference Input for DAC1 and
DAC2 TXD2Transmit Disable Input 2APC2APC2 DAC, Delta-Sigma OutputAPC1APC1 DAC, Delta-Sigma OutputTXF2Transmit Fault Input 2OUT1
Digital Output. General-purpose
output, AS1 output in SFF-8079,
or RS1 output in SFF-8431.EPExposed Pad (Connect to GND)
SFP Controller with Dual LDD Interface
DS1876
Block Diagram
ANALOG MUX
MAIN MEMORY
EEPROM/SRAM
A/D CONFIGURATION/RESULTS,
SYSTEM STATUS/CONTROL BITS,
ALARMS/WARNINGS,
LOOKUP TABLES,
USER MEMORY
I2C
INTERFACE
TEMPERATURE
SENSOR
LOGIC
CONTROL
POWER-ON
ANALOG
INTERRUPT
13-BIT
ADC
EEPROM
256 BYTES
AT A0h
SDA
SCL
VCC
VCC
VCC
BMON1
PMON1
PMON2
BMON2
LOGIC
CONTROL
MOD2 DAC
10 BITS
APC2 DAC
10 BITS
8-BIT
QTs
MOD2
APC2
MOD1 DAC
10 BITSMOD1
APC1 DAC
10 BITSAPC1
TXFOUT
REFIN
TXDOUT1
RSELOUT
OUT1
TXD1
TXD2
TXF1
TXF2
RSEL
IN1
GNDDS1876
VCC
TXDOUT2
VCC
SFP Controller with Dual LDD Interface
DS1876
Detailed Description
The DS1876 integrates the control and monitoring func-
tionality required in a dual transmitter system. Key com-
ponents of the DS1876 are shown in the Block Diagram
and described in subsequent sections.
DACs During Power-Up
On power-up, the DS1876 sets the DACs to high imped-
ance. After time tINIT, the DACs are set to an initial condition
set in EEPROM. After a temperature conversion is com-
pleted and if the VCC LO alarm is enabled, an additional
VCC conversion above the customer-defined VCC LO
alarm level is required before the DACs are updated with
the value determined by the temperature conversion and
the DAC LUT.
If a fault is detected, and TXD1 and TXD2 are toggled
to re-enable the outputs, the DS1876 powers up fol-
lowing a similar sequence to an initial power-up. The
Typical Operating Circuit
TXF1
DISABLE
FAULT
TX_FAULT
TX_DISABLE1
TX_DISABLE2
MOD1
DAC
APC1
DAC
MOD2
DAC
APC2
DAC
LDD1
EEPROM
QUICK
TRIP
ADC
SDA
SCL
TXDOUT2
TXD2
TXDOUT1
TXFOUT
TXF2
TXD1
MODE_DEF2 (SDA)
MODE_DEF1 (SCL)I2C
DS1876
BMON1
PMON1
BMON2
PMON2
BMON
APCIN
APCSET
MODSET
RB1RP2RB1RP1
TOSA1
DISABLE
FAULT
LDD2
BMON
APCIN
APCSET
MODSET
RC FILTERS
(FIGURE 6)
TOSA2
SFP Controller with Dual LDD Interface
DS1876
only difference is that the DS1876 already has deter-
mined the present temperature, so the tINIT time is not
required for the DS1876 to recall the APC and MOD
set points from EEPROM. See Figure 1.
DACs as a Function of Transmit Disable
(TXD1, TXD2)
If TXD1 or TXD2 are asserted (logic 1) during normal
operation, the associated outputs are disabled within
tOFF. When TXD1 or TXD2 are deasserted (logic 0), the
DS1876 sets the DACs with the value associated with
the present temperature. When asserted, soft TXD1 or
soft TXD2 (TXDC) (Lower Memory, Register 6Eh) would
allow a software control identical to the TXD1 or TXD2 pin
(Figure 2). The POLARITY register (Table 02h, Register
C6h) determines if the off-state value of the DACs is
VREFIN or 0V.
Quick-Trip Timing
As shown in Figure 3, the DS1876’s input compara-
tor is shared among the six quick-trip alarms (TXP1
HI, TXP1 LO, TXP2 HI, TXP2 LO, BIAS1 HI, and BIAS2
HI). The comparator polls the alarms in a multiplexed
sequence. The updates are used to compare the HTXP1,
LTXP1, HTXP2, and LTXP2 (monitor diode voltages) and
the HBATH1 and HBATH2 (BMON1, BMON2) signals
against the internal APC and BIAS reference, respec-
tively. Depending on the results of the comparison, the
Table 1. Acronyms
Figure 1. Power-Up Timing
VCC
VPOA
DAC
SETTINGSHIGH IMPEDANCEOFF STATELUT VALUE
500μstINIT
tOFFtON
TXD_
DAC
SETTINGSLUT VALUELUT VALUEOFF STATE
ACRONYMDESCRIPTION
ADCAnalog-to-Digital Converter
AGCAutomatic Gain Control
APCAutomatic Power Control
APDAvalanche Photodiode
ATBAlarm Trap Bytes
DACDigital-to-Analog Converter
LOSLoss of Signal
LUTLookup TableNonvolatileQuick TripTracking Error
TIATransimpedance Amplifier
ROSAReceiver Optical Subassembly
SEEShadowed EEPROM
SFFSmall Form Factor
SFF-8472Document Defining Register Map of SFPs
and SFFs
SFPSmall Form Factor Pluggable
SFP+Enhanced SFP
TOSATransmit Optical Subassembly
TXPTransmit Power
SFP Controller with Dual LDD Interface
DS1876
corresponding alarms and warnings (TXP HI1, TXP LO1,
TXP HI2, TXP LO2, BIAS HI1, and BIAS HI2) are asserted
or deasserted.
After resetting, the device completes one QT cycle
before making comparisons. The TXP LO quick-trip
alarm updates its alarm bit, but does not create FETG
until after TXDEXT. TXP HI and BIAS HI can also be con-
figured to wait for TXDEXT; however, this can be disabled
using QTHEXT_ (Table 02h, Register 88h).
Monitors and Fault Detection
Monitors
Monitoring functions on the DS1876 include six quick-
trip comparators and six ADC channels. This monitoring
combined with the alarm enables (Table 01h/05h) deter-
mines when/if the DS1876 turns off DACs and triggers
the TXFOUT and TXDOUT1, TXDOUT2 outputs. All the
monitoring levels and interrupt masks are user program-
mable.
Six Quick-Trip Monitors and Alarms
Six quick-trip monitors are provided to detect potential
laser safety issues and LOS status. These monitor the
following:
1) High Bias Current 1 (HBATH1), causing QT BIAS1 HI
2) Low Transmit Power 1 (LTXP1), causing QT TXP1 LO
3) High Transmit Power 1 (HTXP1), causing QT TXP1 HI
4) High Bias Current 2 (HBATH2), causing QT BIAS2 HI
5) Low Transmit Power 2 (LTXP2), causing QT TXP2 LO
6) High Transmit Power 2 (HTXP2), causing QT TXP2 HI
The high and low transmit power quick-trip registers
(HTXP1, HTXP2, LTXP1, and LTXP2) set the thresholds
used to compare against the PMON1 and PMON2 volt-
ages to determine if the transmit power is within speci-
fication. The HBATH1 and HBATH2 QTs compare the
BMON1 and BMON2 inputs (generally from the laser
driver’s bias monitor output) against their threshold set-
tings to determine if the present bias current is above
specification. The bias and power QTs are routed to
FETG through interrupt masks to allow combinations
of these alarms to be used to trigger FETG. The bias
and power QTs are directly connected to TXFOUT (see
Figure 9). The user can program up to eight different
temperature-indexed threshold levels for HBATH1 and
HBATH2 (Table 06h, Registers E0h-E7h).
Six ADC Monitors and Alarms
The ADC monitors six channels that measure tem-
perature (internal temp sensor), VCC, PMON1, PMON2,
BMON1, and BMON2 using an analog multiplexer to
measure them round-robin with a single ADC (see the
ADC Timing section). The channels have a customer-
programmable full-scale range, and all channels have a
customer-programmable offset value that is factory pro-
grammed to a default value (see Table 2). Additionally,
PMON1, PMON2 and BMON1, BMON2 can right-shift
results by up to 7 bits before the results are compared
to alarm thresholds or read over the I2C bus. This allows
customers with specified ADC ranges to calibrate the
ADC full scale to a factor of 1/2n of their specified range
to measure small signals. The DS1876 can then right-
Figure 3. Quick-Trip Sample Timing
Table 2. ADC Default Monitor Full-Scale Ranges
QUICK-TRIP SAMPLE TIMESLTXP2
SAMPLE
HBIAS1
SAMPLE
HBIAS1
SAMPLE
HBIAS2
SAMPLE
HTXP1
SAMPLE
HTXP2
SAMPLE
LTXP1
SAMPLE
LTXP2
SAMPLE
tREP
QT CYCLE
SIGNAL (UNITS)+FS SIGNAL+FS HEX-FS SIGNAL-FS HEX
Temperature (NC)127.9967FFF-1288000
VCC (V)6.5528FFF800000
PMON1, PMON2 and BMON1, BMON2 (V)2.4997FFF800000
SFP Controller with Dual LDD Interface
DS1876
The ADC results (after right-shifting, if used) are com-
pared to the alarm and warning thresholds after each
conversion, and the corresponding alarms are set that
can be used to trigger the TXFOUT output. These ADC
thresholds are user programmable, as are the masking
registers that can be used to prevent the alarms from trig-
gering the TXFOUT output.
ADC Timing
There are six analog channels that are digitized in a
round-robin fashion in the order as shown in Figure 4.
The total time required to convert all six channels is tRR
(see the Analog Voltage Monitoring Characteristics table
for details).
Right-Shifting ADC Result
If the weighting of the ADC digital reading must conform
to a predetermined full-scale (PFS) value defined by
a standard’s specification (e.g., SFF-8472), then right-
shifting can be used to adjust the PFS analog measure-
ment range while maintaining the weighting of the ADC
results. The DS1876’s range is wide enough to cover all
requirements; when the maximum input value is P 1/2
the FS value, right-shifting can be used to obtain greater
accuracy. For instance, the maximum voltage might be
1/8 the specified PFS value, so only 1/8 of the converter’s
range is effective over this range. An alternative is to cali-
brate the ADC’s full-scale range to 1/8 the readable PFS
value and use a right-shift value of 3. With this implemen-
tation, the resolution of the measurement is increased by
a factor of 8, and because the result is digitally divided
by 8 by right-shifting, the bit weight of the measurement
still meets the standard’s specification (i.e., SFF-8472).
The right-shift operation on the ADC result is carried
out based on the contents of right-shift control registers
(Table 02h, Registers 8Eh-8Fh) in EEPROM. Four analog
channels—PMON1, PMON2, BMON1, and BMON2—
each have 3 bits allocated to set the number of right-
shifts. Up to seven right-shift operations are allowed and
are executed as a part of every conversion before the
results are compared to the high and low alarm levels, or
loaded into their corresponding measurement registers
(Lower Memory, Registers 64h–6Bh). This is true during
the setup of internal calibration as well as during subse-
quent data conversions.
Low-Voltage Operation
The DS1876 contains two power-on reset (POR) levels.
The lower level is a digital POR (POD) and the higher
level is an analog POR (POA). At startup, before the sup-
ply voltage rises above POA, the outputs are disabled,
all SRAM locations are set to their defaults, shadowed
EEPROM (SEE) locations are zero, and all analog cir-
cuitry is disabled. When VCC reaches POA, the SEE is
recalled, and the analog circuitry is enabled. While VCC
remains above POA, the device is in its normal operating
state, and it responds based on its nonvolatile configu-
ration. If during operation VCC falls below POA, but is
still above POD, the SRAM retains the SEE settings from
the first SEE recall, but the device analog is shut down
and the outputs disabled. If the supply voltage recovers
back above POA, the device immediately resumes nor-
mal operation. If the supply voltage falls below POD, the
device SRAM is placed in its default state and another
SEE recall is required to reload the nonvolatile settings.
The EEPROM recall occurs the next time VCC next
exceeds POA. Figure 5 shows the sequence of events
as the voltage varies.
Any time VCC is above POD, the I2C interface can be
used to determine if VCC is below the POA level. This
is accomplished by checking the RDYB bit in the status
byte (Lower Memory, Register 6Eh). RDYB is set when
VCC is below POA; when VCC rises above POA, RDYB
is timed (within 500Fs) to go to 0, at which point the part
is fully functional.
Figure 4. ADC Round-Robin Timing
TEMPVCCBMON1BMON2PMON1PMON2TEMP
ONE ROUND-ROBIN ADC CYCLE
tRR
NOTE: IF THE VCC LO ALARM IS ENABLED AT POWER-UP, THE ADC ROUND-ROBIN TIMING CYCLES BETWEEN TEMPERATURE AND VCC ONLY UNTIL VCC IS ABOVE THE VCC LOALARM THRESHOLD. THIS ALSO OCCURS IF THERE ARE BOTH A TXD1 EVENT AND A TXD2 EVENT UNDER THE SAME CONDITIONS AS PREVIOUSLY MENTIONED.
SFP Controller with Dual LDD Interface
DS1876
For all device addresses sourced from EEPROM (Table
02h, Register 8Bh), the default device addresses are
A2h and B2h until VCC exceeds POA allowing the device
address to be recalled from the EEPROM.
Delta-Sigma Outputs
Four delta-sigma outputs are provided: MOD1, MOD2,
APC1, and APC2. With the addition of an external RC
filter, these outputs provide 10-bit resolution analog
outputs with the full-scale range set by the input REFIN.
Each output is either manually controlled or controlled
using a temperature-indexed LUT.
A delta-sigma DAC has a digital output using pulse-
density modulation. It provides much lower output ripple
than a standard digital PWM output given the same clock
rate and filter components. Before tINIT, the DAC outputs
are high impedance. The external RC filter components
are chosen based on ripple requirements, output load,
delta-sigma frequency, and desired response time.
Figure 6 shows a recommended filter.
For illustrative purposes, a 3-bit example is provided in
Figure 7.
In LUT mode the DACs are each controlled by an LUT
with high-temperature resolution and an OFFSET LUT
with lower temperature resolution. The high-resolution
LUTs each have 2NC resolutions. The OFFSET LUTs
are located in the upper eight registers (F8h-FFh) of
the table containing each high-resolution LUT. The DAC
values are determined as follows:
DAC value = LUT + 4 x (OFFSET LUT)
An example calculation for MOD1 DAC is as follows:
Assumptions:
1) Temperature is +43NC
2) Table 04h (MOD1 OFFSET LUT), Register FCh = 2Ah
3) Table 04h (MOD1 LUT), Register AAh = 7Bh
Because the temperature is +43NC, the MOD1 LUT index
is AAh and the MOD1 OFFSET LUT index is FCh.
MOD1 DAC = 7Bh + 4 x 2Ah = 123h = 291
Figure 6. Recommended RC Filter for DAC Outputs in Voltage
Mode and Current Sink Mode
Figure 5. Low-Voltage Hysteresis Example
DS1876
DAC
3.24kΩ3.24kΩ
0.01µF0.01µF
VOLTAGE OUTPUT
DS1876
DAC
1kΩ1kΩ
0.1µF0.1µF
CURRENT SINK
2kΩ
VPOA
VPOD
VCC
SEERECALLED VALUERECALLED VALUEPRECHARGED
TO 0
PRECHARGED
TO 0PRECHARGED TO 0
SEE RECALLSEE RECALL
SFP Controller with Dual LDD Interface
DS1876
Figure 7. 3-Bit (8-Position) Delta-Sigma Example
Figure 8. DAC OFFSET LUTs
When temperature controlled, the DACs are updated
after each temperature conversion.
The reference input, REFIN, is the supply voltage for the
output buffer of all four DACs. The voltage connected to
REFIN and its decoupling must be able to support the
edge rate requirements of the delta-sigma outputs. In
a typical application, a 0.1FF capacitor should be con-
nected between REFIN and ground.
DAC OFFSET LUTs (04h/06h)[A2h/B2h]
EIGHT REGISTERS PER DACDELTA-SIGMA DACs
EACH OFFSET REGISTER CAN BE INDEPENDENTLY SET BETWEEN
0 AND 1020. 1020 = 4 x FFh. THIS EXAMPLE ILLUSTRATES POSITIVE
AND NEGATVE TEMPCO.
DAC
LUT
BITS
7:0
F8hDAC
LUT
BITS
7:0
F9hDAC
LUT
BITS
7:0
FAhDAC
LUT
BITS
7:0
FBhDAC
LUT
BITS
7:0
FChDAC
LUT
BITS
7:0
FDh
DAC
LUT
BITS
7:0
FEh
DAC
LUT
BITS
7:0
FFh
-40°C-8°C+8°C+24°C+40°C+56°C+70°C+88°C+104°C
DELTA-SIGMA DACs
EACH OFFSET REGISTER CAN BE INDEPENDENTLY
SET BETWEEN 0 AND 1020. 1020 = 4 x FFh. THIS
EXAMPLE ILLUSTRATES POSITIVE TEMPCO.
DAC
LUT
BITS
7:0
F8h
DAC
LUT
BITS
7:0
F9hDAC
LUT
BITS
7:0
FAhDAC
LUT
BITS
7:0
FBhDAC
LUT
BITS
7:0
FCh
DAC
LUT
BITS
7:0
FDh
DAC
LUT
BITS
7:0
FEh
DAC
LUT
BITS
7:0
FFh
DAC OFFSET LUTs (04h/06h)[A2h/B2h]
EIGHT REGISTERS PER DAC-40°C-8°C+8°C+24°C+40°C+56°C+70°C+88°C+104°C
SFP Controller with Dual LDD Interface
DS1876
Digital I/O Pins
Six digital input pins and five digital output pins are pro-
vided for monitoring and control.
IN1, RSEL, OUT1, RSELOUT
Digital input pins IN1 and RSEL primarily serve to meet
the rate-select requirements of SFP and SFP+. They
can also serve as general-purpose inputs. OUT1 and
RSELOUT are driven by a combination of the IN1, RSEL,
and logic dictated by control registers in the EEPROM
(see Figure 10). The levels of IN1 and RSEL can be
read from the STATUS register (Lower Memory, Register
6Eh). The open-drain output OUT1 can be controlled
Register 89h). The open-drain RSELOUT output is
software controlled and/or inverted through the STATUS
register and CNFGA register (Table 02h, Register 88h).
External pullup resistors must be provided on OUT1 and
RSELOUT to realize high logic levels.
TXF1, TXF2, TXFOUT, TXD1, TXD2,
TXDOUT1, TXDOUT2
TXDOUT1 and TXDOUT2 are generated from a com-
bination of TXF1, TXF2, TXD1, TXD2, and the internal
signals FETG1 and FETG2 (Table 02h, Register 8Ah). A
software control identical to TXD1 and TXD2 is also avail-
able (TXDC1 and TXDC2, Lower Memory, Register 6Eh).
A TXD1 or TXD2 pulse is internally extended (TXDEXT)
by time tINITR1 to inhibit the latching of low alarms and
warnings related to the APC loop to allow for the loop to
stabilize. The nonlatching alarms and warnings are TXP
LO, BMON1 LO, BMON2 LO, PMON1 LO, and PMON2
LO. In addition, TXP LO is disabled from creating FETG.
See the Transmit Fault (TXFOUT) Output section for a
detailed explanation of TXFOUT. As shown in Figure 9,
the same signals and faults can also be used to gener-
ate the internal signal FETG. FETG is used to send a fast
“turn-off” command to the laser driver. The intended use
is a direct connection to the laser driver’s TXD1, TXD2
input if this is desired. When VCC < POA, TXDOUT1 and
Figure 9. Logic Diagram 1
Figure 10. Logic Diagram 2
OUTIN
TXDS_
TXFS_
RPUSET BIAS_ DAC AND
MOD_ DAC TO HIGH
IMPEDANCE
TXD_
TXFINT
INVTXF_
TXFOUTS1
TXFOUTS2
TXF_
TXP_ HI FLAG
TXP HI ENABLE
HBAL_ FLAG
HBAL ENABLE
QTHEXT_
TXP_ LO FLAG
TXP LO ENABLE
TXDEXT (tINITR1)
TXDC_
VCC
TXD_
TXDOUT_
TXFOUTS_
TXDIO_
TXDFG_
FETG_
TXDFLT_
FAULT RESET TIMER
(130ms)
OUT
POWER-ON
RESET
TXFOUT
NOTE:_ CAN BE EITHER 1 OR 2 CORRESPONDING TO TRANSMITTERS 1 OR 2.
REFERS TO A PIN.
INVOUT1
IN1C
IN1
IN1SOUT1
INVRSOUTRSELOUT
RSELC
RSEL
RSELS
= PINS
SFP Controller with Dual LDD Interface
DS1876
Transmit Fault (TXFOUT) Output
TXFOUT can be triggered by all alarms, warnings, QTs,
TXD1, TXD2, TXF1, and TXF2 (see Figure 9). The six
ADC alarms and warnings are controlled by enable bits
(Table 01h/05h, Registers F8h and FCh). See Figures
11a and 11b for nonlatched and latched operation for
TXFOUT. The CNFGB register (Table 02h, Register 89h)
controls the latching of the alarms.
Die Identification
The DS1876 has an ID hardcoded in its memory. Two
registers (Table 02h, Registers 86h-87h) are assigned
for this feature. Register 86h reads 76h to identify the
part as the DS1876; Register 87h reads the present
device version.
I2C Communication
I2C Definitions
The following terminology is commonly used to describe
I2C data transfers.
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses and START and STOP conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between STOP and
START conditions when both SDA and SCL are inac-
START Condition: A START condition is generated
by the master to initiate a new data transfer with a
slave. Transitioning SDA from high to low while SCL
remains high generates a START condition. See
Figure 12 for applicable timing.
STOP Condition: A STOP condition is generated
by the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition. See Figure 12 for
applicable timing.
Repeated START Condition: The master can use
a repeated START condition at the end of one data
transfer to indicate that it will immediately initiate a
new data transfer following the current one. Repeated
STARTs are commonly used during read operations
to identify a specific memory address to begin a data
transfer. A repeated START condition is issued identi-
cally to a normal START condition. See Figure 12 for
applicable timing.
Bit Write: Transitions of SDA must occur during the
low state of SCL. The data on SDA must remain valid
and unchanged during the entire high pulse of SCL
plus the setup and hold time requirements (Figure 12).
Data is shifted into the device during the rising edge
of the SCL.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount
Figure 11a. TXFOUT Nonlatched Operation
Figure 11b. TXFOUT Latched Operation
DETECTION OF TXFOUT FAULT
TXFOUT
DETECTION OF TXFOUT FAULT
TXD_ OR TXFOUT RESET
TXFOUT
SFP Controller with Dual LDD Interface
DS1876
of SCL during a bit read. The device shifts out each
bit of data on SDA at the falling edge of the previous
SCL pulse and the data bit is valid at the rising edge
of the current SCL pulse. Remember that the master
generates all SCL clock pulses, including when it is
reading bits from the slave.
Acknowledgement (ACK and NACK): An acknowl-
edgement (ACK) or not-acknowledge (NACK) is
always the 9th bit transmitted during a byte transfer.
The device receiving data (the master during a read
or the slave during a write operation) performs an ACK
by transmitting a zero during the 9th bit. A device per-
forms a NACK by transmitting a one during the 9th bit.
Timing (Figure 12) for the ACK and NACK is identical
to all other bit writes. An ACK is the acknowledgment
that the device is properly receiving data. A NACK is
used to terminate a read sequence or as an indication
that the device is not receiving data.
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most
significant bit first) plus a 1-bit acknowledgement from
the slave to the master. The 8 bits transmitted by the
master are done according to the bit write definition
and the acknowledgement is read using the bit read
definition.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the
bit read definition, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must NACK the last byte read to
terminate communication so the slave returns control
of SDA to the master.
Slave Address Byte: Each slave on the I2C bus
responds to a slave address byte sent immediately
following a START condition. The slave address byte
contains the slave address in the most significant 7 bits
and the R/W bit in the least significant bit.
The DS1876 responds to three slave addresses. The
auxiliary memory always responds to a fixed I2C slave
address, A0h. (If the main device’s slave address
is programmed to be A0h, access to the auxiliary
memory is disabled.) The Lower Memory and Tables
00h–06h respond to I2C slave addresses whose lower
3 bits are configurable (A0h–AEh, B0h-BEh) using the
DEVICE ADDRESS byte (Table 02h, Register 8Bh). The
user also must set the ASEL bit (Table 02h, Register
88h) for this address to be active. By writing the cor-
rect slave address with R/W = 0, the master indicates
it writes data to the slave. If R/W = 1, the master reads
data from the slave. If an incorrect slave address is
written, the DS1876 assumes the master is communi-
cating with another I2C device and ignores the com-
munications until the next START condition is sent.
Memory Address: During an I2C write operation
to the DS1876, the master must transmit a memory
address to identify the memory location where the
slave is to store the data. The memory address is
SCL
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).SDA
STOPSTARTREPEATED
START
tBUF
tHD:STA
tHD:DATtSU:DAT
tSU:STO
tHD:STAtSP
tSU:STAtHIGH
tLOW
SFP Controller with Dual LDD Interface
DS1876
always the second byte transmitted during a write
operation following the slave address byte.
I2C Protocol
See Figure 13 for an example of I2C timing.
Writing a Single Byte to a Slave: The master must
generate a START condition, write the slave address
byte (R/W = 0), write the memory address, write
the byte of data, and generate a STOP condition.
Remember that the master must read the slave’s
acknowledgement during all byte write operations.
Writing Multiple Bytes to a Slave: To write multiple
bytes to a slave, the master generates a START condi-
tion, writes the slave address byte (R/W = 0), writes
the memory address, writes up to 8 data bytes, and
generates a STOP condition. The DS1876 writes 1 to
8 bytes (one page or row) with a single write trans-
action. This is internally controlled by an address
counter that allows data to be written to consecutive
addresses without transmitting a memory address
before each data byte is sent. The address counter
limits the write to one 8-byte page (one row of the
memory map). Attempts to write to additional pages
of memory without sending a STOP condition between
pages result in the address counter wrapping around
to the beginning of the present row.
For example: A 3-byte write starts at address 06h and
writes three data bytes (11h, 22h, and 33h) to three
“consecutive” addresses. The result is that addresses
06h and 07h would contain 11h and 22h, respec-
tively, and the third data byte, 33h, would be written
to address 00h.
To prevent address wrapping from occurring, the
master must send a STOP condition at the end of
the page, then wait for the bus-free or EEPROM write
time to elapse. Then the master can generate a new
START condition and write the slave address byte
(R/W = 0) and the first memory address of the next
memory row before continuing to write data.
Acknowledge Polling: Any time a EEPROM page is
written, the DS1876 requires the EEPROM write time
(tWR) after the STOP condition to write the contents of
the page to EEPROM. During the EEPROM write time,
the DS1876 does not acknowledge its slave address
because it is busy. It is possible to take advantage
of that phenomenon by repeatedly addressing the
DS1876, which allows the next page to be written
as soon as the DS1876 is ready to receive the data.
The alternative to acknowledge polling is to wait for
maximum period of tWR to elapse before attempting
to write again to the DS1876.
START
STARTSTOP
SLAVE
ACK
SLAVE
ACK
STOP
SINGLE-BYTE WRITE
-WRITE 00h TO REGISTER BAh
TWO-BYTE WRITE
-WRITE 01h AND 75h TO
REGISTERS C8h AND C9h
SINGLE-BYTE READ
-READ REGISTER BAh
TWO-BYTE READ
-READ C8h AND C9h
REPEATED
START
MASTER
NACK0100010
A2h0111010
BAh
SLAVE
ACK
STARTSLAVE
ACK10100010
A2h0100011
A3h0111010
BAh
SLAVE
ACK
SLAVE
ACK
STOP0000000
00h
STOPSLAVE
ACK
STOP1110101
75h
STARTSLAVE
ACK10100010
A2h1001000
C8h
SLAVE
ACK
SLAVE
ACK00000001
01h
SLAVE
ACKDATA IN BAh
DATA
REPEATED
START
MASTER
ACKSTARTSLAVE
ACK10100010
A2h0100011
A3h1001000
C8h
SLAVE
ACK
SLAVE
ACKDATA IN C8h
DATA
MASTER
NACKDATA IN C9h
DATA
EXAMPLE I2C TRANSACTIONS WITH A2h AS THE SLAVE ADDRESS
*IF ASEL IS 0, THE SLAVE ADDRESS IS A0h FOR THE AUXILIARY MEMORY AND A2h/B2h FOR THE MAIN MEMORY.
IF ASEL = 1, THE SLAVE ADDRESS IS DETERMINED BY TABLE 02h, REGISTER 8Bh FOR THE MAIN MEMORY. THE AUXILIARY MEMORY CONTINUES TO BE ADDRESSED AT A0h, EXCEPT WHEN THE PROGRAMMED
ADDRESS FOR THE MAIN MEMORY IS A0h.
TYPICAL I2C WRITE TRANSACTION
MSBLSBb6b5b4b3b2b1b0
REGISTER ADDRESS
MSBLSBb6b5b4b3b2b1b0
DATA
SLAVE
ACK
SLAVE
ACK
SLAVE
ADDRESS*XXX001R/W
MSBLSB
READ/
WRITE
SFP Controller with Dual LDD Interface
DS1876
EEPROM Write Cycles: When EEPROM writes occur,
the DS1876 writes the whole EEPROM memory page,
even if only a single byte on the page was modified.
Writes that do not modify all 8 bytes on the page are
allowed and do not corrupt the remaining bytes of
memory on the same page. Because the whole page
is written, bytes on the page that were not modi-
fied during the transaction are still subject to a write
cycle. This can result in a whole page being worn
out over time by writing a single byte repeatedly.
Writing a page 1 byte at a time wears the EEPROM
out 8x faster than writing the entire page at once. The
DS1876’s EEPROM write cycles are specified in the
Nonvolatile Memory Characteristics table. The speci-
fication shown is at the worst-case temperature. It can
handle approximately 10x that many writes at room
temperature. Writing to SRAM-shadowed EEPROM
memory with SEEB = 1 does not count as a EEPROM
write cycle when evaluating the EEPROM’s estimated
lifetime.
Reading a Single Byte from a Slave: Unlike the
write operation that uses the memory address byte
to define where the data is to be written, the read
operation occurs at the present value of the memory
address counter. To read a single byte from the slave,
the master generates a START condition, writes the
slave address byte with R/W = 1, reads the data byte
with a NACK to indicate the end of the transfer, and
generates a STOP condition.
Manipulating the Address Counter for Reads: A
dummy write cycle can be used to force the address
pointer to a particular value. To do this, the mas-
ter generates a START condition, writes the slave
address byte (R/W = 0), writes the memory address
where it desires to read, generates a repeated START
condition, writes the slave address byte (R/W = 1),
reads data with ACK or NACK as applicable, and
generates a STOP condition.
Memory Organization
The DS1876 features nine separate memory tables
that are internally organized into 8-byte rows. The main
device located at A2h is used for overall device con-
figuration and transmitter 1 control, calibration, alarms,
warnings, and monitoring.
Lower Memory, A2h is addressed from 00h–7Fh and
contains alarm and warning thresholds, flags, masks,
several control registers, password entry area (PWE),
Table 01h, A2h primarily contains user EEPROM (with
PW1 level access) as well as alarm and warning enable
bytes.
Table 02h, A2h/B2h is a multifunction space that con-
tains configuration registers, scaling and offset values,
passwords, and interrupt registers as well as other mis-
cellaneous control bytes. All functions and status can be
written and read from either A2h or B2h addresses.
Table 04h, A2h contains a temperature-indexed LUT for
control of the MOD1 voltage. The MOD1 LUT can be pro-
grammed in 2NC increments over the -40NC to +102NC
range. This also contains a temperature-indexed LUT for
the MOD1 offsets.
Table 05h, A2h is empty by default. It can be config-
ured to contain the alarm and warning enable bytes
from Table 01h, Registers F8h–FFh with the MASK bit
enabled (Table 02h, Register 88h). In this case Table
01h is empty.
Table 06h, A2h contains a temperature-indexed LUT for
control of the APC1 voltage. The APC1 LUT can be pro-
grammed in 2NC increments over the -40NC to +102NC
range. This also contains a temperature-indexed LUT for
the APC1 offsets.
The main device located at B2h is used for transmitter 2
control, calibration, alarms, warnings, and monitoring.
Lower Memory, B2h is addressed from 00h–7Fh and
contains alarm and warning thresholds, flags, masks,
several control registers, PWE, and the table-select byte.
Table 01h, B2h contains alarm and warning enable
bytes.
Table 04h, B2h contains a temperature-indexed LUT for
control of the MOD2 voltage. The MOD2 LUT can be pro-
grammed in 2NC increments over the -40NC to +102NC
range. This also contains a temperature-indexed LUT for
the MOD2 offsets.
Table 05h, B2h is empty by default. It can be config-
ured to contain the alarm and warning enable bytes
from Table 01h, Registers F8h–FFh with the MASK bit
enabled (Table 02h, Register 88h). In this case Table
01h is empty.
Table 06h, B2h contains a temperature-indexed LUT for
control of the APC2 voltage. The APC2 LUT can be pro-
grammed in 2NC increments over the -40NC to +102NC
range. This also contains a temperature-indexed LUT for
the APC2 offsets.
SFP Controller with Dual LDD Interface
DS1876
Auxiliary Memory (Device A0h) contains 256 bytes
of EE memory accessible from address 00h–FFh. It is
selected with the device address of A0h.
See the Register Descriptions section for a more com-
plete detail of each byte’s function, as well as for read/
write permissions for each byte.
Shadowed EEPROM
Many nonvolatile memory locations (listed within the
Register Descriptions section) are actually shadowed
EEPROM and are controlled by the SEEB bit in Table
02h, Register 80h.
The DS1876 incorporates shadowed EEPROM memory
locations for key memory addresses that can be writ-
ten many times. By default the shadowed EEPROM bit,
SEEB, is not set and these locations act as ordinary
EEPROM. By setting SEEB, these locations function
like SRAM cells, which allow an infinite number of write
cycles without concern of wearing out the EEPROM.
This also eliminates the requirement for the EEPROM
write time, tWR. Because changes made with SEEB
enabled do not affect the EEPROM, these changes are
not retained through power cycles. The power-on value
is the last value written with SEEB disabled. This func-
tion can be used to limit the number of EEPROM writes
during calibration or to change the monitor thresholds
periodically during normal operation helping to reduce
the number of times EEPROM is written. Figure 14 shows
the memory map and indicates which locations are
shadowed EEPROM.
Figure 14. Memory Map
EEPROM
(256 BYTES)
FFh
I2C ADDRESS A0hI2C ADDRESS A2h/B2h
AUXILIARY DEVICE
MAIN DEVICES AT A2h AND B2h
00h
ALARM-
ENABLE ROW
(8 BYTES)
PASSWORD ENTRY
(PWE) (4 BYTES)
TABLE-SELECT
BYTE
FFh
80h
F8h
MOD1/2
OFFSET LUT
FFh
F8h
TABLE 01h
(A2h ONLY)EEPROM
(120 BYTES)
F7h
7Fh
00h
LOWER
MEMORYFFh
80h
TABLE 02hNONLOOKUP
TABLE CONTROL
AND
CONFIGURATION
REGISTERS
(B2h ONLY CONTAINS
TRANSMITTER 2-
RELATED REGISTERS)
80h
TABLE 04hMOD1 (A2h)
MOD2 (B2h)
LOOKUP TABLE
(72 BYTES)
C7h
F8h
TABLE 05hALARM-ENABLE ROW
(8 BYTES)
ALARM-ENABLE ROW
CAN BE CONFIGURED
TO EXIST AT TABLE 01h
OR TABLE 05h USING
MASK BIT IN TABLE 02h,
REGISTER 88h.
FFh
NOTE 1: IF ASEL = 0, THEN THE MAIN DEVICE I2C SLAVE ADDRESS IS A2h/B2h.IF ASEL = 1, THEN THE MAIN DEVICE I2C SLAVE ADDRESS IS DETERMINED BY THE VALUE INTABLE 02h, REGISTER 8Bh.
NOTE 2: TABLE 00h DOES NOT EXIST.
NOTE 3: ALARM-ENABLE ROW CAN BE CONFIGURED TO EXIST AT TABLE 01h OR TABLE 05h USING THEMASK BIT IN TABLE 02h, REGISTER 88h.
(APC1/2, HBATH1/2,
TXP HI 1/2, TXP LO 1/2)
OFFSET LUTFFh
E0h
80h
TABLE 06hAPC1 (A2h)
APC2 (B2h)
LOOKUP TABLE
(72 BYTES)
C7h
SFP Controller with Dual LDD Interface
DS1876
Register Descriptions
The register maps show each byte/word (2 bytes) in
terms of its row in the memory. The first byte in the row
is located in memory at the row address (hexadecimal)
in the leftmost column. Each subsequent byte on the row
is one/two memory locations beyond the previous byte/
word’s address. A total of 8 bytes are present on each
row. For more information about each of these bytes, see
the corresponding register description.
Memory Map Access Codes
The following section provides the DS1876 register defi-
nitions. Each register or row of registers has an access
descriptor that determines the password level required
to read or write the memory. Level 2 password is
intended for the module manufacture access only. Level
1 password allows another level of protection for items
the end consumer wishes to protect. Many registers are
always readable, but require password access to write.
There are a few registers that cannot be read without
password access. The following access codes describe
each mode used by the DS1876 with factory settings for
the PW_ENA and PW_ENB (Table 02h, Registers C0h–
C1h) registers.
Memory Addresses A0h, A2h, and B2h
There are three separate I2C addresses in the DS1876:
A0h, A2h, and B2h. A2h and B2h are used to configure
and monitor two transmitters. Transmitter 1 is accessed
using A2h. Transmitter 2 is accessed using B2h. Many
of the registers in A2h and B2h are shared registers.
These registers can be read and written from both A2h
and B2h.
ACCESS CODEREAD ACCESSWRITE ACCESS
<0/_>At least 1 byte/bit in the row/byte is different than the rest of the row/byte, so look at each byte/bit
separately for permissions.
<1/_>Read allWrite PW2
<2/_>Read allWrite not applicable
<3/_>Read allWrite all, but the DS1876 hardware also writes to
these bytes/bits
<4/_>Read PW2Write PW2 + mode_bit
<5/_>Read allWrite all
<6/_>Read not applicableWrite all
<7/_>Read PW1Write PW1
<8/_>Read PW2Write PW2
<9/_>Read not applicableWrite PW2
<10/_>Read PW2Write not applicable
<11/_>Read allWrite PW1
MEMORY CODEA2h AND B2h REGISTERS
or <_/C>A common memory location is used for A2h and B2h device addresses. Reading or writing to these
locations is identical, regardless of using A2h or B2h addresses.
or <_/D>Different memory locations are used for A2h and B2h device addresses.
or <_/M>
Mixture of common and different memory locations for A2h and B2h device addresses. See the individual
bytes within the row for clarification. If “M” is used on an individual byte, see the expanded bit descriptions
to determine which bits are common vs. different.
SFP Controller with Dual LDD Interface
DS1876
Lower Memory Register Map
Table 01h Register Map
or <_/C> = Common, or <_/D> = Different, or <_/M> = Mixture of common and different.
or <_/C> = Common, or <_/D> = Different, or <_/M> = Mixture of common and different.
Note: The ALARM ENABLE bytes (Registers F8h–FFh) can be configured to exist in Table 05h instead of here at Table 01h with
the MASK bit (Table 02h, Register 88h). If the row is configured to exist in Table 05h, these location are empty in Table 01h.
The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h–C1h).
These registers also allow for custom permissions.
LOWER MEMORY
ROW
(HEX)ROW NAME
WORD 0WORD 1WORD 2WORD 3
BYTE 0/8BYTE 1/9BYTE 2/ABYTE 3/BBYTE 4/CBYTE 5/DBYTE 6/EBYTE 7/F<1/C> THRESHOLD0TEMP ALARM HITEMP ALARM LOTEMP WARN HITEMP WARN LO<1/C > THRESHOLD1VCC ALARM HIVCC ALARM LOVCC WARN HIVCC WARN LO<1/D> THRESHOLD2BMON ALARM HIBMON ALARM LOBMON WARN HIBMON WARN LO<1/D> THRESHOLD3PMON ALARM HIPMON ALARM LOPMON WARN HIPMON WARN LO
20–40<1/C > EEPROMEEEEEEEE
48–50<1/D > EEPROMEEEEEEEE<1/C > EEPROMEEEEEEEEEEEEEEEE<2/M> ADC VALUES0TEMP VALUE VCC VALUEBMON VALUEPMON VALUE<0/M> ADC VALUES1RESERVEDRESERVEDRESERVED<0/M>STATUS<3/D> UPDATE<5/D> ALARM/WARNALARM3ALARM2ALARM1RESERVEDWARN3RESERVEDRESERVEDRESERVED<0/M> TABLE SELECTRESERVEDRESERVEDRESERVED<6/C> PWE MSW<6/C> PWE LSW<5/D> TBL SEL
TABLE 01h
ROW
(HEX)ROW NAME
WORD 0WORD 1WORD 2WORD 3
BYTE 0/8BYTE 1/9BYTE 2/ABYTE 3/BBYTE 4/CBYTE 5/DBYTE 6/EBYTE 7/F
80–F7<1/C> EEPROMEEEEEEEEEEEEEEEE<7/M>ALARM ENABLEALARM EN3RESERVEDALARM EN1RESERVEDWARN EN3RESERVEDRESERVEDRESERVED
ACCESS
CODE<0/_><1/_><2/_><3/_><4/_><5/_><6/_><7/_><8/_><9/_><10/_><11/_>
Read
AccessSee each
bit/byte
separately
AllAllAllPW2AllN/APW1PW2N/APW2All
Write
AccessPW2N/A
All and
DS1876
PW2 +
mode
AllAllPW1PW2PW2N/APW1
SFP Controller with Dual LDD Interface
DS1876
Table 02h Register Map
Table 04h Register Map
or <_/C> = Common, or <_/D> = Different, or <_/M> = Mixture of common and different.
*The final result must be XORed with BB40h before writing to this register.
The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h–C1h).
These registers also allow for custom permissions.
or <_/C> = Common, or <_/D> = Different, or <_/M> = Mixture of common and different.
TABLE 02h (PW2)
ROW
(HEX)ROW NAME
WORD 0WORD 1WORD 2WORD 3
BYTE 0/8BYTE 1/9BYTE 2/ABYTE 3/BBYTE 4/CBYTE 5/DBYTE 6/EBYTE 7/F<0/C> CONFIG0<8/C>MODE<4/C>TINDEXRESERVEDRESERVEDRESERVEDRESERVED<10> DEVICE ID<10> DEVICE VER<8/C> CONFIG1CNFGACNFGBCNFGCDEVICE ADDRESSRANGING2RANGING1RSHIFT2RSHIFT1<8/C> SCALE0RESERVEDVCC SCALERESERVEDRESERVED<8/C> SCALE1BMON2 SCALEPMON2 SCALEBMON1 SCALEPMON1 SCALE<8/C> OFFSET0INTERNAL TEMP OFFSET*VCC OFFSETRESERVEDRESERVED<8/C> OFFSET1BMON2 OFFSETPMON2 OFFSETBMON1 OFFSETPMON1 OFFSET<9/C> PWD VALUEPW1 MSWPW1 LSWPW2 MSWPW2 LSW<8/C> THRESHOLDRESERVEDHBIAS2 DACHTXP2 DACLTXP2 DACRESERVEDHBIAS1 DACHTXP1 DACLTXP1 DAC<8/C> PWD ENABLEPW_ENAPW_ENBRESERVEDRESERVEDRESERVEDRESERVEDPOLARITYTBLSELPON<4/C> DAC VALUESMOD2 DACAPC2 DACMOD1 DACAPC1 DAC
D0–FFEMPTYEMPTYEMPTYEMPTYEMPTYEMPTYEMPTYEMPTYEMPTY
TABLE 04h (MODULATION LUT)
ROW
(HEX)ROW NAME
WORD 0WORD 1WORD 2WORD 3
BYTE 0/8BYTE 1/9BYTE 2/ABYTE 3/BBYTE 4/CBYTE 5/DBYTE 6/EBYTE 7/F
80–C7<8/D> LUT4MODMODMODMODMODMODMODMOD
C8–F7EMPTYEMPTYEMPTYEMPTYEMPTYEMPTYEMPTYEMPTYEMPTY<8/D> MOD OFFSETMOD OFFSET
LUT
MOD OFFSET
LUT
MOD OFFSET
LUT
MOD OFFSET
LUT
MOD OFFSET
LUT
MOD OFFSET
LUT
MOD OFFSET
LUT
MOD OFFSET
LUT
ACCESS
CODE<0/_><1/_><2/_><3/_><4/_><5/_><6/_><7/_><8/_><9/_><10/_><11/_>
Read
AccessSee each
bit/byte
separately
AllAllAllPW2AllN/APW1PW2N/APW2All
Write
AccessPW2N/A
All and
DS1876
PW2 +
mode
AllAllPW1PW2PW2N/APW1
SFP Controller with Dual LDD Interface
DS1876
Table 05h Register Map
Table 06h Register Map
or <_/C> = Common, or <_/D> = Different, or <_/M> = Mixture of common and different.
Note: Table 05h is empty by default. It can be configured to contain the alarm and warning enable bytes from Table 01h,
Registers F8h–FFh with the MASK bit enabled (Table 02h, Register 88h). In this case Table 01h is empty.
Auxiliary Memory A0h Register Map
or <_/C> = Common, or <_/D> = Different, or <_/M> = Mixture of common and different.
The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h–C1h).
These registers also allow for custom permissions.
or <_/C> = Common, or <_/D> = Different, or <_/M> = Mixture of common and different.
TABLE 05h
ROW
(HEX)ROW NAME
WORD 0WORD 1WORD 2WORD 3
BYTE 0/8BYTE 1/9BYTE 2/ABYTE 3/BBYTE 4/CBYTE 5/DBYTE 6/EBYTE 7/F
80–F7EMPTYEMPTYEMPTYEMPTYEMPTYEMPTYEMPTYEMPTYEMPTY<7/M> ALARM ENABLEALARM EN3RESERVEDALARM EN1RESERVEDWARN EN3RESERVEDRESERVEDRESERVED
TABLE 06h (APC LUT)
ROW
(HEX)ROW NAME
WORD 0WORD 1WORD 2WORD 3
BYTE 0/8BYTE 1/9BYTE 2/ABYTE 3/BBYTE 4/CBYTE 5/DBYTE 6/EBYTE 7/F
80–C7<8/D> LUT6APC LUTAPC LUTAPC LUTAPC LUTAPC LUTAPC LUTAPC LUTAPC LUT
C8–DFEMPTYEMPTYEMPTYEMPTYEMPTYEMPTYEMPTYEMPTYEMPTY<8/D> HBATHHBATH LUTHBATH LUTHBATH LUTHBATH LUTHBATH LUTHBATH LUTHBATH LUTHBATH LUT<8/D> HTXPHTXP LUTHTXP LUTHTXP LUTHTXP LUTHTXP LUTHTXP LUTHTXP LUTHTXP LUT<8/D> LTXPLTXP LUTLTXP LUTLTXP LUTLTXP LUTLTXP LUTLTXP LUTLTXP LUTLTXP LUT<8/D> APC OFFSETAPC OFFSET
LUT
APC OFFSET
LUT
APC OFFSET
LUT
APC OFFSET
LUT
APC OFFSET
LUT
APC OFFSET
LUT
APC OFFSET
LUT
APC OFFSET
LUT
AUXILIARY MEMORY (A0h)
ROW
(HEX)ROW NAME
WORD 0WORD 1WORD 2WORD 3
BYTE 0/8BYTE 1/9BYTE 2/ABYTE 3/BBYTE 4/CBYTE 5/DBYTE 6/EBYTE 7/F
00–7F<5> AUX EEEEEEEEEEEEEEEEEE
80–FF<5> AUX EEEEEEEEEEEEEEEEEE
ACCESS
CODE<0/_><1/_><2/_><3/_><4/_><5/_><6/_><7/_><8/_><9/_><10/_><11/_>
Read
AccessSee each
bit/byte
separately
AllAllAllPW2AllN/APW1PW2N/APW2All
Write
AccessPW2N/A
All and
DS1876
PW2 +
mode
AllAllPW1PW2PW2N/APW1
SFP Controller with Dual LDD Interface
DS1876
Lower Memory Register Descriptions
Lower Memory, Register 00h–01h: TEMP ALARM HI
Lower Memory, Register 04h–05h: TEMP WARN HI
Lower Memory, Register 02h–03h: TEMP ALARM LO
Lower Memory, Register 06h–07h: TEMP WARN LO
FACTORY DEFAULT 7FFFh
READ ACCESSAll
WRITE ACCESSPW2 or (PW1 and WLOWER)
A2h AND B2h MEMORYCommon A2h and B2h memory location
MEMORY TYPENonvolatile (SEE)
00h, 04hS26252423222120
01h, 05h2-12-22-32-42-52-62-72-8
BIT 7BIT 0
Temperature measurement updates above this two’s complement threshold set its corresponding alarm or
warning bit. Temperature measurement updates equal to or below this threshold clear its alarm or warning bit.
FACTORY DEFAULT 8000h
READ ACCESSAll
WRITE ACCESSPW2 or (PW1 and WLOWER)
A2h AND B2h MEMORYCommon A2h and B2h memory location
MEMORY TYPENonvolatile (SEE)
02h, 06hS26252423222120
03h, 07h2-12-22-32-42-52-62-72-8
BIT 7BIT 0
Temperature measurement updates below this two’s complement threshold set its corresponding alarm or
warning bit. Temperature measurement updates equal to or above this threshold clear its alarm or warning bit.
SFP Controller with Dual LDD Interface
DS1876
Lower Memory, Register 08h–09h: VCC ALARM HI
Lower Memory, Register 0Ch–0Dh: VCC WARN HI
Lower Memory, Register 0Ah–0Bh: VCC ALARM LO
Lower Memory, Register 0Eh–0Fh: VCC WARN LO
FACTORY DEFAULT FFFFh
READ ACCESSAll
WRITE ACCESSPW2 or (PW1 and WLOWER)
A2h AND B2h MEMORYCommon A2h and B2h memory location
MEMORY TYPENonvolatile (SEE)
08h, 0Ch2152142132122112102928
09h, 0Dh 2726252423222120
BIT 7BIT 0
Voltage measurement updates above this unsigned threshold set its corresponding alarm or warning bit.
Voltage measurements equal to or below this threshold clear its alarm or warning bit.
FACTORY DEFAULT 0000h
READ ACCESSAll
WRITE ACCESSPW2 or (PW1 and WLOWER)
A2h AND B2h MEMORYCommon A2h and B2h memory location
MEMORY TYPENonvolatile (SEE)
0Ah, 0Eh2152142132122112102928
0Bh, 0Fh2726252423222120
BIT 7BIT 0
Voltage measurement updates below this unsigned threshold set its corresponding alarm or warning bit. Voltage
measurements equal to or above this threshold clear its alarm or warning bit.
SFP Controller with Dual LDD Interface
DS1876
Lower Memory, Register 10h–11h: BMON ALARM HI
Lower Memory, Register 14h–15h: BMON WARN HI
Lower Memory, Register 18h–19h: PMON ALARM HI
Lower Memory, Register 1Ch–1Dh: PMON WARN HI
Lower Memory, Register 12h–13h: BMON ALARM LO
Lower Memory, Register 16h–17h: BMON WARN LO
Lower Memory, Register 1Ah–1Bh: PMON ALARM LO
Lower Memory, Register 1Eh–1Fh: PMON WARN LO
FACTORY DEFAULT FFFFh
READ ACCESSAll
WRITE ACCESSPW2 or (PW1 and WLOWER)
A2h AND B2h MEMORYDifferent A2h and B2h memory locations
MEMORY TYPENonvolatile (SEE)
10h, 14h,
18h, 1Ch2152142132122112102928
11h, 15h,
19h, 1Dh2726252423222120
BIT 7BIT 0
Voltage measurement updates above this unsigned threshold set its corresponding alarm or warning bit.
Voltage measurements equal to or below this threshold clear its alarm or warning bit.
FACTORY DEFAULT 0000h
READ ACCESSAll
WRITE ACCESSPW2 or (PW1 and WLOWER)
A2h AND B2h MEMORYDifferent A2h and B2h memory locations
MEMORY TYPENonvolatile (SEE)
12h, 16h,
1Ah, 1Eh2152142132122112102928
13h, 17h,
1Bh, 1Fh2726252423222120
BIT 7BIT 0
Voltage measurement updates below this unsigned threshold set its corresponding alarm or warning bit. Voltage
measurements equal to or above this threshold clear its alarm or warning bit.
SFP Controller with Dual LDD Interface
DS1876
Lower Memory, Register 20h–47h: EE
Lower Memory, Register 48h–57h: EE
Lower Memory, Register 58h–5Fh: EE
FACTORY DEFAULT 00h
READ ACCESSAll
WRITE ACCESSPW2 or (PW1 and WLOWER)
A2h AND B2h MEMORYCommon A2h and B2h memory location
MEMORY TYPENonvolatile (EE)
20h–47hEEEEEEEEEEEEEEEE
BIT 7BIT 0
PW2 level access-controlled EEPROM.
FACTORY DEFAULT 00h
READ ACCESSAll
WRITE ACCESSPW2 or (PW1 and WLOWER)
A2h AND B2h MEMORYDifferent A2h and B2h memory locations
MEMORY TYPENonvolatile (EE)
48h–57hEEEEEEEEEEEEEEEE
BIT 7BIT 0
PW2 level access-controlled EEPROM.
FACTORY DEFAULT 00h
READ ACCESSAll
WRITE ACCESSPW2 or (PW1 and WLOWER)
A2h AND B2h MEMORYCommon A2h and B2h memory location
MEMORY TYPENonvolatile (EE)
58h–5FhEEEEEEEEEEEEEEEE
BIT 7BIT 0
PW2 level access-controlled EEPROM.
SFP Controller with Dual LDD Interface
DS1876
Lower Memory, Register 60h–61h: TEMP VALUE
Lower Memory, Register 62h–63h: VCC VALUE
FACTORY DEFAULT 0000h
READ ACCESSAll
WRITE ACCESSN/A
A2h AND B2h MEMORYCommon A2h and B2h memory location
MEMORY TYPEVolatile
60hS26252423222120
61h2-12-22-32-42-52-62-72-8
BIT 7BIT 0
Signed two’s complement direct-to-temperature measurement.
POWER-ON VALUE0000h
READ ACCESSAll
WRITE ACCESSN/A
A2h AND B2h MEMORYCommon A2h and B2h memory location
MEMORY TYPEVolatile
62h2152142132122112102928
63h2726252423222120
BIT 7BIT 0
Left-justified unsigned voltage measurement.
SFP Controller with Dual LDD Interface
DS1876
Lower Memory, Register 64h–65h: BMON VALUE
Lower Memory, Register 66h–67h: PMON VALUE
Lower Memory, Register 68h–6Dh: RESERVED
POWER-ON VALUE0000h
READ ACCESSAll
WRITE ACCESSN/A
A2h AND B2h MEMORYDifferent A2h and B2h memory locations
MEMORY TYPEVolatile
64h, 66h2152142132122112102928
65h, 67h2726252423222120
BIT 7BIT 0
Left-justified unsigned voltage measurement.
POWER-ON VALUE
READ ACCESSN/A
WRITE ACCESSN/A
A2h AND B2h MEMORYN/A
MEMORY TYPEN/A
68h, 6Dh00000000
BIT 7BIT 0
These registers are reserved. The value when read is 00h.
SFP Controller with Dual LDD Interface
DS1876
Lower Memory, Register 6Eh: STATUS
POWER-ON VALUEX0XX 0XXXb
READ ACCESSAll
WRITE ACCESSSee below
A2h AND B2h MEMORYMixture of common memory locations and different memory locations (see below)
MEMORY TYPEVolatile
Write AccessN/AAllN/AAllAllN/AN/AN/A
6EhTXDSTXDCIN1SRSELSRSELCTXFSRAMRDYB
BIT 7BIT 0
BIT 7
TXDS1 [A2h]: TXD1 status bit. Reflects the logic state of the TXD1 pin (read-only).
0 = TXD1 pin is logic-low.
1 = TXD1 pin is logic-high.
TXDS2 [B2h]: TXD2 status bit. Reflects the logic state of the TXD2 pin (read-only).
0 = TXD2 pin is logic-low.
1 = TXD2 pin is logic-high.
BIT 6
TXDC1 [A2h]: TXD1 software control bit. This bit allows for software control that is identical to the
TXD1 pin. See the DACs as a Function of Transmit Disable (TXD1, TXD2) section for further infor-
mation. Its value is wire-ORed with the logic value of the TXD1 pin (writable by all users).
0 = (default)
1 = Forces the device into a TXD1 state regardless of the value of the TXD1 pin.
TXDC2 [B2h]: TXD2 software control bit. This bit allows for software control that is identical to the
TXD2 pin. See the DACs as a Function of Transmit Disable (TXD1, TXD2) section for further infor-
mation. Its value is wire-ORed with the logic value of the TXD2 pin (writable by all users).
0 = (default)
1 = Forces the device into a TXD2 state regardless of the value of the TXD2 pin.
BIT 5
IN1S [A2h or B2h]: IN1 status bit. Reflects the logic state of the IN1 pin (read-only).
0 = IN1 pin is logic-low.
1 = IN1 pin is logic-high.
BIT 4
RSELS [A2h or B2h]: RSEL status bit. Reflects the logic state of the RSEL pin (read-only).
0 = RSEL pin is logic-low.
1 = RSEL pin is logic-high.
BIT 3
RSELC [A2h or B2h]: RSEL software control bit. This bit allows for software control that is iden-
tical to the RSEL pin. Its value is wire-ORed with the logic value of the RSEL pin to create the
RSELOUT pin’s logic value (writable by all users).
0 = (default)
1 = Forces the device into a RSEL state regardless of the value of the RSEL pin.
BIT 2
TXFS1 [A2h]: Reflects state of the TXF1 pin (read-only).
0 = TXF1 pin is low.
1 = TXF1 pin is high.
TXFS2 [B2h]: Reflects the state of the TXF2 pin (read-only).
0 = TXF2 pin is low.
1 = TXF2 pin is high.
BIT 1RAM1 [A2h]: Volatile memory location.
RAM2 [B2h]: Volatile memory location.
RDYB [A2h or B2h]: Ready bar.
SFP Controller with Dual LDD Interface
DS1876
Lower Memory, Register 6Fh: UPDATE
POWER-ON VALUE00h
READ ACCESSAll
WRITE ACCESSAll and DS1876 hardware
A2h AND B2h MEMORYDifferent A2h and B2h memory locations
MEMORY TYPEVolatile
6FhTEMP
RDYVCC RDYBMON
RDY
PMON
RDYRESERVEDRESERVEDRESERVEDRESERVED
BIT 7BIT 0
BITS 7:4
TEMP RDY, VCC RDY, BMON RDY, PMON RDY: Update of completed conversions. At power-on,
these bits are cleared and are set as each conversion is completed. These bits can be cleared so
that a completion of a new conversion is verified.
BITS 3:0RESERVED
