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DS1870
LDMOS RF Power-Amplifier Bias Controller
General DescriptionThe DS1870 is a dual-channel bias controller targeted
toward class AB LDMOS RF power-amplifier applica-
tions. It uses lookup tables (LUTs) to control 256-posi-
tion potentiometers based on the amplifier’s
temperature and drain voltage or current (or other
external monitored signal). With its internal temperature
sensor and multichannel A/D converter (ADC), the
DS1870 provides a cost-effective solution that improves
the amplifier’s efficiency by using nonlinear compensa-
tion schemes that are not possible with conventional
biasing solutions.
ApplicationsCellular Base Stations
Medical Equipment
Industrial Controls
Optical Transceivers
FeaturesTwo-Channel Solution for Programmable RF Bias
ControlThe Potentiometer’s Position is Automatically
Updated to Compensate for the Ambient
Temperature and the Drain Voltage or CurrentA Five-Channel, 13-Bit ADC Continuously
Monitors the Ambient Temperature, VCC, VD, ID1,
and ID2Hi/Lo Alarms for Each ADC Channel can Trigger a
Fault OutputNonvolatile Memory for the Device Settings,
Lookup Tables, and 32-Bytes of User MemoryI2C-Compatible Serial Interface with Up to Eight
Devices on the Same Serial BusSingle 5V Power SupplySmall 16-Pin TSSOP Package-40°C to +95°C Operational Temperature Range
DS1870
LDMOS RF Power-Amplifier Bias
Controller
TSSOP (173 mils)L1
TOP VIEW
ID1
ID2
GNDFAULT
SCL
SDA
HCOM
VCC
DS1870
Pin Configuration
Ordering InformationRev 2; 2/06
EVALUATION KIT
AVAILABLE
PARTTEMP RANGEPIN-PACKAGEDS1870E-010-40°C to +95°C 16 TSSOP
(173 mils)
DS1870E-010+-40°C to +95°C 16 TSSOP
(173 mils)
+Denotes lead-free package.
Typical Operating Circuit appears at end of data sheet.
DS1870
LDMOS RF Power-Amplifier Bias
Controller
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING CONDITIONS(TA= -40°C to +95°C)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on VCC, HCOM, SDA, and SCL Pins Relative to
Ground...............................................................-0.5V to +6.0V
Voltage Range on A0, A1, A2, FAULT, VD, ID1, ID2Relative to
Ground....................-0.5V to VCC+ 0.5V, not to exceed +6.0V
Voltage Range on L0, L1, W0, and W1 Relative to
Ground.................-0.5V to HCOM+ 0.5V, not to exceed +6.0V
Operating Temperature Range...........................-40°C to +95°C
EEPROM Programming Temperature Range.........0°C to +70°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature.......................................See IPC/JEDEC
J-STD-020A Specification
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSupply VoltageVCC(Note 1)4.55.5V
Input Logic 1
(SDA, SCL, A2, A1, A0)VIH0.7 x
VCC
VCC +
0.3V
Input Logic 0
(SDA, SCL, A2, A1, A0)VIL-0.3+0.3 x
VCCV
HCOM Voltage4.55.5V
LX and WX Voltage-0.3HCOM
+ 0.3V
Wiper Current-1+1mA
DC ELECTRICAL CHARACTERISTICS(VCC= +4.5 to 5.5V, TA= -40°C to +95°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSupply CurrentICC(Note 2)12mA
Input LeakageILI-200+200nA
VOL13mA sink current0.4VLow-Level Output Voltage
(SDA, FAULT)VOL26mA sink current0.6V
I/O CapacitanceCI/O10pF
Digital Power-On ResetVPOD1.02.2V
Analog Power-On ResetVPOA2.02.8V
DS1870
LDMOS RF Power-Amplifier Bias
Controller
ANALOG VOLTAGE-MONITORING CHARACTERISTICS(VCC= +4.5 to 5.5V, TA = -40°C to +95°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSVD Monitor Factory-
Calibrated FSCode FFF8h2.4882.5002.513V
VCC Monitor Factory-
Calibrated FSCode FFF8h6.5216.5536.587V
ID1 and ID2 Monitor Factory-
Calibrated FSCode FFF8h0.49750.50000.5025V
Resolution
(VCC, VD, ID1, ID2)0.0122%FS
Accuracy
(VCC, VD, ID1, ID2)0.250.5%FS
Update Rate for
VCC, VD, ID1, ID2tframe50ms
DIGITAL THERMOMETER CHARACTERISTICS(VCC= +4.5 to 5.5V, TA= -40°C to +95°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSThermometer ErrorTERR-40°C to 95°C-3+3°C
Update Ratetframe50ms
ANALOG POTENTIOMETER CHARACTERISTICS(VCC= +4.5 to 5.5V, TA= -40°C to +95°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSWiper Resistance+25°C5001000Ω
Potentiometer
End-to-End ResistanceRPOT+25°C10.01316.8kΩ
Resolution0.4%FS
Absolute Linearity(Note 3)-1+1LSB
Relative Linearity(Note 4)-0.5+0.5LSB
Ratiometric Temperature
Coefficient5ppm/°C
End-to-End Temperature
Coefficient70ppm/°C
-3dB Cutoff Frequency(Note 5)1MHz
Series Resistors from L1, L2 to
GNDRS+25°C15.119.525.2kΩ
VHCOM/VLX0.59750.60.6025
DS1870
LDMOS RF Power-Amplifier Bias
Controller
LOOKUP TABLE CHARACTERISTICS(VCC= +4.5 to 5.5V, TA= -40°C to +95°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSPOT1 and POT2 Temp LUT Size72Bytes
each
POT1 and POT2 Temp LUT Index
Range-40+102°C
Temp Step2°C
Temp Hysteresis(Note 6)1°C
POT1 and POT2 Drain LUT Size64Bytes
each
POT1 and POT2 Drain LUT VD
Index Range8000FE00Hex
POT1 and POT2 Drain LUT VD
Step0200Hex
POT1 and POT2 Drain LUT VD
Hysteresis(Note 6)0100Hex
POT1 and POT2 Drain LUT IDX
Index Range00007E00Hex
POT1 and POT2 Drain LUT IDX
Step0200Hex
POT1 and POT2 Drain LUT IDX
Hysteresis(Note 6)0100Hex
DS1870
LDMOS RF Power-Amplifier Bias
Controller
AC ELECTRICAL CHARACTERISTICS (VCC= +4.5V to 5.5V, TA= -40°C to +95°C, timing referenced to VIL(MAX)and VIH(MIN).) (Figure 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSCL Clock FrequencyfSCL(Note 7)0400kHz
Bus Free Time Between Stop and
Start ConditionstBUF1.3µs
Hold Time (Repeated) Start
ConditiontHD:STA0.6µs
Low Period of SCLtLOW1.3µs
High Period of SCLtHIGH0.6µs
Data Hold TimetHD:DAT00.9µs
Data Setup TimetSU:DAT100ns
Start Setup TimetSU:STA0.6µs
SDA and SCL Rise TimetR(Note 8)20 +
0.1CB300ns
SDA and SCL Fall TimetF(Note 8)20 +
0.1CB300ns
Stop Setup TimetSU:STO0.6µs
SDA and SCL Capacitive
LoadingCB(Note 8)400pF
EEPROM Write TimetW(Note 9)1020ms
NONVOLATILE MEMORY CHARACTERISTICS(VCC= +4.5V to 5.5V, TA= 0°C to +70°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSWrites+70°C (Note 5)50,000
Note 1:All voltages referenced to ground.
Note 2:Supply current is measured with all logic inputs at their inactive state (SDA = SCL = VCC) and driven to well-defined logic
levels. All outputs are disconnected.
Note 3:Absolute linearity is the difference of measured value from expected value at the DAC position. Expected value is a
straight line from measured minimum position to measured maximum position.
Note 4:Relative linearity is the deviation of an LSB DAC setting change vs. the expected LSB change. Expected LSB change is
the slope of the straight line from measured minimum position to measured maximum position.
Note 5:This parameter is guaranteed by design.
Note 6:See Figure 1.
Note 7:I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C stan-
dard-mode timing.
Note 8:CB—total capacitance of one bus line in picofarads.
Note 9:EEPROM write begins after a stop condition occurs.
DS1870
LDMOS RF Power-Amplifier Bias
Controller
Typical Operating Characteristics(VCC= +5.0V, TA = +25°C, unless otherwise noted.)
POTENTIOMETER 1 AND 2 OUTPUT VOLTAGE
vs. POSITONDS1870 toc04
WIPER POSITION (DEC)
WIPER VOLTAGE (V)
HCOM = 5V
L1 AND L2
NOT CONNECTED
POTENTIOMETER 1 DIFFERENTIAL
NONLINEARITY vs. WIPER POSITIONDS1870 toc05
WIPER POSITION (DEC)
DIFFERENTIAL NONLINEARITY (LSB)
POTENTIOMETER 2 DIFFERENTIAL
NONLINEARITY vs. WIPER POSITION
DS1870 toc06
WIPER POSITION (DEC)
DIFFERENTIAL NONLINEARITY (LSB)
POTENTIOMETER 1 INTEGRAL
NONLINEARITY vs. WIPER POSITION
DS1870 toc07
WIPER POSITION (DEC)
INTEGRAL NONLINEARITY (LSB)
POTENTIOMETER 2 INTEGRAL
NONLINEARITY vs. WIPER POSITION
DS1870 toc08
WIPER POSITION (DEC)
INTEGRAL NONLINEARITY (LSB)
POTENTIOMETER 1 AND 2
WIPER RESISTANCE vs. WIPER VOLTAGE
DS1870 toc09
WIPER VOLTAGE (V)
WIPER RESISTANCE (321
HCOM = 5.0V
SUPPLY CURRENT vs. SUPPLY VOLTAGEDS1870 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (
SUPPLY CURRENT vs. TEMPERATURE
DS1870 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (6020400-20
VCC = 5.5V
VCC = 4.5V
VCC = 5.0V
HCOM CURRENT vs. HCOM VOLTAGEDS1870 toc03
HCOM VOLTAGE (V)
COM
CURRENT (mA)
4.55.5
DS1870
LDMOS RF Power-Amplifier Bias
Controllerypical Operating Characteristics (continued)(VCC= +5.0V, TA = +25°C, unless otherwise noted.)
OUTPUT DRIFT (PPM/C)
POTENTIOMETER LOW TERMINAL VOLTAGE
vs. TEMPERATURE
DS1870 toc12
TEMPERATURE (°C)60-2002040-40100
HCOM = 5.0V
VCC CONVERSION ERROR
vs. SUPPLY VOLTAGEDS1870 toc13
SUPPLY VOLTAGE (V)
ERROR (% FS)
DEFAULT VCC
CALIBRATION
VD CONVERSION ERROR
vs. INPUT VOLTAGEDS1870 toc14
INPUT VOLTAGE (V)
ERROR (% FS)
DEFAULT VD
CALIBRATION
ID1 CONVERSION ERROR
vs. INPUT VOLTAGEDS1870 toc15
INPUT VOLTAGE (V)
ERROR (% FS)
DEFAULT ID1
CALIBRATION
ID2 CONVERSION ERROR
vs. INPUT VOLTAGEDS1870 toc16
INPUT VOLTAGE (V)
ERROR (% FS)
DEFAULT ID2
CALIBRATION
POTENTIOMETER 1 AND 2
WIPER RESISTANCE vs. WIPER VOLTAGEDS1870 toc09
WIPER VOLTAGE (V)
WIPER RESISTANCE (321
HCOM = 5.0V
POTENTIOMETER 1 AND 2
WIPER RESISTANCE vs. TEMPERATUREDS1870 toc10
TEMPERATURE (°C)
RESISTANCE CHANGE FROM 25
C (PPM/C)6020400-20
HCOM = 5V
WIPER VOLTAGE = 4V
POTENTIOMETER END-TO-END RESISTANCE
vs. TEMPERATUREDS1870 toc11
TEMPERATURE (°C)
CHANGE FROM RESISTANCE AT 25
C (PPM/C)60-2002040
RPOT2 + RS2
RPOT1 + RS1
DS1870
LDMOS RF Power-Amplifier Bias
Controller
Pin Description
PINNAMEFUNCTION1L1Potentiometer 1 Low Terminal
2W1Potentiometer 1 Wiper Terminal
3W2Potentiometer 2 Wiper Terminal
4L2Potentiometer 2 Low Terminal
5ID1Drain Current 1 Monitor Input
6ID2Drain Current 2 Monitor Input
7VDDrain Voltage Monitor InputGNDGroundFAULTFault Output. This open-collector output is active high when one of the enabled alarms is outside its
programmable limit value.A0A1A22C Address Inputs. These inputs determine the slave address of the device. The slave address in
binary is 1010A2A1A0.SCLSerial Clock Input. I2C clock input.SDASerial Data Input/Output. Bidirectional I2C data pin.HCOMPotentiometer High Terminal. Common to potentiometers 1 and 2.VCCPower Input
DS1870
LDMOS RF Power-Amplifier Bias
Controller
Functional Diagram+++
13-BIT
ADC
ON-CHIP
TEMP SENSOR
VCC
ID1
ID2
ADDRESS
GENERATION
SDA
SCL2C DATA BUS
32 BYTES
USER
MEMORYOFFSET
CALIBRATION
REGISTERS
FAULT
LOAD
INDEX
INDEXINDEX
INDEX
LOAD
TEMP
POT1
RPOT
POT2
RPOT
HCOM
POT1
DRAIN
LUT
TABLE 4
(64 BYTES)
POT2
DRAIN
LUT
TABLE 5
(64 BYTES)LIMIT
COMPARATOR
LIMIT FLAG
REGISTERS
FAULT
MASK
VCC
VCC
GND
GAIN
CALIBRATION
REGISTERS
VD1VD2ID2ID1
POT1
TEMP
LUT
TABLE 2
(72 BYTES)
POT2
TEMP
LUT
TABLE 3
(72 BYTES)
I2C INTERFACE
CONTROL
HI AND LO
LIMITS FOR
TEMP, VCC,
VD, ID1, ID2
MEASURED
VALUES FOR
TEMP, VCC,
VD, ID0, ID1
DS1870
DS1870
LDMOS RF Power-Amplifier Bias
Controller
Detailed DescriptionThe DS1870 is a dual-channel LDMOS bias controller.
It is intended to replace traditional bias control solu-
tions that are limited by a constant temperature-coeffi-
cient correction. This IC offers lookup tablecorrection
that is programmable as a function of temperature as
well as drain supply voltage or current. The flexibility to
use a nonlinear bias correction improves efficiency sig-
nificantly. This is a direct consequence of the ability to
lower the bias current, particularly in class AB opera-
tion, since the bias correction no longer requires a con-
stant temperature coefficient. In addition, correcting the
bias as a function of drain supply voltage, or drain cur-
rent in class AB, assists in distortion reduction and gain
management.
Two outputs (W1 and W2), each controlled by a dedi-
cated two-dimensional lookup tableas shown in the
functional diagram, drive two LDMOS gates. The two
degrees of freedom are temperature and either drain
supply voltage or drain current. The lookup tables are
programmed during power-amplifier assembly and
test. After calibration, the IC automatically recalls the
proper control setting for each output, based on tem-
perature and drain characteristics.
A 13-bit ADC samples and digitizes the chip tempera-
ture, VCC, the drain supply voltage, and two drain cur-
rents. These digitized signals are stored in memory
ready to be accessed by the look up tablecontrols.
The digitized values are also compared to alarm
thresholds generating high or low alarm flags. The
FAULT output can be configured to assert high based
any alarm’s assertion, or the alarms can be masked to
prevent unwanted fault assertions. The ADC readings
as well as the alarm flags and fault status are accessi-
ble through the I2C-compatible interface.
Voltage/Current Monitor OperationThe DS1870 monitors four voltages (VCC, VD, ID1, and
ID2) plus the temperature in a round-robin fashion using
its 13-bit ADC. The converted voltage values are stored
in memory addresses 62h–69h as 16-bit unsigned
The three least significant bits of the ADC result registers
are masked to zero. The round-robin time is specified by
tframein the analog voltage-monitoring characteristics.
The default factory-calibrated values for the voltage
monitors are shown in Table1.
To calculate the voltage measured from the register
value, first calculate the LSB weight of the 16-bit regis-
ter that is equal to the full-scale voltage span divided
by 65,528. Next, convert the hexadecimal register
value to decimal and multiply it times the LSB weight.
Example: Using the factory default VCCtrim, what volt-
age is measured if the VCCregister value is C347h
The LSB for VCCis equal to (6.553V - 0V) / 65,528 =
100.00µV. C347h is equal to 49,991 decimal, which
yields a supply voltage equal to 49,991x100.00µV =
4.999V. Table2 shows more conversion examples
based on the factory trimmed ADC settings.
By using the internal gain and offset calibration regis-
ters, the +FS and -FS signal values shown in Table1
can be modified to meet customer needs. For more
information on calibration, see the Voltage-Monitor
Calibrationsection.
Note:The method shown above for determining the
input voltage level only works when the offset register is
set to zero.
SIGNAL+FS SIGNAL+FS
(hex)
-FS
SIGNAL
-FS
(hex)VCC6.553VFFF80V00002.5VFFF80V0000
ID10.5VFFF80V0000
ID20.5VFFF80V0000
Table1. Voltage-Monitor Factory DefaultCalibration
SIGNALLSB
WEIGHT (µV)
REGISTER
VALUE (hex)
INPUT
VOLTAGE (V)VCC100.0080803.29
VCC100.00C0F84.9438.152C0001.87538.15280801.255
ID17.630380000.2500
ID27.630313280.0374
Table2. Voltage-Monitor ConversionExamples
DS1870
LDMOS RF Power-Amplifier Bias
Controller
Temperature-Monitor OperationThe internal temperature monitor values are stored as
16-bit 2’s complement numbers at memory addresses
60h to 61h. The round-robin update time (tframe) for the
temperature register is the same as the voltage moni-
tors. The factory default calibration values for the tem-
perature monitor are shown in Table3.
To convert the 2’s complement register value to the
temperature it represents, first convert the 2-byte hexa-
decimal value to a decimal value as if it is an unsigned
value, then divide the result by 256. Finally, subtract
256 if the result of the division is greater than or equal
to +128. Table 4 shows example converted values.
The offset of the temperature sensor can be adjusted
using the internal calibration registers to account for
differences between the ambient temperature at the
location of the DS1870 and the temperature of the
device it is biasing. When offsets are applied to the
temperature measurement, the value converted will be
off by a fixed value from the DS1870’s ambient temper-
ature. For more information, see the Temperature
Monitor Offset Calibrationsection.
Potentiometer OperationBoth of the DS1870’s potentiometers are 256 positions
with their high terminals connected to the high common
pin, HCOM. The low terminals of the potentiometers are
internally shunted to GND by resistors such that the
output voltage is 3V to 5V when HCOMis connected to
a 5V source. The internal shunt resistors and the poten-
tiometer’s end-to-end resistance feature matching tem-
perature coefficients that prevent the output voltage
from drifting over temperature.
External resistors can be placed from HCOMto LXand/or
from LXto GND to modify the typical output voltage.
Normal OperationDuring normal operation, each potentiometer’s position
is automatically adjusted to the sum of its temperature
and drain LUT values after each round of conversions.
The potentiometer setting is applied after both the base
and offset LUT values are recalled from memory. The
sum of the currently indexed values in the POT1 Temp
LUT (memory table2) and the POT1 Drain LUT (memo-
ry table4) control potentiometer 1. The sum of the cur-
rently indexed values in the POT2 Temp LUT (memory
table3) and the POT2 Drain LUT (memory table5) con-
trol potentiometer 2. In the event that two tablevalues
are summed and the result is greater than 255 or less
than 0, the potentiometer’s position is set to 255 or 0,
respectively.
SIGNAL+FS
SIGNAL
+FS
(hex)
-FS
SIGNAL
-FS
(hex)Temp+127.97°C7FF8-128.00°C8000
Table3. Internal Temperature-MonitorFactory Default Calibration
MSB
(bin)
LSB
(bin)
TEMPERATURE
(°C)0100000000000000+64
0100000000001111+64.059
0101111100000000+95
Table4. Temperature Conversion Values
LUT ADDRESS (hex)CORRESPONDING
TEMPERATURE (°C)≤ -40°C-38°C-36°C+100°C≥ +102°C
Table5. LUT Addresses forCorresponding Temperature Values
DS1870
LDMOS RF Power-Amplifier Bias
ControllerThe temperature tables (LUT 2 and LUT 3) are 72 bytes
each. This allows the biasing to be adjusted every 2°C
between -40°C and +102°C. Temperatures less than
-40°C or greater than +102°C use the -40°C or +102°C
values, respectively. The values in the temperature
tables are 8-bit unsigned values (0 to 255 decimal) that
allow the potentiometer to be set to any position as a
function of the temperature. The temperature LUTs
have 1°C hysteresis (Figure1) to prevent the poten-
tiometer’s position from chattering in the event the tem-
perature remains near a LUT switching point. Table5
shows how the DS1870 determines the temperature
tables index as a function of temperature.
The drain tables (LUT 4 and LUT5) are 64 bytes each,
and they can be indexed either by the drain voltage or
the drain current corresponding to the potentiometer.
The VD1 control bit determines if the voltage sensed onor ID1adjusts the POT1 Drain LUT, and the VD2
control bit determines if the voltage sensed on VDor
ID2controls the POT2 Drain LUT. The VD1 and VD2
control bits are located in register 85h of memory table
1. The drain tables are programmed with an 8-bit
signed value (-128 to +127 decimal) that allow a rela-
tive offset from the temperature LUT values determined
by the amplifier’s drain characteristics.
The drain LUTs are indexed either by the upper half of
the VDrange or the lower half of its corresponding IDX
range. Table6 shows how the index is determined
based on the VDor IDXvalues. Hysteresis equal to
0100h is also implemented on the drain monitor
(Figure1) to ensure that voltages close to a switching
point do not cause the potentiometer position to chatter
between two LUT values. The drain LUT index values are
specified in hexadecimal because the hexadecimal val-
ues are applicable regardless of the gain and offset cali-
bration of the DS1870.
Manual ModeDuring normal operation, the potentiometer position is
automatically modified once per conversion cycle
based on the ADC results. The DS1870 can either stop
the update function all together by using the B/O_en
bit, or the temperature and drain LUT indexes can be
manually controlled by using the Index_en bit. These
bits are located in the Man DAC register located in
memory table1, byte AFh. More information about
these bits is in the Register Descriptionsection.
Voltage-Monitor CalibrationThe DS1870 can scale each analog voltage’s gain and
offset to produce the desired digital result. Each of the
inputs (VCC, VD, ID1, ID2) has a unique register for the
gain and offset (in memory table1) allowing them to be
individually calibrated. Additionally, the DS1870 offers
the ability to provide a temperature offset to allow the
temperature measurement to be compensated to
account for the difference in temperature between the
DS1870 and the device it is biasing.
To scale the gain and offset of the converter for a spe-
cific input, you must first know the relationship between
the analog input and the expected digital result. The
input that would produce a digital result of all zeros is
the null value (normally this input is GND). The input
that would produce a digital result of all ones (FFF8h) is
LUT ADDRESS
(hex)
VD VALUE
(hex)
IDX VALUE
(hex)≤ 800000008200020084000400…FC007C00≥ FE00≥ 7E00
Table6. LUT Addresses for VDor IDXValues9Ah
99h
98h
97h
96h
95h4681012
TEMPERATURE (°C)
MEMOR
Y LOCA
TION
MEMOR
Y LOCA
TION
MEMOR
Y LOCA
TION9Ah
99h
98h
97h
96h
95h
AA00AC00AEOOB000B200B400
DRAIN VOLTAGE CONVERSION (HEX)9Ah
99h
98h
97h
96h
95h
2A002C002E00300032003400
DRAIN CURRENT CONVERSION (HEX)INCREASING
TEMPERATURE
INCREASING
DRAIN VOLTAGE
INCREASING
DRAIN CURRENT
DECREASING
TEMPERATURE
DECREASING
DRAIN VOLTAGE
DECREASING
DRAIN CURRENT
Figure 1. LUT Hysteresis
DS1870
LDMOS RF Power-Amplifier Bias
Controllerthe full-scale (FS) value. The expected FS value is also
found by multiplying an all-ones digital answer by the
LSB weight.
Example: Since the FS digital reading is 65,528 (FFF8
hex) LSBs, if the LSB’s weight is 50µV, then the FS
value is 65,528 x 50µV = 3.2764V.
A binary search is used to calibrate the gain of the con-
verter. This requires forcing two known voltages to the
input pin. It is preferred that one of the forced voltages
is the null input and the other is 90% of FS. Since the
LSB of the least significant bit in the digital reading reg-
ister is known, the expected digital results can be cal-
culated for both the null input and the 90% of full scale
value.
An explanation of the binary search used to scale the
gain is best served with the following example pseudo-
code:
/* Assume that the null input is 0.5V */
/* Assume that the requirement for the LSB is 50µV */
FS = 65528 * 50e-6; /*3.2764V */
CNT1 = 0.5 / 50e-6; /* 1000 */
CNT2 = 0.9 X FS / 50e-6;/* 58981.5 */
/* So the null input is 0.5V and 90% of FS is 2.949V */
Set the input’s offset register to zero
gain_result = 0h; /* Working register for gain
calculation */
CLAMP = FFF8h; /* This is the max ADC value*/
For n = 15 down to 0
begin
gain_result = gain_result + 2n;
Write gain_result to the input’s
gain register;
Force the 90% FS input (2.949V);
Meas2= ADC result from DS1870;
If Meas2 ≥CLAMP
Then
gain_result = gain_result - 2n;
Else
Force the null input (0.5V)
Meas1 = ADC result from DS1870
If [(Meas2-Meas1)>(CNT2-CNT1)]
Then
gain_result = gain_result - 2n;
end;
Write gain_result to the input’s gain
register;
The gain register is now set and the resolution of the
conversion matches the expected LSB. Customers
requiring non-zero null values (e.g., 0.5V) must next
calibrate the input’s offset. If the desired null value is
0V, leave the offset register programmed to 0000h and
skip this step.
To calibrate the offset register, program the gain regis-
ter with the gain_result value determined above. Next,
force the null input voltage (0.5V for the example) and
read the digital result from the part (Meas1). The offset
value can be calculated using the following formula:
Temperature-Monitor Offset CalibrationThe DS1870’s temperature sensor comes precalibrated
and requires no further adjustment by the customer for
proper operation. However, it is possible for customers
to characterize their system and add a fixed offset to
the DS1870’s temperature reading so it is reflective of
another location’s temperature. This is not required for
biasing because the temperature offset can be
accounted for by adjusting the data’s location in the
LUTs, but this feature is available for customers who
see application benefits.
To change the temperature sensor’s offset: write the
temperature offset register to 0000h, measure the
source reference temperature (Tref), and read the tem-
perature from the DS1870 (TDS1870). Then, the follow-
ing formula can be used to calculate the value for the
temperature offset register.
Once the value is calculated, write it to the temperature
offset register.
Power-Up and Low-Voltage OperationDuring power-up, the device is inactive until VCC
exceeds the digital power-on-reset voltage (VPOD). At
this voltage, the digital circuitry, which includes the I2C-
compatible interface, becomes functional. However,
EEPROM-backed registers/settings cannot be internally
read (recalled) until VCCexceeds the analog power-on
reset (VPOA), at which time the remainder or the device
becomes fully functional. Once VCCexceeds VPOA, the
Rdyb bit in byte 74h is timed to go from a 1 to a 0 and
indicates when ADC conversions begin. If VCCever
dips below VPOA, the Rdyb bit reads as a 1 again.
Once a device exceeds VPOAand the EEPROM is
recalled, the values remain active (recalled) until VCC
falls below VPOD.
TempOffsetTTXORBBhrefDSbitwise=×−+−()()64275401870
OffsetMeas=−×⎛⎜⎞⎟11
DS1870
LDMOS RF Power-Amplifier Bias
ControllerAs the device powers up, the VCCLo alarm flag
defaults to a 1 until the first VCCADC conversion
occurs and sets or clears the flag accordingly. The
FAULT output is active when VCC< VPOA.
Memory DescriptionThe DS1870 memory map is divided into six sections
that include the lower memory (addresses 00h to 7Fh)
and five memory tables (Figure2). The memory tables
are addressed by setting the table-select byte (7Fh) to
the desired tablenumber and accessing the upper
memory locations (80h to FFh). The lower memory can
be addressed at any time regardless of the state of the
table-select byte. The lower memory and memory table
1 are used to configure the DS1870 and read the status
of the monitors. The lower memory also contains the 32
bytes of user memory. Memory tables 2 and 3 contain
the base potentiometer positions that are used for bias-
ing based on the reading of the internal temperature
sensor. Memory tables 4 and 5 contain the relative off-
sets that are added to the base number as a function of
either the drain voltage or the individual drain current
monitors. See the Memory Mapfor a complete listing of
registers and the Register Descriptionsection for
details about each register.
Password Memory ProtectionThe DS1870 contains a 2-byte password that allows all
of its EE memory to be write protected until the proper
password is entered into the password entry (PWE)
word (address 78h). This allows factory calibration data
for the bias settings, alarm thresholds, and all the other
EEPROM information to be write protected. The pass-
word is set by writing to the Password register, which is
the first two bytes of memory table1.
The factory default value for the password is FFFFh,
which is also the factory default value for PWE on
power-up. This means that parts are unlocked at
power-up when they are first received by customers.
The password should be programmed to a value other
than FFFFh to ensure the calibration data is write pro-
tected. The PWE register always reads 0000h regard-
less of its programmed value.
EEPROM Write DisableMemory locations 20h to 3Fh and Table1 locations 80h
to A7h are SRAM-shadowed EEPROM. By default
(SEE= 0) these locations act as ordinary EEPROM. By
setting SEE= 1, these locations begin to function like
SRAM cells, which allow an infinite number of write
cycles without concern of wearing out the EEPROM.
This also eliminates the requirement for the EEPROM
write time. Because changes made with SEE= 1 do not
affect the EEPROM, these changes are not retained
through power cycles. The power-up value is the last
value written with SEE= 0. This function can be used to
limit the number of EEPROM writes during calibration or
to change the monitor thresholds periodically during
normal operation without wearing out the EEPROM. The
SEEbit resides in memory table1, byte AFh.
Memory MapThe upper part of the memory map is organized into
8-byte or 4-word (2-byte) rows. The beginning address
of the row is shown in the left-most column of the map,
and is equal to the byte 0 or word 0 memory address.
The next byte (Byte 1) is located at the next highest
memory address, and the next word (Word 1) is two
memory addresses greater than the row’s beginning
address. The lower part of the memory map expands
the bytes or the words to show the names of the bits
within the byte/word, or their bit weights (2X) for regis-
ters that contain numerical information. Numerical reg-
isters that contain an “S” in the most significant bit are
showing sign extension for 2’s complement numbers.
Descriptions of each byte/bit follow in the Register
Descriptionsection.
USER MEMORY;
HI/LO ALARM
THRESHOLDS;
ADC RESULTS;
CONFIGURATION
CONFIGURATIONPOT1
TEMP
LUT
POT2
TEMP
LUT
POT1
DRAIN
LUT
POT2
DRAIN
LUT
00h
7Fh
80h
AFh
80h
C7h
80h
C7h
80h
BFh
80h
BFh
MAIN MEMORY
TABLE 1TABLE 2TABLE 3TABLE 4TABLE 5
TABLE-SELECT
BYTE (7Fh)
SEL
SELSELSELSEL
Figure 2. Memory Organization
