DS1865 ,PON Triplexer Control and Monitoring CircuitApplicationsMaskable Laser Shutdown CapabilityOptical Triplexers with GEPON, BPON, or GPON♦ Two-Lev ..
DS1865K ,PON Triplexer Control and Monitoring CircuitELECTRICAL CHARACTERISTICS(V = +2.85V to +3.9V, T = -40°C to +95°C, unless otherwise noted.)CC APAR ..
DS1865K+ ,PON Triplexer Control and Monitoring CircuitFeaturesThe DS1865 controls and monitors all the burst-mode♦ Meets GEPON, BPON, and GPON Timingtran ..
DS1866 ,Log Trimmer PotentiometerPIN DESCRIPTIONSV - Power Supply Terminal. The DS1866 will support supply voltages ranging from +2. ..
DS1866Z ,Log Trimmer PotentiometerPIN DESCRIPTIONSV - Power Supply Terminal. The DS1866 will support supply voltages ranging from +2. ..
DS1867-010 , Dual Digital Potentiometer with EEPROM
DS1865-DS1865K-DS1865K+
PON Triplexer Control and Monitoring Circuit
General DescriptionThe DS1865 controls and monitors all the burst-mode
transmitter and video receiver biasing functions for a
passive optical network (PON) triplexer. It has an APC
loop with tracking-error compensation that provides the
reference for the laser driver bias current and a temper-
ature-indexed lookup table (LUT) that controls the mod-
ulation current. It continually monitors for high output
current, high bias current, and low and high transmit
power with its internal fast comparators to ensure that
laser shutdown for eye safety requirements are met with-
out adding external components. Six ADC channels
monitor VCC, internal temperature, and four external
monitor inputs (MON1–MON4) that can be used to meet
transmitter and video receive signal monitoring require-
ments. Two digital-to-analog converter (DAC) outputs
are available for biasing the video receiver channel, and
five digital I/O pins are present to allow additional moni-
toring and configuration.
ApplicationsOptical Triplexers with GEPON, BPON, or GPON
Transceiver
FeaturesMeets GEPON, BPON, and GPON Timing
Requirements for Burst-Mode TransmittersBias Current Control Provided by APC Loop with
Tracking-Error CompensationModulation Current is Controlled by a
Temperature-Indexed Lookup TableLaser Power Leveling from -6dB to +0dBTwo 8-Bit Analog Outputs, One is Controlled by
MON4 Voltage for Video Amplifier Gain ControlInternal Direct-to-Digital Temperature SensorSix Analog Monitor Channels: Temperature, VCC,
MON1, MON2, MON3, and MON4Five Digital I/O Pins for Additional Control and
Monitoring FunctionsComprehensive Fault Management System with
Maskable Laser Shutdown CapabilityTwo-Level Password Access to Protect
Calibration Data120 Bytes of Password 1 Protected Nonvolatile
Memory128 Bytes of Password 2 Protected Nonvolatile
Memory in Main Device Address128 Bytes of Nonvolatile Memory Located at A0h
Slave AddressI2C-Compatible Interface for Calibration and
MonitoringOperating Voltage: 2.85V to 3.9VOperating Temperature Range: -40°C to +95°CPackaging: 28-Pin Lead-Free TQFN (5mm x 5mm
x 0.8mm)
DS1865
PON Triplexer Control and
Monitoring Circuit19-5044; Rev 1; 11/09
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
T&R = Tape and reel.
Ordering Information
PARTTEMP RANGEPIN-PACKAGE DS1865T+ -40°C to +95°C 28 TQFN-EP*
DS1865T+T&R -40°C to +95°C 28 TQFN-EP*
TQFN
(5mm x 5mm x 0.8mm)TOP VIEW272524911
TX-D
FETG
VCC
GND
N.C.
*EP
*EXPOSED PAD.
BEN
BIAS
GND
M4DAC
MOD
DAC1
MON4
N.C.
N.C.
SCLSDA
TX-FVCC3
LOSID0BMDD2D3D1
MON3MON1MON2
N.C.
DS1865
Pin Configuration
DS1865
PON Triplexer Control and
Monitoring Circuit
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS(TA= -40°C to +95°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on MON1–MON4, BEN, BMD, and
TX-D Pins Relative to Ground.................-0.5V to (VCC+ 0.5V)
(subject to not exceeding +6V)
Voltage Range on VCC, SDA, SCL, D0–D3, and
TX-F Pins Relative to Ground...............................-0.5V to +6V
Operating Temperature Range...........................-40°C to +95°C
Programming Temperature Range.........................0°C to +70°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature...................See J-STD-020 Specification
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS Supply Voltage VCC (Note 1) +2.85 +3.9 V
High-Level Input Voltage
(SDA, SCL, BEN) VIH:10.7 x
VCC
VCC +
0.3 V
Low-Level Input Voltage
(SDA, SCL, BEN) VIL:1 -0.3 0.3 x
VCCV
High-Level Input Voltage
(TX-D, LOSI, D0, D1, D2, D3) VIH:2 2.0 VCC +
0.3 V
Low-Level Input Voltage
(TX-D, LOSI, D0, D1, D2, D3) VIL:2 -0.3 0.8 V
DC ELECTRICAL CHARACTERISTICS(VCC = +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSupply CurrentICC(Notes 1, 2)510mA
Output Leakage
(SDA, TX-F, D0, D1, D2, D3)ILO1µA
IOL = 4mA0.4Low-Level Output Voltage
(SDA, TX-F, FETG, D0, D1, D2, D3)VOLIOL = 6mA0.6V
High-Level Output Voltage
(FETG)VOHIOH = 4mAVCC -
0.4V
FETG Before Recall(Note 3)10100nA
Input-Leakage Current
(SCL, BEN, TX-D, LOSI)ILI1µA
Digital Power-On ResetPOD1.02.2V
Analog Power-On ResetPOA2.12.75V
DS1865
PON Triplexer Control and
Monitoring Circuit
ANALOG INPUT CHARACTERISTICS (BMD, TXP-HI, TXP-LO, HBIAS)(VCC = +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSBM D , TX P - H I, TX P - LO Ful l - S cal e V ol tag eVAPC(Note 4)2.5V
HBIAS Full-Scale Voltage1.25mA
BM D Input Resistance355065kΩ
Resolution(Note 4)8Bits
ErrorTA = +25°C (Note 5)±2%FS
Integral Nonlinearity-1+1LSB
Differential Nonlinearity-1+1LSB
Temperature Drift-2.5+2.5%FS
ANALOG OUTPUT CHARACTERISTICS(VCC = +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSBIAS CurrentIBIAS(Note 1)1.2mA
IBIAS Shutdown CurrentIBIAS:OFF10100nA
Voltage at IBIAS0.71.21.4V
MOD Full-Scale VoltageVMOD(Note 6)1.25V
MOD Output Impedance(Note 7)3kΩ
VMOD ErrorTA = +25°C (Note 8)-2.5+2.5%FS
VMOD Integral Nonlinearity-3+3LSB
VMOD Differential Nonlinearity-1+1LSB
VMOD Temperature Drift-2+2%FS
ELECTRICAL CHARACTERISTICS (DAC1 and M4DAC)(VCC = +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSDAC Output Range02.5V
DAC Output Resolution8Bits
DAC Output Integral Nonlinearity-2+2LSB
DAC Output Differential Nonlinearity-1+1LSB
DAC ErrorTA = +25°C-1.25+1.25LSB
DAC Temperature Drift-2+2% FS
DAC OffsetVCC = 2.85V to 3.6V-20+20µV
Maximum Load-500+500µA
Maximum Load Capacitance250pF
TIMING CHARACTERISTICS (CONTROL LOOP AND QUICK-TRIP)(VCC = +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSFirst MD Sample Following BENtFIRST(Note 9)
Remaining Updates During BENtUPDATE(Note 9)
BEN High TimetBEN:HIGH400ns
BEN Low TimetBEN:LOW96ns
Output-Enable Time Following POAtINIT10ms
BIAS and MOD Turn-Off DelaytOFF5µs
BIAS and MOD Turn-On DelaytON5µs
FETG Turn-On DelaytFETG:ON5µs
FETG Turn-Off DelaytFETG:OFF5µs
Binary Search TimetSEARCH(Note 10)513BIAS amp l es
ADC Round-Robin TimetRR75ms
DS1865
PON Triplexer Control and
Monitoring Circuit
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSThermometer ErrorTERR-40°C to +95°C±3.0°C
DIGITAL THERMOMETER(VCC= +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSInput ResolutionΔVMON610µV
Supply ResolutionΔVCC1.6mV
Input/Supply AccuracyM ON 1, M ON 2, M ON 3, M ON 4, V C C ) ACCAt factory setting0.250.5% FS
(full scale)
Update Rate for MON1, MON2,
MON3, MON4 Temp, or VCCtFRAME3045ms
Input/Supply OffsetM ON 1, M ON 2, M ON 3, M ON 4, V C C ) VOS(Note 14)05LSBON1, MON 2,ON3, MON 42.5Factory SettingC C 6.5536
ANALOG VOLTAGE MONITORING (VCC= +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)
DS18652C AC ELECTRICAL CHARACTERISTICS(VCC = +2.85V to +3.9V, TA= -40°C to +95°C, timing referenced to VIL(MAX)and VIH(MIN).) (See Figure 9.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSCL Clock FrequencyfSCL(Note 11)0400kHz
Clock Pulse-Width LowtLOW1.3µs
Clock Pulse-Width HightHIGH0.6µs
Bus-Free Time Between STOP and
START ConditiontBUF1.3µs
Start Hold TimetHD:STA0.6µs
Start Setup TimetSU:STA0.6µs
Data in Hold TimetHD:DAT00.9µs
Data in Setup TimetSU:DAT100ns
Rise Time of Both SDA and SCL
SignalstR(Note 12)20 +
0.1CB300ns
Fall Time of Both SDA and SCL
SignalstF(Note 12)20 +
0.1CB300ns
STOP Setup TimetSU:STO0.6µs
Capacitive Load for Each Bus LineCB(Note 12)400pF
EEPROM Write TimetW(Note 13)20ms
PON Triplexer Control and
Monitoring Circuit
NONVOLATILE MEMORY CHARACTERISTICS(VCC= +2.85V to +3.9V)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSEEPROM Write CyclesAt +70°C50,000
Note 1:All voltages are referenced to ground. Current into IC is positive, out of the IC is negative.
Note 2:Digital inputs are at rail. FETG is disconnected. SDA = SCL = VCC. DAC1 and M4DAC are not loaded.
Note 3:See the Safety Shutdown (FETG) Outputsection for details.
Note 4:Eight ranges allow the full-scale range to change from 625mV to 2.5V.
Note 5:This specification applies to the expected full-scale value for the selected range. See the Comp Ranging byte for available
full-scale ranges.
Note 6:Eight ranges allow the BMD full-scale range to change from 312.5mV to 1.25V.
Note 7:The output impedance of the DS1865 is proportional to its scale setting. For instance, if using the 1/2 scale, the output
impedance would be approximately 1.56kΩ.
Note 8:This specification applies to the expected full-scale value for the selected range. See the Mod Ranging byte for available
full-scale ranges.
Note 9:See the APC and Quick-Trip Shared Comparator Timing sectionfor details.
Note 10:Assuming an appropriate initial step is programmed that would cause the power to exceed the APC set point within four
steps, the bias current will be 1% within the time specified by the binary search time. See the Bias and MODOutput During
Power-Up section.
Note 11:I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with the I2C stan-
dard mode.
Note 12:CBtotal capacitance of one bus line in picofarads.
Note 13:EEPROM write begins after a STOPcondition occurs.
Note 14:Guaranteed by design.
DS1865
PON Triplexer Control and
Monitoring CircuitDAC1 AND M4DAC INL
DS1865 toc04
DAC1 AND M4DAC POSITION (DEC)
DAC1 AND M4DAC INL (LSB)
DAC1 AND M4DAC OFFSET vs. VCC
DS1865 toc05
VCC (V)
DAC1 AND M4DAC OFFSET (mV)
TA = -40°C TO +95°C
LOAD = -0.5mA TO +0.5mA
DAC1 AND M4DAC OFFSET VARIATION
vs. LOAD CURRENT
DS1865 toc06
LOAD CURRENT (mA)
DAC1 AND M4DAC OFFSET (mV)
VCC = 2.85V
VCC = 3.6V
VCC = 3.9V
DAC1 AND M4DAC OUTPUT
vs. LOAD CURRENT
DS1865 toc07
LOAD CURRENT (mA)
DAC1 AND M4DAC OUTPUT (V)
VCC = 2.85V
VCC = 3.9V
OUTPUT WITHOUT OFFSET
CALCULATED AND DESIRED % CHANGE
IN VMOD vs. MOD RANGING
DS1865 toc08
MOD RANGING VALUE (DEC)
CHANGE IN V
MOD
(%)
DESIRED VALUE
CALCULATED VALUE
DESIRED AND CALCULATED CHANGE
IN VBMD vs. COMP RANGING
DS1865 toc09
COMP RANGING (DEC)
CHANGE IN V
BMD
(%)
DESIRED VALUE
CALCULATED VALUE
Typical Operating Characteristics(VCC = 3.3V, TA= +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
DS1865 toc01
VCC (V)
SUPPLY CURRENT (mA)
SDA = SCL = VCC
+95°C
-40°C+25°C
SUPPLY CURRENT vs. TEMPERATURE
DS1865 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
SDA = SCL = VCC
VCC = 3.9V
VCC = 2.85V
DAC1 AND M4DAC DNL
DS1865 toc03
DAC1 AND M4DAC POSITION (DEC)
DAC1 AND M4DAC DNL (LSB)
DS1865
PON Triplexer Control and
Monitoring CircuitMON1–MON4 INL
DS1865 toc10
MON1–MON4 INPUT VOLTAGE (V)
MON1–MON4 INL (LSB)
USING FACTORY-PROGRAMMED
FULL-SCALE VALUE OF 2.5V
MON1–MON4 DNL
DS1865 toc11
MON1–MON4 INPUT VOLTAGE (V)
MON1–MON4 DNL (LSB)
USING FACTORY-PROGRAMMED
FULL-SCALE VALUE OF 2.5V
VBMD INL vs. APC INDEX
DS1865 toc12
APC INDEX (DEC)
BMD
INL (LSB)
Typical Operating Characteristics (continued)(VCC = 3.3V, TA= +25°C, unless otherwise noted.)
VMOD INL vs. MOD INDEX
DS1865 toc13
MOD INDEX (DEC)
MOD
INL (LSB)
DS1865
PON Triplexer Control and
Monitoring Circuit
Pin Description
PINNAMEFUNCTIONBENBurst Enable Input. Triggers the sampling of the APC and quick-trip monitors.TX-DTransmit Disable Input. Disables BIAS and MOD outputs.TX-FTransmit Fault Output, Open DrainFETGOutput to FET Gate. Signals an external n- or p-channel MOSFET to enable/disable the laser’s current.
5, 19VCCSupply Voltage
6, 18GNDGround
7, 10, 11,N.C.No ConnectionSDAI2C Serial Data. Input/output for I2C data.SCLI2C Serial Clock. Input for I2C clock.
12–15MON1–MON4
External Monitor Input 1–4. The voltage at these pins are digitized by the internal analog-to-digital
converter and can be read through the I2C interface. Alarm and warning values can be assigned to
interrupt the processor based on the ADC result.DAC1M4DAC
Digital-to-Analog Output DAC1 and M4DAC. Two 8-bit DAC outputs for generating analog voltages.
Typically used to control the video photodiode bias. M4DAC is controlled by the input voltage on MON4
and Table 06h LUT.BIASBias Current Output. This current DAC generates the bias current reference for the MAX3643.MODModulation Output Voltage. This 8-bit voltage output has eight full-scale ranges from 1.25V to 0.3125V.
This pin is connected to the MAX3643’s VMSET input to control the modulation current.BMDMonitor Diode Input (Feedback Voltage, Transmit Power Monitor)LOSILoss-of-Signal Input. This input is accessible in the status register through the I2C interface.D0Digital I/O 0. This signal is either the open-drain output driver for LOSI, or can be controlled by the
OUT0 bit (D0OUT). The logic level of this pin is indicated by the D0IN and LOS status bits.
26, 27,D1, D2, D3Digital I/O 1–3. These are bidirectional pins controlled by internally addressable bits. The outputs are
open-drain.EPExposed Pad. This contact should be connected to GND.
DS1865
PON Triplexer Control and
Monitoring CircuitHBIAS QUICK-
TRIP LIMIT
HTXP QUICK-
TRIP LIMIT
LTXP QUICK-
TRIP LIMIT
APC SET POINT
FROM APC LUT
LATCH
ENABLE
VCC
TEMP
SENSOR
I2C
INTERFACE
SAMPLE
CONTROL
8-BIT DAC
W/SCALINGDIGITAL APC
INTEGRATOR
13-BIT
DAC
ANALOG MUX
MOD LUT
8-BIT DAC
W/SCALING
BIAS MAX
QUICKTRIP
INTERRUPT
MASK
INTERRUPT
LATCH
INTERRUPT
MASK
INTERRUPT
LATCH
POWER-ON ANALOG
VCC > VPOA
NONMASKABLE
INTERRUPT
13-BIT
ADC
DS1865 MEMORY ORGANIZATION
SRAM RESET
DIGITAL LIMIT
COMPARATOR FOR
ADC RESULTS
DS1865
MUX
MUX
MUX
TX-D
BMD
BEN
MON3
MON2
MON1
MON4
SCL
SDA
TTL
LOSI
TTLD0D0 IN/LOS STATUS
D0 OUT
MUX LOSI
TTLD1D1 IN
D1 OUT
TTLD2D2 IN
D2 OUT
TTLD3D3 IN
D3 OUT
GND
INV LOSI
DAC1
8-BIT, 2.5V
FULL SCALE
I2C PROGRAMMED
NONVOLATILE SETTINGDAC1
FETG
BIAS
MOD
M4DAC
8-BIT, 2.5V
FULL SCALE
TABLE 06h
VIDEO POWER
LOOKUP TABLE
M4DAC
I2C CONTROL
VCC
VCC
EEPROM
128 BYTES AT
A0h SLAVE
ADDRESS
TX-F
TABLE 01h (EEPROM)
PW1 USER MEMORY, ALARM TRAP
TABLE 04h (EEPROM)
MODULATION LUT
TABLE 02h (EEPROM)
CONFIGURATION AND CALIBRATION
TABLE 05h (EEPROM)
APC LUT
TABLE 03h (EEPROM)
PW2 USER MEMORY
TABLE 06h (EEPROM)
M4DAC (VIDEO GAIN LUT)
MAIN MEMORY
EEPROM/SRAM
ADC CONFIGURATION/RESULTS
SYSTEM STATUS BITS
ALARM/WARNING COMPARISON RESULTS/THRESHOLDS
Block Diagram
DS1865
PON Triplexer Control and
Monitoring Circuit
Detailed DescriptionThe DS1865 integrates the control and monitoring func-
tionality required to implement a PON system using
Maxim’s MAX3643 compact burst-mode laser driver.
The compact laser driver solution offers a considerable
cost benefit by integrating control and monitoring fea-
tures in the low-power CMOS process, while leaving
only the high-speed portions to the laser driver. Key
components of the DS1865 are shown in the Block
Diagramand described in subsequent sections. Table 1
contains a list of acronyms used in this data sheet.
APC ControlBIAS current is controlled by an average power control
(APC) loop. The APC loop uses digital techniques to
overcome the difficulties associated with controlling
Typical Operating CircuitBEN+
BEN-
DIS
IN-
IN+
OUT-
BIAS-
BIAS+
MDIN
COMPACT BURST-MODE
LASER DRIVER
DS1865
BURST-MODE
MONITOR/CONTROL CIRCUIT
MDOUT
OUT+
VCC
TX-F
TX-D
SCL
SDA
LOSI
MON2
MON3
MON4
FETG
DAC1
M4DAC
MON13.3V
THERMISTOR
APD BOOST DC-DC
BMD
3.3V
VMSETMODSETVREFIMAXGNDBIASSETBENOUT
MODBIAS
BEN
BCMONVBSET
TRANSMIT POWER
DISABLE INPUT
RECEIVER LOS
OPEN-DRAIN LOS OUTPUT
FAULT OUTPUT
I2C COMMUNICATION
RECEIVE POWER
ADDITIONAL
DIGITAL I/O
CATV
12V
FTTH CATV
TIA
GAIN CONTROL
SHUTDOWN CONTROL
MAX3643
MAX3654
Table 1. Acronyms
ACRONYMDEFINITIONADCAnalog-to-Digital Converter
APCAverage Power Control
ATBAlarm Trap Bytes
DACDigital-to-Analog Converter
LUTLookup TableNonvolatile
PONPassive Optical NetworkQuick Trip
SEEShadowed EEPROMTracking Error
TXPTransmit Power
DS1865
PON Triplexer Control and
Monitoring CircuitThe APC loop’s feedback is the monitor diode (BMD)
current, which is converted to a voltage using an exter-
nal resistor. The feedback voltage is compared to an 8-
bit scaleable voltage reference that determines the
APC set point of the system. Scaling of the reference
voltage accommodates the wide range in photodiode
sensitivities. This allows the application to take full
advantage of the APC reference’s resolution.
The DS1865 has an LUT to allow the APC set point to
change as a function of temperature to compensate for
tracking error (TE). The TE LUT (Table 05h) has 36
entries that determine the APC setting in 4°C windows
between -40°C to +100°C. Ranging of the APC DAC is
possible by programming a single byte in Table 02h.
Modulation ControlThe MOD output is an 8-bit scaleable voltage output that
interfaces with the MAX3643’s VMSET input. An external
resistor to ground from the MAX3643’s MODSET pin sets
the maximum current the voltage at VMSET input can
produce for a given output range. This resistor value
should be chosen to produce the maximum modulation
current the laser type requires over temperature. Then
the MOD output’s scaling is used to calibrate the full-
scale (FS) modulation output to a particular laser’s
requirements. This allows the application to take full
advantage of the MOD output’s resolution. The modula-
tion LUT can be programmed in 2°C increments over the
-40°C to +102°C range.
Ranging of the MOD DAC is possible by programming
a single byte in Table 02h.
BIAS and MOD Output
During Power-UpOn power-up, the modulation and bias outputs remain
off until VCCis above VPOAand a temperature conver-
sion has been completed. If the VCCLO ADC alarm is
enabled, then a VCCconversion above the customer-
defined VCClow alarm level is required before the
outputs are enabled with the value determined by the
temperature conversion and the modulation LUT.
When the MOD output is enabled and BEN is high, the
BIAS output is turned on to a value equal to ISTEP(see
Figure 1). The startup algorithm checks if this bias cur-
rent causes a feedback voltage above the APC set point,
and if it does not it continues increasing the BIAS by
ISTEPuntil the APC set point is exceeded. When the APC
set point is exceeded, the DS1865 begins a binary
search to quickly reach the bias current corresponding
to the proper power level. After the binary search is com-
pleted the APC integrator is enabled, and single LSB
steps are taken to tightly control the average power.
All quick-trip alarm flags are masked until the binary
search is completed. However, the BIAS MAX alarm is
monitored during this time to prevent the bias output
from exceeding MAX IBIAS. During the bias current ini-
tialization, the bias current is not allowed to exceed
MAX IBIAS. If this occurs during the ISTEPsequence,
the binary search routine begins. If MAX IBIAS is
exceeded during the binary search, the next smaller
step is activated. ISTEPor binary increments that would
cause IBIASto exceed MAX IBIAS are not taken.
Masking the alarms until the completion of the binary
search prevents false trips during startup.
ISTEPis programmed by the customer using the Startup
Step register. This value should be programmed to the
maximum safe current increase that is allowable during
startup. If this value is programmed too low, the DS1865
will still operate, but it could take significantly longer for
the algorithm to converge and hence to control the aver-
age power.
If a fault is detected and TX-D is toggled to re-enable the
outputs, the DS1865 powers up following a similar
sequence to an initial power-up. The only difference is
that the DS1865 already has determined the present tem-
perature, so the tINITtime is not required for the DS1865
to recall the APC and MOD set points from EEPROM.
If the Bias-En bit (Table 02h, Register 80h) is written to
0, the BIAS DAC is manually controlled by the MAN
IBIAS register (Table 02h, Registers F8h–F9h).
BIAS and MOD Output as a Function
of Transmit Disable (TX-D)If the TX-D pin is asserted (logic 1) during normal oper-
ation, the outputs are disabled within tOFF. When TX-D
is deasserted (logic 0), the DS1865 turns on the MOD
output with the value associated with the present tem-
perature, and initializes the BIAS using the same
search algorithm used at startup. When asserted, the
soft TX-D (Lower Memory, Register 6Eh) offers a soft-
ware control identical to the TX-D pin (see Figure 2).
APC and Quick-Trip Shared
Comparator TimingAs shown in Figure 3, the DS1865’s input comparator is
shared between the APC control loop and the three
quick-trip alarms (TXP-HI, TXP-LO, and BIAS HI). The
comparator polls the alarms in a round-robin multi-
plexed sequence. Six of every eight comparator read-
ings are used for APC loop-bias current control. The
other two updates are used to check the HTXP/LTXP
(monitor diode voltage) and the HBIAS (MON1) signals
against the internal APC and BIAS reference. The
HTXP/LTXP comparison checks HTXP to see if the last
DS1865
PON Triplexer Control and
Monitoring Circuitbias update comparison was above the APC set point,
and checks LTXP to see if the last bias update compari-
son was below the APC set point. Depending on the
results of the comparison, the corresponding alarms
and warnings (TXP-HI, TXP-LO) are asserted or
deasserted.
The DS1865 has a programmable comparator sample
time based on an internally generated clock to facilitate a
wide variety of external filtering options suitable
for burst-mode transmitter data rates between 155Mbps
and 1250Mbps. The rising edge of the burst enable
(BEN) triggers the sample to occur, and the Update Rate
register (Table 02h, Register 88h) determines the sam-
pling time. The first sample occurs tFIRSTafter the rising
edge of BEN. The internal clock is asynchronous to BEN,
causing a ±50ns uncertainty regarding when the first
sample will occur following BEN. After the first sample
occurs, subsequent samples occur on a regular interval,
tREP. Table 2 shows the sample rate options available.2345678910111213
tINIT
VPOA
BINARY SEARCH
APC
INTEGRATOR
tSEARCH
VMOD
IBIAS
VCC
BIAS
SAMPLE
ISTEP
4x ISTEP
3x ISTEP
2x ISTEP
Figure 1. Power-Up Timing
TX-D
IBIAS
VMODtOFFtON
tONtOFF
Figure 2. TX-D Timing (Normal Operating Conditions)
Table 2. Update Rate Timing
SR3–SR0
MINIMUM TIME
FROM BEN TO
FIRST SAMPLE
(tFIRST) ±50ns
REPEATED
SAMPLE PERIOD
FOLLOWING FIRST
SAMPLE (tREP)0000b350ns800ns
0001b550ns1200ns
0010b750ns1600ns
0011b950ns2000ns
0100b1350ns2800ns
0101b1550ns3200ns
0110b1750ns3600ns
0111b2150ns4400ns
1000b2950ns6000ns
1001b*3150ns6400ns
*All codes greater than 1001b (1010b–1111b) use the maximum
sample time of code 1001b.
DS1865
PON Triplexer Control and
Monitoring CircuitUpdates to the TXP-HI, TXP-LO, and BIAS HI quick-trip
alarms do not occur during the burst-enable low time.
Any quick-trip alarm that is detected by default remains
active until a subsequent comparator sample shows the
condition no longer exists.
A second bias-current monitor (BIAS MAX) compares
the DS1865’s BIAS DAC’s code to a digital value stored
in the MAX IBIAS register. This comparison is made
every bias-current update to ensure that a high bias
current is quickly detected.
Monitors and Fault Detection
MonitorsMonitoring functions on the DS1865 include four quick-
trip comparators and six ADC channels. This monitor-
ing, combined with the interrupt masks, determines
when/if the DS1865 shuts down its outputs and triggers
the TX-F and FETG outputs. All the monitoring levels
and interrupt masks are user programmable.
Four Quick-Trip Monitors and AlarmsFour quick-trip monitors are provided to detect potential
laser safety issues. These monitor:High Bias Current (HBIAS)Low Transmit Power (LTXP)High Transmit Power (HTXP)Max Output Current (MAX IBIAS)
The high and low transmit power quick-trip registers
(HTXP and LTXP) set the thresholds used to compare
against the BMD voltage to determine if the transmit
power is within specification. The HBIAS quick-trip com-
pares the MON1 input (generally from the MAX3643
bias monitor output) against its threshold setting to
determine if the present bias current is above specifica-
tion. The BIAS MAX quick-trip is a digital comparison
that determines if the BIAS DAC indicates that the bias
current is above specification. IBIASis not allowed to
exceed the value set in the MAX IBIAS register. When
the DS1865 detects that the bias is at the limit, it sets the
BIAS MAX status bit and holds the bias current at the
MAX IBIAS level. The quick-trips are routed to the TX-F
and FETG outputs through interrupt masks to allow com-
binations of these alarms to be used to trigger these out-
puts. When FETG is triggered, the DS1865 also disables
the MOD and BIAS outputs. See the BIASand MOD
Output During Power-Upsection for details.
Six ADC Monitors And AlarmsThe ADC monitors six channels that measure tempera-
ture (internal temp sensor), VCC, MON1, MON2, MON3,
and MON4 using an analog multiplexer to measure
them round-robin with a single ADC. Each channel has
a customer-programmable full-scale range and offset
value that is factory programmed to a default value (see
Table 3). Additionally, MON1–MON4 can right shift
results by up to 7 bits before the results are compared
to alarm thresholds or read over the I2C bus. This
allows customers with specified ADC ranges to cali-
brate the ADC full scale to a factor of 1/2nof their spec-
ified range to measure small signals. The DS1865 can
then right shift the results by n bits to maintain the bit
weight of their specification.
LAST BURST'S
BIAS SAMPLE
BEN
BIAS DAC CODE
QUICK-TRIP
SAMPLE TIMES
HBIAS
SAMPLE
tFIRST
tREP
HTXP/LTXP
SAMPLE
BIAS
SAMPLE
BIAS
SAMPLE
BIAS
SAMPLE
BIAS
SAMPLE
BIAS
SAMPLE
BIAS
SAMPLE
BIAS
SAMPLE
Figure 3. APC and Quick-Trip Alarm Sample Timing
Table 3. ADC Default Monitor Full-Scale
Ranges
SIGNAL (UNITS)+FS
SIGNAL
+FS
HEX
-FS
SIGNAL-FS HEXTemperature (oC)127.9967FFF-1288000
VCC (V)6.5528FFF80V0000
MON1–MON4 (V)2.4997FFF80V0000
DS1865
PON Triplexer Control and
Monitoring CircuitThe ADC results (after right shifting, if used) are com-
pared to high alarm thresholds, low alarm thresholds,
and the warning threshold after each conversion, and
the corresponding alarms are set, which can be used
to trigger the TX-F or FETG outputs. These ADC thresh-
olds are user programmable, as are the masking regis-
ters that can be used to prevent the alarms from
triggering the TX-F and FETG outputs.
ADC TimingThere are six analog channels that are digitized in a
round-robin fashion in the order as shown in Figure 4. The
total time required to convert all six channels is tRR(see
Timing Characteristics (Control Loop and Quick-Trip)
for details).
Right Shifting ADC ResultIf the weighting of the ADC digital reading must con-
form to a predetermined full-scale value defined by a
standard’s specification, then right shifting can be used
to adjust the predetermined full-scale analog measure-
ment range while maintaining the weighting of the ADC
results. The DS1865’s range is wide enough to cover all
requirements; when the maximum input value is far
short of the FS value, right shifting can be used to
obtain greater accuracy. For instance, the maximum
voltage might be 1/8th the specified predetermined full-
scale value, so only 1/8th the converter’s range is used.
An alternative is to calibrate the ADC’s full-scale range
to 1/8th the readable predetermined full-scale value
and use a right-shift value of 3. With this implementa-
tion, the resolution of the measurement is increased by
a factor of 8, and because the result is digitally divided
by 8 by right shifting, the bit weight of the measurement
still meets the standard’s specification (i.e., SFF-8472).
The right-shift operation on the ADC result is carried out
based on the contents of Right Shift Control registers
(Table 02h, Registers 8Eh-8Fh) in EEPROM. Four ana-
log channels, MON1–MON4, each have 3 bits allocated
to set the number of right shifts. Up to 7 right-shift oper-
ations are allowed and are executed as a part of every
conversion before the results are compared to the high
and low alarm levels, or loaded into their corresponding
measurement registers (Table 01h, Registers
62h–6Bh). This is true during the setup of internal cali-
bration as well as during subsequent data conversions.
Transmit Fault (TX-F) OutputThe TX-F output has masking registers for the six ADC
alarms and the four QT alarms to select which compar-
isons cause it to assert. In addition, the FETG alarm is
selectable through the TX-F mask to cause TX-F to
assert. All alarms, with the exception of FETG, only
cause TX-F to remain active while the alarm condition
persists. However, the TX-F latch bit can enable the TX-F
output to remain active until it is cleared by the TX-F
reset bit, TX-D, soft TX-D, or by power cycling the part. If
the FETG output is configured to trigger TX-F, it indicates
that the DS1865 is in shutdown, and requires TX-D, soft
TX-D, or cycling power to reset. The QT alarms are
masked until the completion of the binary search. Only
enabled alarms will activate TX-F. See Figure 5.
Table 4 shows TX-F as a function of TX-D and the alarm
sources.
Safety Shutdown (FETG) OutputThe FETG output has masking registers (separate from
TX-F) for the five ADC alarms and the four QT alarms to
select which comparisons cause it to assert. Unlike TX-F,
the FETG output is always latched in case it is triggered
by an unmasked alarm condition. Its output polarity is
programmable to allow an external nMOSFET or
pMOSFET to open during alarms to shut off the laser
diode current. If the FETG output triggers, indicating that
the DS1865 is in shutdown, it requires TX-D, soft TX-D, or
cycling power to be reset. Under all conditions, when the
analog outputs are reinitialized after being disabled, all
the alarms with the exception of the VCClow ADC alarm
are cleared. The VCClow alarm must remain active to
prevent the output from attempting to operate when
TEMPVCCMON1MON2MON3MON4TEMPVCC
ONE ROUND-ROBIN ADC CYCLE
MON4
tRR
NOTE: AT POWER-UP, IF THE VCC LOW ALARM IS SET FOR EITHER THE TX-F OR FETG OUTPUT, THE ADC ROUND-ROBIN TIMING CYCLES BETWEEN TEMP AND VCC ONLY UNTIL VCC IS ABOVE THE VCC LOW THRESHOLD.
Figure 4. ADC Round-Robin Timing
DS1865
PON Triplexer Control and
Monitoring Circuitinadequate VCCexists to operate the laser driver. Once
adequate VCCis present to clear the VCClow alarm, the
outputs are enabled following the same sequence as the
power-up sequence.
As previously mentioned, the FETG is an output used to
disable the laser current through a series nMOSFET or
pMOSFET. This requires that the FETG output can sink
or source current. Because the DS1865 does not know
if it should sink or source current before VCCexceeds
VPOA, which triggers the EE recall, this output will
be high impedance when VCCis below VPOA(see the
Low-Voltage Operationsection for details and
diagram). The application circuit must use a pullup or
pulldown resistor on this pin that pulls FETG to the
alarm/shutdown state (high for a pMOS, low for a
nMOS). Once VCCis above VPOA, the DS1865 pulls the
FETG output to the state determined by the FETG DIR
bit (Table 02h, Register 89h). FETG DIR is 0 if an nMOS
is used and 1 if a pMOS is used.
Determining Alarm Causes
Using the I2C InterfaceTo determine the cause of the TX-F or FETG alarm, the
system processor can read the DS1865’s Alarm Trap
Bytes (ATB) through the I2C interface (in Table 01h). The
ATB has a bit for each alarm. Any time an alarm occurs,
regardless of the mask bit’s state, the DS1865 sets the
corresponding bit in the ATB. Active ATB bits remain set
until written to zeros through the I2C interface. On power-
up, the ATB is zeros until alarms dictate otherwise.
Die IdentificationThe DS1865 has an ID hard coded to its die. Two regis-
ters (Table 02h bytes 86h–87h) are assigned for this
feature. Byte 86h reads 65h to identify the part as the
DS1865, byte 87h reads the die revision.
Low-Voltage OperationThe DS1865 contains two power-on reset (POR) levels.
The lower level is a digital POR (VPOD) and the higher
level is an analog POR (VPOA). At startup, before the
supply voltage rises above VPOA, the outputs are dis-
abled (FETG and BIAS outputs are high impedance,
MOD is low), all SRAM locations are low (including
shadowed EEPROM), and all analog circuitry is dis-
abled. When VCCreaches VPOA, the SEE is recalled,
and the analog circuitry is enabled. While VCCremains
above VPOA, the device is in its normal operating state,
and it responds based on its nonvolatile configuration.
If during operation VCCfalls below VPOAbut is still
above VPOD, the SRAM retains the SEE settings from
TX-F LATCHED OPERATION
TX-F NON LATCHED OPERATION
DETECTION OF
TX-F FAULT
TX-D OR
TX-F RESET
TX-F
DETECTION OF
TX-F FAULT
TX-F
Figure 5. TX-F Timing
Table 4. TX-F as a Function of TX-D and
Alarm Sources
VCC > VPOATX-DNONMASKED
TX-F ALARMTX-FXX1
Yes000
Yes011
Yes1X0
DS1865
PON Triplexer Control and
Monitoring Circuitthe first SEE recall, but the device analog is shut down
and the outputs are disabled. FETG is driven to its
alarm state defined by the FETG DIR bit (Table 02h,
Register 89h). If the supply voltage recovers back
above VPOA, the device immediately resumes normal
functioning. If the supply voltage falls below VPOD, the
device SRAM is placed in its default state and another
SEE recall is required to reload the nonvolatile settings.
The EEPROM recall occurs the next time VCCexceeds
VPOA. Figure 7 shows the sequence of events as the
voltage varies.
Any time VCCis above VPOD, the I2C interface can be
used to determine if VCCis below the VPOAlevel. This is
accomplished by checking the RDYB bit in the status
(Lower Memory, Register 6Eh) byte. RDYB is set when
VCCis below VPOA. When VCCrises above VPOA, RDYB
is timed (within 500µs) to go to 0, at which point the part
is fully functional.
For all device addresses sourced from EEPROM (Table
02h, Register 8Ch), the default device address is A2h
until VCCexceeds VPOAallowing the device address to
be recalled from the EEPROM.
Power-On Analog (POA) POA holds the DS1865 in reset until VCCis at a suitable
level (VCC > VPOA) for the part to accurately measure
with its ADC and compare analog signals with its quick-
trip monitors. Because VCCcannot be measured by the
ADC when VCCis less than VPOA, POA also asserts the
VCClow alarm, which is cleared by a VCCADC conver-
sion greater than the customer-programmable VCClow
ADC limit. This prevents the TX-F and FETG outputs
from glitching during a slow power-up. The TX-F and
FETG outputs do not latch until there is a conversion
above VCClow limit.
The POA alarm is nonmaskable. The TX-F and FETG
outputs are asserted when VCCis below VPOA. See the
Low-Voltage Operationsection for more information.
DAC1 OutputThe DAC1 output has a 0 to 2.5V range, 8 bits of resolu-
tion, and is programmed through the I2C interface. The
DAC1 setting is nonvolatile and password 2 (PW2) pro-
tected.
M4DAC OutputThe M4DAC output has a 0 to 2.5V range, 8 bits of res-
olution, and is controlled by an LUT indexed by the
MON4 voltage. The M4DAC LUT (Table 06h) is non-
volatile and PW2 protected. See the Memory
Organization section for details.
IBIAS
VMOD
DETECTION OF
FETG FAULT
tOFFtON
tONtOFF
TX-D
tFETG:ONFETG*
*FETG DIR = 0
tFETG:OFF
Figure 6. FETG/Modulation and Bias Timing (Fault Condition Detected)
Table 5. FETG, MOD, and BIAS Outputs
as a Function of TX-D and Alarm Sources
VCC >
VPOATX-DNONMASKED
FETG ALARMFETG
MOD AND
BIAS
OUTPUTSYes00FETG DIREnabled
Yes01FETG DIRDisabled
Yes1XFETG DIRDisabled
DS1865
PON Triplexer Control and
Monitoring Circuit
Digital I/O PinsFive digital I/O pins are provided for additional monitor-
ing and control of the triplexer. By default the LOSI pin
is used to convert a standard comparator output for
loss of signal (LOSI) to an open-collector output. This
means the mux shown on the block diagram by default
selects the LOSI pin as the source for the D0 output
transistor. The level of the D0 pin can be read in the
status byte (Lower Memory, Register 6Eh) as the LOS
status bit. The LOS status bit reports back the logic
level of the D0 pin, so an external pullup resistor must
be provided for this pin to output a high level. The LOSI
signal can be inverted before driving the open-drain
output transistor using the XOR gate provided. The
mux LOSI allows the D0 pin to be used identically to the
D1, D2, and D3 pins. However, the mux setting (stored
in the EEPROM) does not take effect until VCC > VPOA,
allowing the EEPROM to recall. This requires the LOSI
pin to be grounded for D0 to act identical to the D1, D2,
and D3 pins.
Digital pins D1, D2, and D3 can be used as inputs or
outputs. External pullup resistors must be provided to
realize high logic levels. The levels of these input pins
can be read by reading the DIN byte (Lower Memory,
Register 79h), and the open-drain outputs can be con-
trolled using the DOUT byte (Lower Memory, Register
78h). When VCC< VPOA, these outputs are high imped-
ance. Once VCC≥VPOA, the outputs go to the power-on
default state stored in the DPU byte (Table 02h, Register
C0h). The EEPROM determined default state of the pin
can be modified with PW2 access. After the default state
has been recalled, the SRAM registers controlling out-
puts can be modified without password access. This
allows the outputs to be used to control serial interfaces
without wearing out the default EEPROM setting.
Memory OrganizationThe DS1865 features eight banks of memory composed
of the following.
The Lower Memoryis addressed from 00h to 7Fh
and contains alarm and warning thresholds, flags,
masks, several control registers, password entry
area (PWE), and the table select byte. The table
select byte determines which table (01h–06h) will be
mapped into the upper memory locations, namely
80h–FFh (unless stated otherwise).
Table 01hprimarily contains user EEPROM (with
PW1 level access) as well as some alarm and warn-
ing status bytes.
Table 02his a multifunction space that contains
configuration registers, scaling and offset values,
passwords, interrupt registers, as well as other mis-
cellaneous control bytes.
Table 03his strictly user EEPROM that is protected
by a PW2 level access.
Table 04hcontains a temperature-indexed LUT for
control of the modulation voltage. The modulation
LUT can be programmed in 2°C increments over the
-40°C to +102°C range. This register is protected by
a PW2 level access.
Table 05hcontains another LUT, which allows the
APC set point to change as a function of tempera-
ture to compensate for tracking error (TE). This TE
LUT has 36 entries that determine the APC setting
in 4°C windows between -40°C to +100°C. This reg-
VCC
VPOA
VPOD
FETG
SEE*
*SEE = SHADOWED EEPROM
HIGH
IMPEDANCE
HIGH
IMPEDANCE
HIGH
IMPEDANCE
NORMAL
OPERATION
DRIVEN TO
FETG DIR
NORMAL
OPERATION
PRECHARGED
TO 0
PRECHARGED
TO 0
PRECHARGED
TO 0
RECALLED
VALUE
RECALLED
VALUE
DRIVEN TO
FETG DIR
NORMAL
OPERATION
DRIVEN TO
FETG DIR
SEE RECALLSEE RECALL
Figure 7. Low-Voltage Hysteresis Example
DS1865
PON Triplexer Control and
Monitoring Circuit
Table 06hcontains a MON4-indexed LUT for con-
trol of the M4DAC voltage. The M4DAC LUT has 32
entries that are configurable to act as one 32-entry
LUT or two 16-entry LUTs. When configured as one
32-byte LUT, each entry corresponds to an incre-
ment of 1/32 of the full scale. When configured as
two 16-byte LUTs, the first 16 bytes and the last 16
bytes each correspond to 1/16 of full scale. Either
of the two sections is selected with a separate con-
figuration bit. This LUT is protected by a PW2 level
access.
Auxiliary Memoryis EEPROM accessible at the2Cslave address, A0h.
See the register map tables for a more complete detail
of each byte’s function, as well as for read/write permis-
sions for each byte.
Shadowed EEPROMIn addition to volatile memory (SRAM) and nonvolatile
memory (EEPROM), the DS1865 also features shadowed
EEPROM. Shadowed EEPROM (SEE) can be configured
as either volatile or nonvolatile memory using the SEEB
bit in Table 02h, Register 80h.
The DS1865 uses shadowed EEPROM memory for key
memory addresses that can be rewritten many times. By
default the shadowed EEPROM bit, SEEB, is not set and
these locations act as ordinary EEPROM. By setting
SEEB, these locations function like SRAM cells, which
allow an infinite number of write cycles without concern
of wearing out the EEPROM. This also eliminates the
requirement for the EEPROM write time, tWR. Because
changes made with SEEB enabled do not affect the
EEPROM, these changes are not retained through
power cycles. The power-up value is the last value writ-
ten with SEEB disabled. This function can be used to
limit the number of EEPROM writes during calibration or
to change the monitor thresholds periodically during nor-
mal operation, helping to reduce the number of times
EEPROM is written. The Memory Organizationdescrip-
tion indicates which locations are shadowed EEPROM.
ATBMISC. CONTROL
BITS
EEPROM
7Fh
I2C SLAVE ADDRESS A0h
00h
FFh
80h
F8h
PW1 LEVEL ACCESS
EEPROM
(120 BYTES)
TABLE 01h
AUXILLARY MEMORYTABLE SELECT BYTE
PASSWORD ENTRY (PWE)
(4 BYTES)
DIGITAL DIAGNOSTIC
FUNCTIONS
7Fh
I2C SLAVE ADDRESS A2h (DEFAULT)
00h
LOWER MEMORYFFh
F7h
C7h
F7h
80h
F8h
C8h
CONFIGURATION AND
CONTROL
NO MEMORY
TABLE 02hFFh
80h
PW2 LEVEL ACCESS
EEPROM
(128 BYTES)
TABLE 03hC7h
80h
MODULATION LUT
TABLE 04hA7h
80h
APC LUT
TABLE 05h9Fh
80h
M4DAC LUT
TABLE 06hDEC
HEX
1277F
255FF
Figure 8. Memory Map
DS1865
PON Triplexer Control and
Monitoring Circuit2C DefinitionsThe following terminology is commonly used to
describe I2C data transfers.
Master Device:The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses and START and STOP conditions.
Slave Devices:Slave devices send and receive data at
the master’s request.
Bus Idle or Not Busy:Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic-high states. When the bus is idle, it often initi-
ates a low-power mode for slave devices.
START Condition:A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition. See Figure 9 for
applicable timing.
STOP Condition:A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition. See Figure 9 for
applicable timing.
Repeated START Condition:The master can use a
repeated START condition at the end of one data trans-
fer to indicate that it will immediately initiate a new data
transfer following the current one. Repeated START
conditions are commonly used during read operations
to identify a specific memory address to begin a data
transfer. A repeated START condition is issued identi-
cally to a normal START condition. See Figure 9 for
applicable timing.
Bit Write:Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold-time requirements (Figure 9). Data is shift-
ed into the device during the rising edge of the SCL.
Bit Read:At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time before the next rising edge of SCL during a
bit read. The device shifts out each bit of data on SDA at
the falling edge of the previous SCL pulse and the data
bit is valid at the rising edge of the current SCL pulse.
Remember that the master generates all SCL clock puls-
es including when it is reading bits from the slave.
Acknowledgement (ACK and NACK):An acknowledge-
ment (ACK) or not acknowledge (NACK) is always the
9th bit transmitted during a byte transfer. The device
receiving data (the master during a read or the slave
during a write operation) performs an ACK by transmit-
ting a zero during the 9th bit. A device performs a
NACK by transmitting a one during the 9th bit. Timing
for the ACK and NACK is identical to all other bit writes.
An ACK is the acknowledgment that the device is prop-
erly receiving data. A NACK is used to terminate a read
sequence or as an indication that the device is not
receiving data.
Byte Write:A byte write consists of 8 bits of information
transferred from the master to the slave (most signifi-
cant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgement is read using the bit read definition.
Byte Read:A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition, and the master transmits an ACK using
the bit write definition to receive additional data bytes.
The master must NACK the last byte read to terminate
communication so the slave returns control of SDA to
the master.
Slave Address Byte:Each slave on the I2Cbus
responds to a slave addressing byte (Figure 9) sent
immediately following a START condition. The slave
address byte contains the slave address in the most sig-
nificant 7 bits and the R/Wbit in the least significant bit.
The DS1865 responds to two slave addresses. The auxil-
iary memory always responds to a fixed I2C slave address,
A0h. The Lower Memory and tables 01h–06h respond to
I2C slave addresses that can be configured to any value
between 00h–FEh using the Device Address byte (Table
02h, Register 8Ch). The user also must set the ASELbit
(Table 02h, Register 89h) for this address to be active. By
writing the correct slave address with R/W= 0, the master
indicates it will write data to the slave. If R/W= 1, the mas-
ter reads data from the slave. If an incorrect slave address
is written, the DS1865 assumes the master is communicat-
ing with another I2C device and ignores the communica-
tions until the next START condition is sent.
Memory Address: During an I2C write operation, the
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is always the second byte trans-
mitted during a write operation following the slave
address byte.
DS1865
PON Triplexer Control and
Monitoring Circuit2C Communication
Writing a Single Byte to a Slave:The master must
generate a START condition, write the I2C slave address
byte (R/W= 0), write the byte of data, and generate a
STOP condition. The master must read the slave’s
acknowledgement during all byte write operations.
Writing Multiple Bytes to a Slave: To write multiplebytes to a slave, the master generates a STARTcondi-
tion, writes the slave address byte (R/W= 0), writes the
memory address, writes up to 8 data bytes, and gener-
ates a STOPcondition. The DS1865 writes 1 to 8 bytes
(1 page or row) with a single write transaction. This is
internally controlled by an address counter that allows
data to be written to consecutive addresses without
transmitting a memory address before each data byte is
sent. The address counter limits the write to one 8-byte
page (one row of the memory map). Attempts to write to
additional pages of memory without sending a STOP
condition between pages result in the address counter
wrapping around to the beginning of the present row.
Example:A 3-byte write starts at address 06h and
writes three data bytes (11h, 22h, and 33h) to three
“consecutive” addresses. The result is that addresses
06h and 07h contain 11h and 22h, respectively, and
the third data byte, 33h, is written to address 00h.
To prevent address wrapping from occurring, the mas-
ter must send a STOPcondition at the end of the page,
then wait for the bus-free or EEPROM-write time to
elapse. Then the master can generate a new START
condition, and write the slave address byte (R/W= 0)
and the first memory address of the next memory row
before continuing to write data.
Acknowledge Polling:Any time an EEPROM location
is written, the DS1865 requires the EEPROM write time
(tW) after the STOP condition to write the contents of
the byte of data to EEPROM. During the EEPROM write
time, the device does not acknowledge its slave
address because it is busy. It is possible to take advan-
tage of that phenomenon by repeatedly addressing the
DS1865, which allows the next page to be written as
soon as the DS1865 is ready to receive the data. The
alternative to acknowledge polling is to wait for a maxi-
mum period of tWto elapse before attempting to write
again to the DS1865.
EEPROM Write Cycles:When EEPROM writes occur
to the memory, the DS1865 writes to all three EEPROM
memory locations, even if only a single byte was modi-
fied. Because all three bytes are written, the bytes that
were not modified during the write transaction are still
subject to a write cycle. This can result in all three bytes
being worn out over time by writing a single byte
repeatedly. The DS1865’s EEPROM write cycles are
specified in the Nonvolatile Memory Characteristics
table. The specification shown is at the worst-case tem-
perature. It can handle approximately 10 times that
many writes at room temperature. Writing to SRAM-
shadowed EEPROM memory with SEEB = 1 does not
count as an EEPROM write cycle when evaluating the
EEPROM’s estimated lifetime.
SDA
SCL
tHD:STA
tLOW
tHIGHtF
tHD:DAT
tSU:DATREPEATED
START
tSU:STA
tHD:STA
tSU:STO
tSP
STOPSTART
tBUF
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).Figure 9. I2C Timing Diagram
DS1865
PON Triplexer Control and
Monitoring Circuit
Reading a Single Byte from a Slave:Unlike the write
operation that uses the memory address byte to define
where the data is to be written, the read operation occurs
at the present value of the memory address counter. To
read a single byte from the slave, the master generates a
STARTcondition, writes the slave address byte with R/W
= 1, reads the data byte with a NACK to indicate the end
of the transfer, and generates a STOPcondition.
Manipulating the Address Counter for Reads:A
dummy write cycle can be used to force the address
pointer to a particular value. To do this, the master gen-
erates a STARTcondition, writes the slave address byte
(R/W= 0), writes the memory address where it desires to
read, generates a repeated STARTcondition, writes the
slave address byte (R/W= 1), reads data with ACK or
NACK as applicable, and generates a STOPcondition.
DS1865
PON Triplexer Control and
Monitoring Circuit
LOWER MEMORYWORD 0WORD 1WORD 2WORD 3ROW
(HEX)
ROW
NAMEBYTE 0/8BYTE 1/9BYTE 2/ABYTE 3/BBYTE 4/CBYTE 5/DBYTE 6/EBYTE 7/F<1>THRESHOLD0TEMP ALARM HITEMP ALARM LOTEMP WARN HITEMP WARN LO<1>THRESHOLD1VCC ALARM HIVCC ALARM LOVCC WARN HIVCC WARN LO<1>THRESHOLD2MON1 ALARM HIMON1 ALARM LOMON1 WARN HIMON1 WARN LO<1>THRESHOLD3MON2 ALARM HIMON2 ALARM LOMON2 WARN HIMON2 WARN LO<1>THRESHOLD4MON3 ALARM HIMON3 ALARM LOMON3 WARN HIMON3 WARN LO<1>THRESHOLD5MON4 ALARM HIMON4 ALARM LOMON4 WARN HIMON4 WARN LO<1>PW2 EEEEEEEEEEEEEEEEEE<1>PW2 EEEEEEEEEEEEEEEEEE<1>PW2 EEEEEEEEEEEEEEEEEE<1>PW2 EEEEEEEEEEEEEEEEEE<1>PW2 EEEEEEEEEEEEEEEEEE<1>PW2 EEEEEEEEEEEEEEEEEE<2>ADC VALUES0TEMP VALUEVCC VALUEMON1 VALUEMON2 VALUE<0> ADC VALUES1<2>MON3 VALUE<2> MON4 VALUE<2>RESERVED<0>STATUS<3>UPDATE<2>ALARM/WARNALARM3ALARM2ALARM1ALARM0WARN3WARN2RESERVED<0>TABLE SELECT<2>DOUT<2>DIN<6>RESERVED<6>PWE MSB<6>PWE LSB<5>TBL SEL
ACCESS CODE<0><1><2><3><4><5><6><7><8><9><10><11>Read AccessAllAllAllPW2AllN/APW1PW2N/APW2All
Write Accessee eachi t /b yt eep ar at el y PW2N/A
Al l andDS1865
har dwar e
PW2 +mode bitAllAllPW1PW2PW2N/APW1
Lower Memory Register MapThis register map shows each byte/word in terms of the
row it is on in the memory. The first byte in the row is
located in memory at the hexadecimal row address in
the left-most column. Each subsequent byte on the row
is one/two memory locations beyond the previous
byte/word’s address. A total of 8 bytes are present on
each row. For more information about each of these
bytes, see the corresponding register description in the
following tables.
Register Maps
DS1865
PON Triplexer Control and
Monitoring Circuit
Table 01h Register Map
TABLE 01h (PW1)WORD 0WORD 1WORD 2WORD 3ROW
(HEX)
ROW
NAMEBYTE 0/8BYTE 1/9BYTE 2/ABYTE 3/BBYTE 4/CBYTE 5/DBYTE 6/EBYTE 7/F<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<11>ALARM TRAPALARM3ALARM2ALARM1ALARM0WARN3WARN2RESERVED
ACCESS CODE<0><1><2><3><4><5><6><7><8><9><10><11>Read AccessAllAllAllPW2AllN/APW1PW2N/APW2All
Write Accessee eachi t /b yt eep ar at el y PW2N/A
Al l andDS1865
har dwar e
PW2 +mode bitAllAllPW1PW2PW2N/APW1
DS1865
PON Triplexer Control and
Monitoring Circuit
Table 02h Register Map
TABLE 02h (PW2)WORD 0WORD 1WORD 2WORD 3ROW
(HEX)
ROW
NAMEBYTE 0/8BYTE 1/9BYTE 2/ABYTE 3/BBYTE 4/CBYTE 5/DBYTE 6/EBYTE 7/F<0> CONFIG0<8>MODE<4>T INDEX<4> MOD DAC<4> APC DAC<4> V INDEX<4> M4DAC<10> D EV IC E ID <10> DEVICE VER<8> CONFIG1UPDATE
RATECONFIGSTARTUP
STEP
MOD
RANGING
DEVICE
ADDRESS
COMP
RANGINGRSHIFT1RSHIFT0<8> SCALE0RESERVEDVCC SCALEMON1 SCALEMON2 SCALE<8> SCALE1MON3 SCALEMON4 SCALERESERVEDRESERVED<8> OFFSET0RESERVEDVCC OFFSETMON1 OFFSETMON2 OFFSET<8> OFFSET1MON3 OFFSETMON4 OFFSETRESERVEDINTERNAL TEMP OFFSET*<9> P WD V ALU E PW1 MSWPW1 LSWPW2 MSWPW2 LSW<8> INTERRUPTFETG EN1FETG EN0TX-F EN1TX-F EN0HTXPLTXPHBIASMAX IBIAS<8> CNTL OUTDPURESERVEDRESERVEDRESERVEDDAC1RESERVEDRESERVEDM 4 LU T C N TL
C8-F7EMPTYEMPTYEMPTYEMPTYEMPTYEMPTYEMPTYEMPTYEMPTY<0> M AN IBIAS <4> M AN IBIAS 1
<4> M AN IBIAS 0
<4> M AN _C NTL<10> BIAS DAC 1
<10> BIAS DAC 0RE SE RV ED RE SE RV ED RE SE RV ED
ACCESS CODE<0><1><2><3><4><5><6><7><8><9><10><11>Read AccessAllAllAllPW2AllN/APW1PW2N/APW2All
Write Accessee eachi t /b yt es ep ar at el y PW2N/A
Al l and
DS1865
har dwar e
PW2 +
mode bitAllAllPW1PW2PW2N/APW1
*The final result must be XORed with BB40h before writing to this register.
DS1865
PON Triplexer Control and
Monitoring Circuit
Table 03h Register Map
TABLE 03h (PW3)WORD 0WORD 1WORD 2WORD 3ROW
(HEX)
ROW
NAMEBYTE 0/8BYTE 1/9BYTE 2/ABYTE 3/BBYTE 4/CBYTE 5/DBYTE 6/EBYTE 7/F<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE
ACCESS CODE<0><1><2><3><4><5><6><7><8><9><10><11>Read AccessAllAllAllPW2AllN/APW1PW2N/APW2All
Write Accessee eachi t /b yt eep ar at el y PW2N/A
Al l andDS1865
har dwar e
PW2 +mode bitAllAllPW1PW2PW2N/APW1
DS1865
PON Triplexer Control and
Monitoring Circuit
Table 04h Register Map
TABLE 04h (MOD LUT)WORD 0WORD 1WORD 2WORD 3ROW
(HEX)
ROW
NAMEBYTE 0/8BYTE 1/9BYTE 2/ABYTE 3/BBYTE 4/CBYTE 5/DBYTE 6/EBYTE 7/F<8>LUT4MODMODMODMODMODMODMODMOD<8>LUT4MODMODMODMODMODMODMODMOD<8>LUT4MODMODMODMODMODMODMODMOD<8>LUT4MODMODMODMODMODMODMODMOD<8>LUT4MODMODMODMODMODMODMODMOD<8>LUT4MODMODMODMODMODMODMODMOD<8>LUT4MODMODMODMODMODMODMODMOD<8>LUT4MODMODMODMODMODMODMODMOD<8>LUT4MODMODMODMODMODMODMODMOD
ACCESS CODE<0><1><2><3><4><5><6><7><8><9><10><11>Read AccessAllAllAllPW2AllN/APW1PW2N/APW2All
Write Accessee eachi t /b yt es ep ar at el y PW2N/A
Al l and
DS1865
har dwar e
PW2 +
mode bitAllAllPW1PW2PW2N/APW1
Table 05h Register Map
TABLE 05h (APC LUT)WORD 0WORD 1WORD 2WORD 3ROW
(HEX)
ROW
NAMEBYTE 0/8BYTE 1/9BYTE 2/ABYTE 3/BBYTE 4/CBYTE 5/DBYTE 6/EBYTE 7/F<8>LUT5APC REFAPC REFAPC REFAPC REFAPC REFAPC REFAPC REFAPC REF<8>LUT5APC REFAPC REFAPC REFAPC REFAPC REFAPC REFAPC REFAPC REF<8>LUT5APC REFAPC REFAPC REFAPC REFAPC REFAPC REFAPC REFAPC REF<8>LUT5APC REFAPC REFAPC REFAPC REFAPC REFAPC REFAPC REFAPC REF<8>LUT5APC REFAPC REFAPC REFAPC REFRE SE RV ED RE SE RV ED RE SE RV ED RE SE RV ED
ACCESS CODE<0><1><2><3><4><5><6><7><8><9><10><11>Read AccessAllAllAllPW2AllN/APW1PW2N/APW2All
Write Accessee eachi t /b yt es ep ar at el y PW2N/A
Al l and
DS1865
har dwar e
PW2 +
mode bitAllAllPW1PW2PW2N/APW1
DS1865
PON Triplexer Control and
Monitoring Circuit
Table 06h Register Map
TABLE 06h (LUT FOR M4DAC)WORD 0WORD 1WORD 2WORD 3ROW
(HEX)
ROW
NAMEBYTE 0/8BYTE 1/9BYTE 2/ABYTE 3/BBYTE 4/CBYTE 5/DBYTE 6/EBYTE 7/F<8>LUT6M4DACM4DACM4DACM4DACM4DACM4DACM4DACM4DAC<8>LUT6M4DACM4DACM4DACM4DACM4DACM4DACM4DACM4DAC<8>LUT6M4DACM4DACM4DACM4DACM4DACM4DACM4DACM4DAC<8>LUT6M4DACM4DACM4DACM4DACM4DACM4DACM4DACM4DAC
ACCESS CODE<0><1><2><3><4><5><6><7><8><9><10><11>Read AccessAllAllAllPW2AllN/APW1PW2N/APW2All
Write Accessee eachb i t /b yt eep ar at el y PW2N/A
Al l and
DS1865
har dwar e
PW2 +
mode bitAllAllPW1PW2PW2N/APW1
DS1865
PON Triplexer Control and
Monitoring Circuit
AUX A0h Memory Register Map
AUX MEMORY (A0h)WORD 0WORD 1WORD 2WORD 3ROW
(HEX)
ROW
NAMEBYTE 0/8BYTE 1/9BYTE 2/ABYTE 3/BBYTE 4/CBYTE 5/DBYTE 6/EBYTE 7/F<5>AUX EEEEEEEEEEEEEEEEEE<5>AUX EEEEEEEEEEEEEEEEEE<5>AUX EEEEEEEEEEEEEEEEEE<5>AUX EEEEEEEEEEEEEEEEEE<5>AUX EEEEEEEEEEEEEEEEEE<5>AUX EEEEEEEEEEEEEEEEEE<5>AUX EEEEEEEEEEEEEEEEEE<5>AUX EEEEEEEEEEEEEEEEEE<5>AUX EEEEEEEEEEEEEEEEEE<5>AUX EEEEEEEEEEEEEEEEEE<5>AUX EEEEEEEEEEEEEEEEEE<5>AUX EEEEEEEEEEEEEEEEEE<5>AUX EEEEEEEEEEEEEEEEEE<5>AUX EEEEEEEEEEEEEEEEEE<5>AUX EEEEEEEEEEEEEEEEEE<5>AUX EEEEEEEEEEEEEEEEEE
ACCESS CODE<0><1><2><3><4><5><6><7><8><9><10><11>Read AccessAllAllAllPW2AllN/APW1PW2N/APW2All
Write Accessee eachi t /b yt es ep ar at el y PW2N/A
Al l and
DS1865
har dwar e
PW2 +
mode bitAllAllPW1PW2PW2N/APW1
DS1865
PON Triplexer Control and
Monitoring Circuit
Lower Memory, Register 00h to 01h: Temp Alarm Hi
Lower Memory, Register 04h to 05h: Temp Warn HiFACTORY DEFAULT:7FFFh
READ ACCESSAll
WRITE ACCESSPW2
MEMORY TYPE:Nonvolatile (SEE)
00h, 04hS26252423222120
01h, 05h2-12-22-32-42-52-62-72-8
bit7bit0
Temperature measurement updates above this two’s complement threshold will set its corresponding alarm or warning bit.
Temperature measurement updates equal to or below this threshold will clear its alarm or warning bit.
Lower Memory, Register 02h to 03h: Temp Alarm Lo
Lower Memory, Register 06h to 07h: Temp Warn LoFACTORY DEFAULT:8000h
READ ACCESSAll
WRITE ACCESSPW2
MEMORY TYPE:Nonvolatile (SEE)
02h, 06hS26252423222120
03h, 07h2-12-22-32-42-52-62-72-8
bit7bit0
Temperature measurement updates above this two’s complement threshold will set its corresponding alarm or warning bit.
Temperature measurement updates equal to or below this threshold will clear its alarm or warning bit.
Lower Memory Registers
DS1865
PON Triplexer Control and
Monitoring Circuit
Lower Memory, Register 08h to 09h: Vcc Alarm Hi
Lower Memory, Register 0Ch to 0dh: Vcc Warn Hi
Lower Memory, Register 10h to 11h: MON1 Alarm Hi
Lower Memory, Register 14h to 15h: MON1 Warn Hi
Lower Memory, Register 18h to 19h: MON2 Alarm Hi
Lower Memory, Register 1Ch to 1Dh: MON2 Warn Hi
Lower Memory, Register 20h to 21h: MON3 Alarm Hi
Lower Memory, Register 24h to 25h: MON3 Warn Hi
Lower Memory, Register 28h to 29h: MON4 Alarm Hi
Lower Memory, Register 2Ch to 2Dh: MON4 Warn HiFACTORY DEFAULT:FFFFh
READ ACCESSAll
WRITE ACCESSPW2
MEMORY TYPE:Nonvolatile (SEE)
08, 0C, 10,
14, 18, 1C,
20, 24, 28,
2Ch152142132122112102928
09, 0D, 11,
15, 19, 1D,
21, 25, 29,
2Dh726252423222120
bit7bit0
Voltage measurement updates above this unsigned threshold will set its corresponding alarm or warning bit.
Voltage measurements equal to or below this threshold will clear its alarm or warning bit.
DS1865
PON Triplexer Control and
Monitoring Circuit
Lower Memory, Register 30h to 5Fh: PW2 EEFACTORY DEFAULT:00h
READ ACCESSAll
WRITE ACCESSPW2
MEMORY TYPE:Nonvolatile (EE)
30h to 5FhEEEEEEEEEEEEEEEE
bit7bit0
PW2 level access controlled EEPROM.
Lower Memory, Register 0Ah to 0Bh: Vcc Alarm Lo
Lower Memory, Register 0Eh to 0Fh: Vcc Warn Lo
Lower Memory, Register 12h to 13h: MON1 Alarm Lo
Lower Memory, Register 16h to 17h: MON1 Warn Lo
Lower Memory, Register 1Ah to 1Bh: MON2 Alarm Lo
Lower Memory, Register 1Eh to 1Fh: MON2 Warn Lo
Lower Memory, Register 22h to 23h: MON3 Alarm Lo
Lower Memory, Register 26h to 27h: MON3 Warn Lo
Lower Memory, Register 2Ah to 2Bh: MON4 Alarm Lo
Lower Memory, Register 2Eh to 2Fh: MON4 Warn LoFACTORY DEFAULT:0000h
READ ACCESSAll
WRITE ACCESSPW2
MEMORY TYPE:Nonvolatile (SEE)
0A, 0E, 12,
16, 1A, 1E,
22, 26, 2A,
2Eh152142132122112102928
0B, 0F, 13,
17, 1B, 1F,
23, 27, 2B,
2Fh726252423222120
bit7bit0
Voltage measurement updates above this unsigned threshold will set its corresponding alarm or warning bit.
Voltage measurements equal to or below this threshold will clear its alarm or warning bit.
DS1865
PON Triplexer Control and
Monitoring Circuit
Lower Memory, Register 60h to 61h: Temp ValuePOWER-ON VALUE0000h
READ ACCESSAll
WRITE ACCESSN/A
MEMORY TYPE:Volatile
60hS26252423222120
61h2-12-22-32-42-52-62-72-8
bit7bit0
Signed two’s complement direct-to-temperature measurement.
Lower Memory, Register 6Ch to 6D: ReservedPOWER-ON VALUE00h
READ ACCESSAll
WRITE ACCESSN/A
MEMORY TYPE:
6C, 6Dh000000000
bit7bit0
These registers are reserved. The value when read is 00h.
Lower Memory, Register 62h to 63h: VCC Value
Lower Memory, Register 64h to 65h: MON1 Value
Lower Memory, Register 66h to 67h: MON2 Value
Lower Memory, Register 68h to 69h: MON3 Value
Lower Memory, Register 6Ah to 6Bh: MON4 ValuePOWER-ON VALUE0000h
READ ACCESSAll
WRITE ACCESSN/A
MEMORY TYPE:Volatile
62, 64, 66,
68, 6Ah2152142132122112102928
63, 65, 67,
69, 6Bh2726252423222120
bit7bit0
Left-justified unsigned voltage measurement.
DS1865
PON Triplexer Control and
Monitoring Circuit
Lower Memory, Register 6Eh: StatusPOWER-ON VALUEx000 0x0x b
READ ACCESSAll
WRITE ACCESSSee Below
MEMORY TYPE:Volatiler i te AccessN/AALLN/AALLALLN/AN/AN/A
6EhFETG
STATUS
SOFT
FETGRESERVEDTX-F
RESET
SOFT
TX-D
TX-F
STATUS
LOS
STATUSRDYB
bit7bit0
bit7
FETG STATUS: Reflects the active state of FETG. The FETG-DIR bit in Table 02h, Register 89hdefines the polarity of FETG.
0 = Normal operation. Bias and modulation outputs are enabled.
1 = The FETG output is active. Bias and modulation outputs are disabled.
bit6
SOFT FETG:0 = (Default)
1 = Forces the bias and modulation outputs to their off states and asserts the FETG output.
bit5
RESERVED (Default = 0)bit4
TX-F RESET:0 = Does not affect the TX-F output. (Default)
1 = Resets the latch for the TX-F output. This bit is self-clearing after the reset.
bit3
SOFT TX-D: This bit allows a software control is identical to the TX-D pin. See the section on TX-D forfurther information. Its value is wired-ORed with the logic value of the TX-D pin.
0 = Internal TX-D signal is equal to external TX-D pin.
1 = Internal TX-D signal is high.
bit2
TX-F STATUS: Reflects the active state of TX-F.0 = TX-F pin is not active.
1 = TX-F pin is active.
bit1
LOS STATUS: Loss of Signal. Reflects the logic level of the D0 input pin. Note that with the use of theMUX LOSI and INV LOSI bits (Table 02h, Register C0h), the D0 pin is controlled by the LOSI pin.
0 = D0 is logic-low.
1 = D0 is logic-high.
bit0
RDYB: Ready Bar.0 = VCC is above POA.
1 = VCC is below POA or too low to communicate over the I2C bus.
DS1865
PON Triplexer Control and
Monitoring Circuit
Lower Memory, Register 6Fh: UpdatePOWER-ON VALUE00h
READ ACCESSAll
WRITE ACCESSAll + DS1865 Hardware
MEMORY TYPE:Volatile
6FhTEMP RDYVCC RDYMON1 RDYMON2 RDYMON3 RDYMON4 RDYRESERVEDRESERVED
bit7bit0
Update of completed conversions. At power-on, these bits are cleared and are set as each conversion is completed.
These bits can be cleared so that a completion of a new conversion is verified.
