DS1863E+ ,Burst-Mode PON Controller With Integrated MonitoringFeaturesThe DS1863 controls and monitors all the burst-mode♦ Meets BPON, GPON, and GEPON Timingtran ..
DS1863E+T&R ,Burst-Mode PON Controller With Integrated MonitoringApplications♦ Two-Level Password Access to ProtectBPON, GPON, and GEPON Burst-Mode TransmittersCali ..
DS1863K ,Burst-Mode PON Controller With Integrated MonitoringDS186319-4883; Rev 2; 8/09Burst-Mode PON ControllerWith Integrated Monitoring
DS1863K+ ,Burst-Mode PON Controller With Integrated MonitoringApplications♦ Two-Level Password Access to ProtectBPON, GPON, and GEPON Burst-Mode TransmittersCali ..
DS1865 ,PON Triplexer Control and Monitoring CircuitApplicationsMaskable Laser Shutdown CapabilityOptical Triplexers with GEPON, BPON, or GPON♦ Two-Lev ..
DS1865K ,PON Triplexer Control and Monitoring CircuitELECTRICAL CHARACTERISTICS(V = +2.85V to +3.9V, T = -40°C to +95°C, unless otherwise noted.)CC APAR ..
DS1863-DS1863E+-DS1863E+T&R-DS1863K-DS1863K+
Burst-Mode PON Controller With Integrated Monitoring
General DescriptionThe DS1863 controls and monitors all the burst-mode
transmitter and video receiver biasing functions for a
passive optical network (PON) transceiver. It has an
APC loop with tracking-error compensation that pro-
vides the reference for the laser driver’s bias current
and a temperature-indexed lookup table (LUT) that
controls the modulation current. It continually monitors
for high output current, high bias current, and low and
high transmit power with its internal fast comparators to
ensure that laser shutdown for eye safety requirements
are met without adding external components. Five ADC
channels monitor VCC, internal temperature, and three
external monitor inputs (MON1, MON2, MON3) that can
be used to meet transmitter and receive monitoring
requirements.
ApplicationsBPON, GPON, and GEPON Burst-Mode Transmitters
Laser Control and Monitoring
Broadband Local Access
FeaturesMeets BPON, GPON, and GEPON Timing
Requirements for Burst-Mode TransceiversBias Current Control Provided by APC Loop with
Tracking Error CompensationModulation Current Is Controlled by a
Temperature-Indexed Lookup TableSupports 0dB, -3dB, -6dB Power Leveling
Settings with No Additional CalibrationInternal Direct-to-Digital Temperature SensorFive Analog Monitor Channels: Temperature, VCC,
MON1, MON2, and MON3Comprehensive Fault Management System with
Maskable Laser Shutdown CapabilityTwo-Level Password Access to Protect
Calibration Data120 Bytes of Password 1 (PW1) Protected
Nonvolatile Memory128 Bytes of Password 2 (PW2) Protected
Nonvolatile MemoryI2C-Compatible Interface for Calibration and
MonitoringOperating Voltage: 2.85V to 3.9VOperating Temperature: -40°C to +95°C16-Pin, Lead-Free TSSOP Package
DS1863
Burst-Mode PON Controller
With Integrated Monitoring19-4883; Rev 2; 8/09
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
Ordering Information
PARTTEMP RANGEPIN-PACKAGEDS1863E+-40°C to +95°C16 TSSOP
DS1863E+T&R-40°C to +95°C16 TSSOP
VCC
BMD
MOD
BIASTX-F
N.C.
TX-D
BEN
TOP VIEW
GND
MON3
MON2SCL
SDA8MON1GND
FETG
TSSOP
(173 mils)DS1863
Pin Configuration
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS(TA= -40°C to +95°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage on VCC, SDA and SCL Pin Relative
to Ground....................................................................-0.5V to 6V
Voltage on BEN, TX-D, TX-F, MON1–MON3,
BMD Relative to Ground...............................-0.5V to VCC+ 0.5V
(subject to not exceeding +6V)
Operating Temperature Range...........................-40°C to +95°C
Programming Temperature Range.........................0°C to +70°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature...................See J-STD-020 specification
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSupply VoltageVCC(Note 1)+2.853.9Vi gh- Level Inp ut V ol tage ( SD A, S C L, BE N) VIH:10.7 x VCCVCC + 0.3V
Low- Level Inp ut V oltag e ( S DA, SC L, BE N )VIL:1-0.30.3 x VCCV
High-Level Input Voltage (TX-D)VIH:22.0VCC + 0.3V
Low-Level Input Voltage (TX-D)VIL:2-0.30.8V
ELECTRICAL CHARACTERISTICS(VCC= +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSupply CurrentICC(Notes 1, 2)57mA
Output Leakage (SDA, TX-F)ILO1µA
IOL = 4mA0.4Low-Level Output Voltage
(SDA, TX-F, FETG)VOLIOL = 6mA0.6V
High-Level Output Voltage (FETG)VOHIOH = 4mA (Note 2)VCC – 0.4V
FETG Before Recall(Note 3)10100nA
Inp ut Leakag e C ur r ent ( S C L, BE N , TX - D ) ILI:11µA
Digital Power-On ResetPOD1.02.2V
Analog Power-On ResetPOA2.12.75V
ANALOG INPUT CHARACTERISTICS (BMD)(VCC= +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSBMD Full-Scale Voltage RangeVAPC(Note 4)2.5V
Resolution(Note 4)8bits
VAPC ErrorTA = +25°C (Note 5)-1.75+1.75%FS
VAPC Integral Nonlinearity-1+1LSB
VAPC Differential Nonlinearity-1+1LSB
VAPC Temp Drift-2.5+2.5%FS
Input Resistance3550.065kΩ
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
ANALOG OUTPUT CHARACTERISTICS(VCC= +2.85V to +3.9V,TA= -40°C to +95°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSBIAS CurrentIBIAS(Note 1)1.2mA
IBIAS Shutdown CurrentIB IA S : OF F 10100nA
Voltage at IBIAS0.71.21.4V
MOD Full-Scale VoltageVMOD(Note 6)1.25V
MOD Output Impedance(Note 7)3.14kΩ
VMOD ErrorTA = +25°C (Note 8)-1.25+1.25%FS
VMOD Integral Nonlinearity-1+1LSB
VMOD Differential Nonlinearity-1+1LSB
VMOD Temperature Drift-2+2%FS
CONTROL LOOP AND QUICK-TRIP TIMING CHARACTERISTICS(VCC= +2.85V to +3.9V,TA= -40°C to +95°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSFirst BMD Sample Following BENtFIRST(Note 9)
Remaining Updates During BENtREP(Note 9)
BEN High TimetBEN:HIGH420ns
BEN Low TimetBEN:LOW96ns
BIAS and MOD Turn-Off DelaytOFF5µs
BIAS and MOD Turn-On DelaytON5µs
FETG Turn-On DelaytFETG:ON5µs
FETG Turn-Off DelaytFETG:OFF5µs
Binary Search TimetSEARCH(Note 10)513BIAS
Samples
ADC Round-Robin TimetRR65ms
ANALOG VOLTAGE MONITORING(VCC= +2.85V to +3.9V,TA= -40°C to +95°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSADC Resolution 13 Bits
Input/Supply Accuracy
(MON1, MON2, MON3, VCC)ACC At factory setting 0.25 0.5 %FS
Update Rate for Temperature, MON1,
MON2, MON3, VCCtFRAME:1 52 70 ms
Input/Supply Offset
(MON1, MON2, MON3, VCC)VOS (Note 11) 0 5 LSB
MON1, MON2, MON3 2.5 Factory
Setting VCCFull scales are user programmable 6.5536 V
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
NONVOLATILE MEMORY CHARACTERISTICS(VCC= +2.85V to +3.9V,unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSEEPROM Write Cycles+70°C50,000
2C AC ELECTRICAL CHARACTERISTICS(VCC = +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted, see Figure 9.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSCL Clock FrequencyfSCL(Note 12)0400kHz
Clock Pulse-Width LowtLOW1.3µs
Clock Pulse-Width HightHIGH0.6µs
Bus Free Time Between STOP and
START ConditiontBUF1.3µs
START Hold TimetHD:STA0.6µs
START Setup TimetSU:STA0.6µs
Data-In Hold TimetHD:DAT00.9µs
Data-In Setup TimetSU:DAT100ns
Rise Time of Both SDA and
SCL SignalstR(Note 13)20 + 0.1CB300ns
Fall Time of Both SDA and
SCL SignalstF(Note 13)20 + 0.1CB300ns
STOP Setup TimetSU:STO0.6µs
Capacitive Load for Each Bus LineCB(Note 13)400pF
EEPROM Write TimetW(Note 14)20ms
Note 1:All voltages are referenced to ground. Currents into the IC are positive and out of the IC are negative.
Note 2:Digital Inputs are at rail. FETG is disconnected SDA = SCL = 1.
Note 3:See the Safety Shutdown (FETG) Output section for details.
Note 4:Eight ranges allow the full-scale range to change from 625mV to 2.5V.
Note 5:This specification applies to the expected full-scale value for the selected range. See the Comp Ranging byte for available
full-scale ranges.
Note 6:Eight ranges allow the full-scale range to change from 312.5mV to 1.25V.
Note 7:The output impedance of the DS1863 is proportional to its scale setting. For instance, if using the 1/2 scale, the output
impedance would be 1.5kΩ.
Note 8:This specification applies to the expected full-scale value for the selected range. See the Mod Ranging byte for available
full-scale ranges.
Note 9:See the APC/Quick-Trip Sample Timingsection for details.
Note 10:Assuming an appropriate initial step is programmed that would cause the power to exceed the APC set point within 4
steps, the bias current will be within 1% within the time specified by the binary search time.
Note 11:Guaranteed by design.
Note 12:I2Cinterface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I2Cstan-
dard-mode timing.
Note 13:CB—total capacitance of one bus line in picofarads.
Note 14:EEPROM write begins after a STOP condition occurs.
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Typical Operating Characteristics(VCC= 3.3V, TA= +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
DS1863 toc01
VCC (V)
SUPPLY CURRENT (mA)
SDA = SCL = VCC
+95°C
-40°C
+25°C
SUPPLY CURRENT vs. TEMPERATURE
DS1863 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
VCC = 2.85V
VCC = 3.9V
SDA = SCL = VCC
MOD DNL
DS1863 toc03
MOD INPUT CODE (DEC)
MOD DNL (LSB)
MOD INL
DS1863 toc04
MOD INPUT CODE (DEC)
MOD INL (LSB)
CALCULATED AND DESIRED % CHANGE
IN VMOD vs. MOD RANGING
DS1863 toc05
MOD RANGING VALUE (DEC)
CHANGE IN V
MOD
(%)
DESIRED VALUE
CALCULATED VALUE
DESIRED AND CALCULATED CHANGE
IN VBMD vs. COMP RANGING
DS1863 toc06
COMP RANGING (DEC)
CHANGE IN V
BMD
(%)
DESIRED VALUE
CALCULATED VALUE
MON1–3 DNL
DS1863 toc07
MON1–3 INPUT VOLTAGE (V)
MON1–3 DNL (LSB)
USING FACTORY-PROGRAMMED
FULL-SCALE VALUE OF 2.5V
MON1–3 INL
DS1863 toc08
MON1–3 INPUT VOLTAGE (V)
MON1–3 INL (LSB)
USING FACTORY-PROGRAMMED
FULL-SCALE VALUE OF 2.5V
VBMD INL vs. APC INDEX
DS1863 toc09
APC INDEX (DEC)
BMD
INL (LSB)
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Pin Description
PINNAMEDESCRIPTIONBENBurst Enable Input. Triggers the sampling of the APC and Quick-trip monitors.TX-DTransmit Disable Input. Disables BIAS and MOD outputs.N.C.No ConnectionTX-FTransmit Fault Output. Open-drain.FETGOutput to FET Gate. Signals an external N or P Channel MOSFET to enable/disable the laser’s current.SDAI2C Serial Data I/OSCLI2C Serial Clock InputGNDGroundMON1MON2MON3
External Analog Inputs. The voltage at these pins is digitized by the internal analog-to-digital converter
and can be read through the I2C interface. Alarm and warning values can be assigned to interrupt the
processor based on the ADC result.GNDGroundBIASBias Current Output. This current DAC generates the bias current reference for the MAX3643.MODModulation Output Voltage. This 8-bit voltage output has 8 full-scale ranges from 1.25V to 0.3125V.
This pin is connected to the MAX3643’s VMSET input to control the modulation current.BMDMonitor Diode Input (Feedback Voltage, Transmit Power Monitor)VCCPower Supply Input
DS1863
Burst-Mode PON Controller
With Integrated MonitoringBMD
BEN
MON2
MON1
MON3
SCL
SDA
GND
VCC
TX-D
BIAS
MOD
FETG
TX-F
HBIAS QUICK
TRIP LIMIT
HTXP QUICK
TRIP LIMIT
LTXP QUICK
TRIP LIMIT
APC SETPOINT FROM
TRACKING ERROR TABLE
LATCH
ENABLE
VCC
TEMP
SENSOR
I2C
INTERFACE
SAMPLE
CONTROL
8-BIT DAC
W/SCALINGDIGITAL APC
INTEGRATOR
13-BIT
DAC
ANALOG MUX
MODULATION LOOKUP
TABLE (TABLE 04h)
8-BIT DAC
W/SCALING
MAX BIAS
QUICKTRIP
INTERRUPT
MASK
INTERRUPT
LATCH
INTERRUPT
MASK
INTERRUPT
LATCH
POWER ON ANALOG
VCC > VPOA
NONMASKABLE
INTERRUPT
13-BIT
ADC
DS1863 MEMORY ORGANIZATION
SRAM RESET
RIGHT
SHIFT
TABLE 01h
EEPROM
PW1
USER MEMORY
AND ALARM
TRAPS
TABLE 02h
EEPROM
CONFIGURATION
AND
CALIBRATION
TABLE 03h
EEPROM
PW2
USER MEMORY
LOWER MEMORY
EEPROM/SRAM
ADC CONFIG/RESULTS
SYSTEM STATUS BITS
ALARM/WARNING COMPARISON RESULTS/THRESHOLDS
TABLE 04h
EEPROM
MODULATION
LUT
TABLE 05h
EEPROM
TRACKING
ERROR LUT
DIGITAL LIMIT
COMPARATOR FOR
ADC RESULTS
DS1863
MUX
MUX
MUX
Block Diagram
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Detailed DescriptionThe DS1863 integrates the control and monitoring func-
tionality required to implement a PON system using
Maxim’s MAX3643 compact burst mode laser driver.
The compact laser driver solution offers a considerable
cost benefit by integrating control and monitoring fea-
tures in low power CMOS process, while leaving only
the high speed portions to the laser driver IC.
APC ControlBIAS current is controlled by an Average Power Control
(APC) loop. The APC loop uses digital techniques to
overcome the difficulties associated with controlling
burst mode systems.
The APC loop’s feedback is the monitor diode (BMD)
current, which is converted to a voltage using an exter-
nal resistor. The feedback voltage is compared to an 8-
bit scaleable voltage reference, which determines the
APC set point of the system. Scaling of the reference
voltage along with the modulation output can be uti-
lized to implement GPON power leveling.
The DS1863 has a Lookup Table to allow the APC set
point to change as a function of temperature to com-
pensate for Tracking Error (TE). The TE LUT (Table
05h), has 36 entries that determine the APC setting in
4°C windows between -40°C to +100°C.
Ranging of the APC DAC is possible by programming a
single byte in Table 02h.
Typical Operating CircuitBEN+
BEN-
DIS
MAX3643
IN-
IN+
OUT-
BIAS-
BIAS+
MDIN
COMPACT BURST MODE
LASER DRIVER
DS1863
BURST MODE
MONITOR/CONTROL CIRCUIT
MDOUT
OUT+
VCC
TX-F
TX-D
SCL
SDA
MON2
MON3
FETG
MON1
BMD
3.3V
VMSETMODSETVREFIMAXGNDBIASSETBENOUT
MODBIAS
BEN
BIASMONVBEST
TRANSMIT POWER
RECEIVE POWER
I2C COMMUNICATION
FAULT OUTPUT
DISABLE INPUT
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Modulation ControlThe MOD voltage is controlled using an internal tem-
perature indexed Lookup Table.
The MOD output is an 8-bit scaleable voltage output that
interfaces with the MAX3643’s VMSET input. An external
resistor to ground from the MAX3643’s MODSET pin sets
the maximum current the voltage at VMSET input can
produce for a given output range. This resistor value
should be chosen to produce the maximum modulation
current the laser type requires over temperature. The
modulation LUT can be programmed in 2°C increments
over the -40°C to +102°C range to provide temperature
compensation for the laser’s modulation. The modulation
DAC’s scaling can be used (with APC scaling) to imple-
ment GPONpower leveling with a single LUT that works
for all three power levels.
Ranging of the MOD DAC is possible by programming
a single byte in Table 02h.
BIAS and MOD Output During
Initial Power-UpOn power-up the modulation and bias outputs will
remain off until VCCis above VPOA, a temperature con-
version has been completed, and if the VCCLO ADC
alarm is enabled, then a VCCconversion above the
customer defined VCClow alarm level has cleared the
VCClow alarm. Once all of these conditions are satis-
fied, the MOD output will be enabled with the value
determined by the temperature conversion and the
modulation LUT.
When the MOD output is enabled and BEN is high, the
IBIASDAC output will be turned on to a value equal to
ISTEP(see above). The start-up algorithm checks if this
bias current causes a feedback voltage above the APC
set-point, and if it does not it continues increasing the
IBIASby ISTEPuntil the APC set-point is exceeded.
When the APC set point is exceeded, the device will
begin a binary search to quickly reach the bias current
corresponding to the proper power level. After the bina-
ry search is completed the APC integrator is enabled,
and single LSB steps are taken to tightly control the
average power.
All quick-trip and ADC alarm flags are masked until the
binary search is completed. However, the BIAS MAX
alarm is monitored during this time to prevent the bias
output from exceeding MAX IBIAS. During the bias cur-
rent initialization, the bias current is not allowed to
exceed MAX IBIAS. If this occurs during the ISTEP
sequence then the binary search routine is enabled. If
MAX IBIASis exceeded during the binary search, then
the next smaller step is activated. ISTEPor binary incre-
ments that would cause IBIASto exceed MAX IBIASare
not taken. Many of the alarm sources are likely to trip2345678910111213
tON
VPOA
BINARY SEARCH
APC
INTEGRATOR
tSEARCH
POWER-UP TIMING
MOD
VOLTAGE
BIAS
CURRENT
VCC
BIAS
SAMPLE
ISTEP
4x ISTEP
3x ISTEP
2x ISTEP
Figure 1. DS1863 Power-Up.
DS1863
Burst-Mode PON Controller
With Integrated Monitoringduring start-up. Masking the alarms until the completion
of the binary search prevents false alarms.
ISTEPis programmed by the customer using the Start-
up Step register. This value should be programmed to
the maximum safe current increase that is allowable
during start-up. If this value is programmed too low, the
DS1863 will still operate, but it could take significantly
longer for the algorithm to converge and hence to con-
trol the average power.
If a fault is detected, and TX-D is toggled to re-enable the
outputs, the DS1863 will power up following a similar
sequence to an initial power up. The only difference is
that the DS1863 already has determined the present tem-
perature, so the tINITtime is not required for the DS1863
to recall the APC and MOD set points from EEPROM.
BIAS and MOD Output as a Function
of Transmit Disable (TX-D)If TX-D is asserted (logic 1) during operation, the out-
puts will immediately turn off (tOFF). When TX-D is
deasserted (logic 0), the DS1863 will turn on the MOD
output with the value associated with the present tem-
perature, and initialize the IBIASusing the same search
algorithm as done at start-up. Soft TX-D (Lower
Memory, Register 6Eh) when asserted would allow a
software control identical to the TX-D pin.
APC/Quick-Trip Shared Comparator TimingThe DS1863’s input comparator is shared between the
APC control loop and the three quick-trip alarms
(HTXP, LTXP and HBIAS). The comparator polls the
alarms in a round-robin multiplexed sequence. Six of
every eight of the comparator readings will be used for
APC Loop bias current control. The other two updates
will be used to check the HTXP/LTXP (Monitor Diode
voltage) and the HBIAS (MON1) signals against the
internal APC and BIAS reference. The HTXP/LTXP com-
parison will check HTXP if the last bias-update compar-
ison was above the APC set-point, and LTXP if the last
bias update comparison was below the APC set-point.
The DS1863 has a programmable comparator sample
time based on an internally generated clock to facilitate a
wide variety of external filtering options suitable for burst
mode transmitter data rates between 155Mbits/s and
1250Mbits/s. The rising edge of burst enable (BEN) trig-
gers the sample to occur, and the Sample Rate register
determines the delay. The internal clock is asynchronous
to BEN, causing a 100ns uncertainty as to when the first
sample will occur following BEN. After the first sample
occurs, subsequent samples will occur on a regular
interval. The following sample rate options are available.
Comparisons of the HTXP, LTXP, and HBIAS quick-trip
alarms will not occur during the burst enable low time.
Any quick-trip alarm that is detected will by default
remain active until a subsequent comparator sample
shows the condition no longer exists.
A second bias current monitor compares the DS1863’s
bias current DAC’s code to a digital value stored in the
MAX IBIAS register. This comparison is made every
bias current update to ensure that a high bias current
will be quickly detected.
TX-D TIMING (NORMAL OPERATION)
TX-D
IBIAS
IMODtOFFtON
tONtOFF
Figure 2. TX-D Timing (Output Disabled During Normal Operating
Conditions).
SR3–SR0
MINIMUM TIME
FROM BEN TO FIRST
SAMPLE (tFIRST)
±50ns
REPEATED SAMPLE
PERIOD FOLLOWING
FIRST SAMPLE (tREP)0000b350ns800ns
0001b550ns1200ns
0010b750ns1600ns
0011b950ns2000ns
0100b1350ns2800ns
0101b1550ns3200ns
0110b1750ns3600ns
0111b2150ns4400ns
1000b2950ns6000ns
1001b*3150ns6400ns
*All codes greater than 1001b (1010b–111b) use the maximum
sample time of code 1001b.
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Monitors And Fault Detection
MonitorsMonitoring functions on the DS1863 include four quick-
trip comparators and five ADC channels
This monitoring combined with the interrupt masks
determines when/if the DS1863 shuts down its outputs
and triggers the TX-F and FETG outputs. All of the mon-
itoring levels and interrupt masks are user programma-
ble with the exception of POA, which trips at a fixed
range and is non-maskable for safety reasons.
Four Quick-Trip Monitors And AlarmsFour quick-trip monitors are provided to detect potential
laser safety issues. These monitorHigh Bias Current (HBIAS)Low Transmit Power (LTXP)High Transmit Power (HTXP)Max Output Current (MAX IBIAS)
The high and low transmit power quick-trip registers
(HTXP and LTXP) set the thresholds used to compare
against the BMD voltage to determine if the transmit
power is within specification. The HBIAS quick-trip
compares the MON1 input (generally from the
MAX3643 bias monitor output) against its threshold set-
ting to determine if the present bias current is above
specification. The Max Bias quick-trip is a digital com-
parison that determines if the Bias Output code indi-
cates the bias current is above specification. The bias
current will not be allowed to exceed the value set in
this register. When the DS1863 detects the bias is at
the limit it will set the BIAS MAXstatus bit and hold the
bias current at the MAX IBIASlevel. The quick-trips are
routed to the TX-F and FETG outputs via interrupt
masks to allow combinations of these alarms to be
used to trigger these outputs. Any time FETG is trig-
gered the DS1863 will also disable its outputs. All the
quick-trip alarm levels and masks are programmable
through the I2Cinterface.
Five ADC Monitors And AlarmsThe ADC monitors five channels that measure tempera-
ture (internal temp sensor), VCC, MON1, MON2, and
MON3 using an analog multiplexer to measure them
round robin with a single ADC. Each channel has a
customer programmable full scale range and offset
value that will be factory programmed to default value
(see below). Additionally, MON1, MON2, and MON3
have the ability to right shift results by up to 7 bits
before the results are compared to alarm thresholds or
read over the I2Cbus. This allows customers with spec-
ified ADC ranges to calibrate the ADC full scale to a
factor of 1/2nof their specified range to measure small
signals. The DS1863 can then right shift the results by n
bits to maintain the bit weight of their specification.
The ADC results (after right shifting, if used) are com-
pared to high alarm thresholds (to check if the results
exceeded this threshold), the low alarm thresholds (to
check if the ADC results are below this threshold) and
the warning threshold after each conversion (20 com-
parisons total), and the corresponding alarms are set
which can be used to trigger the TX-F or FETG outputs.
These ADC thresholds are user programmable via the2Cinterface, as are the masking registers that can be
APC LOOP/QUICK TRIP SAMPLE TIMING
LAST BURST'S
BIAS SAMPLE
BEN
BIAS DAC
CODE
QUICK-TRIP
SAMPLE TIMES
HBIAS
SAMPLE
tFIRST
tREP
H/LTXP
SAMPLE
BIAS
SAMPLE
BIAS
SAMPLE
BIAS
SAMPLE
BIAS
SAMPLE
BIAS
SAMPLE
BIAS
SAMPLE
BIAS
SAMPLE
Figure 3. APC/Quick-Trip Alarm Sample Timing.
ADC Default Monitor Full Scale Ranges
SIGNAL (UNITS)+ FS
SIGNAL
+ FS
HEX
- FS
SIGNAL
- FS
HEXTemperature (oC)127.9967FFF-1288000
VCC (V)6.5528FFF80V0000
MON1, MON2,
MON3 (V)2.4997FFF80V0000
DS1863
Burst-Mode PON Controller
With Integrated Monitoringused to prevent the alarms from triggering the TX-F and
FETG outputs. See below for more detail on the TX-F
and FETG outputs.
ADC TimingThere are five analog channels that are digitized in a
round robin fashion in the order shown in Figure 4. The
total time required to convert all five channels is tRR
(see electrical specifications for details).
Right Shifting A/D Conversion ResultIf the weighting of the ADC digital reading must con-
form to a Predetermined Full-Scale (PFS) value defined
by a specification, then right shifting can be used to
adjust the PFS analog measurement range while main-
taining the weighting of the ADC results. The DS1863’s
range is wide enough to cover all requirements; when
maximum input value is far short of the FS value, right
shifting can be used to obtain greater accuracy. For
instance, the maximum voltage might be 1/8 of the
specified PFS value, so only 1/8 of the converter’s
range is effective over this range. An alternative is to
calibrate the ADC’s full scale range to 1/8 the readable
PFS value and use a right-shift value of 3. With this
implementation, the resolution of the measurement has
increased by a factor of 8, and because the result is
digitally divided by 8 by right shifting, the bit weight of
the measurement still meets the standard.
The right shift operation on the A/D converter results is
carried out based on the contents of Right Shift Control
Registers (Table 02h Registers 8Eh to 8Fh) in EEPROM.
Three analog channels: MON1 to MON3 each have 3
bits allocated to set the number of right shifts. Up to 7
right shift operations are allowed and will be executed
as a part of every conversion before the results are
compared to the high and low alarm levels, or loaded
into their corresponding measurement registers 62h to
69h. This is true during the setup of internal calibration
as well as during subsequent data conversions.
Transmit Fault (TX-F) OutputThe TX-F output has masking registers for the five ADC
alarms and the four QT alarms to select which compar-
isons cause it to assert. In addition, the FETG alarm is
selectable via the TX-F mask to cause TX-F to assert.
All alarms, with the exception of FETG, will only cause
TX-F to remain active while the alarm condition persists.
However, the TX-F latch bit can enable the TX-F output
to remain active until it is cleared by the TX-F reset bit,
TX-D, soft TX-D, or by power cycling the part. If the
FETG output is configured to trigger TX-F, then it is indi-
cating that the DS1863 is in shutdown, and will require
TX-D, soft TX-D, or cycling power to reset. The ADC
and Quick-trip alarms (with the exception of BIAS MAX)
are ignored for the first 8-10 bias current updates dur-
ing power up. Only enabled alarms will activate TX-F.
The following table shows TX-F as a function of TX-D
and the alarm sources.
Safety Shutdown (FETG) OutputThe FETG output has masking registers (separate from
TX-F) for the five ADC alarms and the four QT alarms to
select which comparisons cause it to assert. Unlike TX-F,
NORMAL ADC SAMPLE TIMING
TEMPVCCMON1MON2MON3TEMPVCC
ONE ROUND-ROBIN ADC CYCLE
MON3
tRR
Figure 4. ADC Round-Robin Timing.
If VCClow alarm is set for either the TX-F or FETG output, the Round Robin timing will cycle between only TEMP and VCC.
TX-F as a Function of TX-D and Alarm
Sources
VCC > VPOATX-DNON-MASKED
TX-F ALARMTX-FXX1
Yes000
Yes011
Yes1X0
DS1863
Burst-Mode PON Controller
With Integrated MonitoringFETG output is always latched in case it is triggered by
an unmasked alarm condition. Its output polarity is pro-
grammable to allow an external N or P MOSFET to open
during alarms to shut off the laser diode current. If the
FETG output triggers indicating the DS1863 is in shut-
down, then it requires TX-D, soft TX-D, or cycling power
to be reset. Under all conditions when the analog outputs
are re-initialized after being disabled, all the alarms with
the exception of the VCClow ADC alarm will be cleared.
The VCClow alarm must remain active to prevent the out-
put from attempting to operate when inadequate VCC
exists to operate the laser driver. Once adequate VCCis
present to clear the VCClow alarm, the outputs will be
enabled following the same sequence as power up.
As mentioned before the FETG is an output used to dis-
able the laser current via a series N or P MOSFET. This
requires that the FETG output is capable of sinking or
sourcing current. Because the DS1863 will not know if it
should sink or source current before VCCexceeds
VPOA, which triggers the EE recall, this output will be
high impedance when VCCis below VPOA. (see “Low
Voltage Operation” section for details and diagram).
The application circuit must use a pull-up or pull-down
resistor on this pin that pulls FETG to the alarm/shut-
down state (high for a PMOS, low for a NMOS). Once
VCCis above VPOA, the DS1863 will pull the FETG out-
put to the state determined by the FETG DIR bit (Table
02h, Register 89h). FETG DIR will be 0 if an NMOS is
used and 1 if a PMOS is used.
Determining Alarm Causes
Using The I2C InterfaceTo determine the cause of the TX-F or FETG alarm, the
system processor can read the DS1863’s Alarm Trap
Bytes (ATB) through the I2C interface (in Table 01h). The
ATB have a bit for each alarm. Any time an alarm occurs,
regardless of the mask bit’s state, the DS1863 sets the
corresponding bit in the ATB. Active ATB bits will remain
set until written to zeros via the I2C interface. On power
up the ATB will be zeros until alarms dictate otherwise.
Die IdentificationDS1863 will have an ID hard coded to its die. Two reg-
isters (Table 02h bytes 86h–87h) are assigned for this
feature. Byte 86h will read 63h to identify the part as the
DS1863, byte 87h will read to A1h (for A1 die revision).
Low-Voltage OperationThe DS1863 contains two Power-On Reset (POR) lev-
els. The lower level is a Digital POR (VPOD) and the
TX-F LATCHED OPERATION
TX-F NON-LATCHED OPERATION
DETECTION OF
TX-F FAULT
TX-D OR
TX-F RESET
TX-F
DETECTION OF
TX-F FAULT
TX-F
Figure 5. DS1863 TX-F Timing.
FETG and MOD and BIAS Outputs as a
Function of TX-D and Alarm Sources
VCC >
VPOATX-DNON-MASKED
FETG ALARMFETG
MOD AND
BIAS
OUTPUTSYes00FETG DIREnabled
Yes01FETG DIRDisabled
Yes1XFETG DIRDisabled
DS1863
Burst-Mode PON Controller
With Integrated Monitoringhigher level is an Analog POR (VPOA). At start up,
before the supply voltage rises above VPOA, the out-
puts are disabled (FETG and BIAS outputs are high
impedance, MOD is low), all SRAM outputs are low
(including Shadowed EEPROM), and all analog circuit-
ry is disabled. When VCCreaches VPOA, the SEE is
recalled, and the analog circuitry is enabled. While
VCCremains above VPOA, the device is in its normal
operating state, and it responds based on its non-
volatile configuration. If during operation VCCfalls
below VPOA, but is still above VPOD, then the SRAM
will retain the SEE settings from the first SEE recall, but
the device analog will be shut down and the outputs
disabled. FETG will be driven to its alarm state defined
by the FETG DIR bit (Table 02h, Register 89h). If the
supply voltage recovers back above VPOA, then the
device will immediately resume normal functioning. If
the supply voltage falls below VPOD, then the device
SRAM will be placed in its default state and another
SEE recall will be required to reload the nonvolatile set-
tings. The EEPROM recall will occur the next time VCC
next exceeds VPOA. Figure 7 shows the sequence of
events as the voltage varies.
Any time VCCis above VPOD, the I2Cinterface can be
used to determine if VCCis below the VPOAlevel. This
is accomplished by checking the RDYB bit in the Status
(6Eh) byte. RDYB is set when VCCis below VPOA; when
VCCrises above VPOARDYB is timed (within 500µs) to
go to 0, at which point the part is fully functional.
For all Device Addresses sourced from EEPROM (Byte
8Ch, Table 01h in memory) the default Device Address
is A2h until VCCexceeds VPOAallowing the device
address to be recalled from the EEPROM.
Power-On Analog (POA)POA holds the DS1863 in reset until VCCis at a suitable
level (VCC > VPOA) for the part to accurately measure
with its ADC and compare analog signals with its quick-
trip monitors. Because VCCcannot be measured by the
ADC when VCCis less than VPOA, POA also asserts the
VCClow alarm, which must be cleared by a VCCADC
conversion that is greater than the customer programma-
ble VCClow ADC limit. This prevents the TX-F and FETG
outputs from glitching during a slow power up. The TX-F
and FETG output will not latch until there is a conversion
above VCClow limit.
The POA alarm is non-maskable. The TX-F, and FETG
outputs shuts off any time VCCis below VPOA. See Low
Voltage Operationsection for more information.
FETG/OUTPUT DISABLE TIMING (FAULT CONDITION DETECTED)
IBIAS
IMOD
DETECTION OF
FETG FAULT
tOFFtON
tONtOFF
TX-D
tFETG:ONFETGtFETG:OFF
Figure 6. FETG/Modulation and Bias Timing (Fault Condition Detected).
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
DS1863 Memory Map
Memory OrganizationThe DS1863 features six memory banks that include the
following.
The Lower Memoryis addressed from 00h to 7Fh and
contains alarm and warning thresholds, flags, masks,
several control registers, password entry area (PWE),
and the Table Select byte. The Table Select Byte deter-
mines which Table (01h–05h) will be mapped into the
upper memory locations.
Table 01hprimarily contains user EEPROM (with PW1
level access) as well as some Alarm and Warning sta-
tus bytes.
Table 02his a multifunction space that contains
Configuration registers, scaling and offset values,
Passwords, interrupt registers as well as other miscella-
neous control bytes.
Table 03his strictly user EEPROM that is protected by
a PW2 level password.
Table 04hcontains a temperature indexed Look up
Table (LUT) for control of the modulation voltage. The
modulation LUT can be programmed in 2°C increments
over the -40°C to +102°C range. Access to this register
is protected by a PW2 level password.
Table 05hcontains another LUT which allows the APC
set point to change as a function of temperature to
compensate for Tracking Error (TE). This TE LUT, has
36 entries that determine the APC setting in 4°C win-
dows between -40°C to 100°C. Access to this register
is protected by a PW2 level password.
Complete detail of each byte’s function, as well as
Read/Write permissions for each Byte for each table is
provided in the Register Descriptionssections.
Shadowed EEPROMMany nonvolatile (NV)memory locations (listed within
the Detailed Register Descriptionsection) are actually
Shadowed-EEPROM which are controlled by the SEEB
bit in Table 02h, Byte 80h.
The DS1863 incorporates Shadowed EEPROM memory
locations for key memory addresses that may be re-
written many times. By default the Shadowed EEPROM
Bit, SEEB, is not set and these locations act as ordinary
EEPROM. By setting SEEB these locations function like
SRAM cells, which allow an infinite number of write
cycles without concern of wearing out the EEPROM.
This also eliminates the requirement for the EEPROM
write time, tWR. Because changes made with SEEB
enabled do not affect the EEPROM, these changes are
not retained through power cycles. The power-up value
is the last value written with SEEB disabled. This func-
tion can be used to limit the number of EEPROM writes
during calibration or to change the monitor thresholds
periodically during normal operation helping to reduce
the number of times EEPROM is written. The Memory
Map description indicates which locations are shad-
owed-EEPROM.
VCC
VPOA
VPOD
FETG
SEE*
HIGH
IMPEDANCE
HIGH
IMPEDANCE
HIGH
IMPEDANCE
NORMAL
OPERATION
DRIVEN TO
FETG DIR
NORMAL
OPERATION
PRECHARGED
TO 0
PRECHARGED
TO 0
PRECHARGED
TO 0
RECALLED
VALUE
RECALLED
VALUE
DRIVEN TO
FETG DIR
NORMAL
OPERATION
DRIVEN TO
FETG DIR
SEE RECALLSEE RECALL
Figure 7. DS1863 Digital and Analog Power-On Reset.
DS1863
Burst-Mode PON Controller
With Integrated Monitoring2C Definitions
Master Device:The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, START and STOP conditions.
Slave Devices:Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy:Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic-high states. When the bus is idle it often initi-
ates a low-power mode for slave devices.
START Condition:A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition. See the timing dia-
gram for applicable timing.
STOP Condition:A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition. See the timing dia-
gram for applicable timing.
Repeated START Condition:The master can use a
repeated START condition at the end of one data trans-
fer to indicate that it will immediately initiate a new data
transfer following the current one. Repeated STARTS
are commonly used during read operations to identify a
TABLE SELECT BYTE
MISC. CONTROL BITS
PASSWORD ENTRY (PWE)
(4 BYTES)
DIGITAL DIAGNOSTIC
FUNCTIONS
7Fh2C SLAVE ADDRESS A2h
00h
FFh
80h
PW1 LEVEL ACCESS
EEPROM
(120 BYTES)
TABLE 01h
LOWER MEMORYFFh
F7h
80h
C0h
CONFIGURATION AND
CONTROL
EMPTY
TABLE 02hFFh
80h
PW2 LEVEL ACCESS
EEPROM
(128 BYTES)
TABLE 03hC7h
80h
MODULATION VOLTAGE
CONTROL TEMPERATURE
INDEXED LUT
TABLE 04hA7h
80h
TRACKING ERROR LUT
FOR TEMPERATURE
INDEXED CONTROL OF
APC SET-POINT
TABLE 05hDEC
HEX
1277F
248F8
255FF
Figure 8. DS1863 Memory Map.
DS1863
Burst-Mode PON Controller
With Integrated Monitoringspecific memory address to begin a data transfer. A
repeated START condition is issued identically to a nor-
mal START condition. See the timing diagram for
applicable timing.
Bit Write:Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold-time requirements (Figure 9). Data is shift-
ed into the device during the rising edge of the SCL.
Bit Read:At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time before the next rising edge of SCL during a
bit read. The device shifts out each bit of data on SDA at
the falling edge of the previous SCL pulse and the data
bit is valid at the rising edge of the current SCL pulse.
Remember that the master generates all SCL clock
pulses including when it is reading bits from the slave.
Acknowledgement (ACK and NACK):An Acknowledge-
ment (ACK) or Not Acknowledge (NACK) is always the
9th bit transmitted during a byte transfer. The device
receiving data (the master during a read or the slave
during a write operation) performs an ACK by transmit-
ting a zero during the 9th bit. A device performs a
NACK by transmitting a one during the 9th bit. Timing
for the ACK and NACK is identical to all other bit writes.
An ACK is the acknowledgment that the device is prop-
erly receiving data. A NACK is used to terminate a read
sequence or as an indication that the device is not
receiving data.
Byte Write:A byte write consists of 8 bits of information
transferred from the master to the slave (most signifi-
cant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgement is read using the bit read definition.
Byte Read:A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition, and the master transmits an ACK using
the bit write definition to receive additional data bytes.
The master must NACK the last byte read to terminate
communication so the slave will return control of SDA to
the master.
Slave Address Byte:Each slave on the I2Cbus
responds to a slave addressing byte (Figure 10) sent
immediately following a START condition. The slave
address byte contains the slave address in the most sig-
nificant 7 bits and the R/Wbit in the least significant bit.
The DS1863’s slave address can be configured to any
value between 00h to FEh using the Device Address
Byte (Table 02h, Register 8Ch). The user also has to set
the ASEL bit (Table 02h, Register 89h) for this address to
be active. The default address is A2h (see Figure 10). By
writing the correct slave address with R/W= 0, the mas-
ter indicates it will write data to the slave. If R/W= 1, the
master will read data from the slave. If an incorrect slave
address is written, the DS1863 will assume the master is
communicating with another I2C device and ignore the
communications until the next START condition is sent.
Memory Address: During an I2Cwrite operation, the
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is always the second byte trans-
mitted during a write operation following the slave
address byte.
SDA
SCL
tHD:STA
tLOW
tHIGHtF
tHD:DAT
tSU:DATREPEATED
START
tSU:STA
tHD:STA
tSU:STO
tSP
STOPSTART
tBUF
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
Figure 9. I2C Timing Diagram.
DS1863
Burst-Mode PON Controller
With Integrated Monitoring2C Communication
Writing a Single Byte to a Slave:The master must
generate a START condition, write the slave address
byte (R/W= 0), write the byte of data, and generate a
STOP condition. The master must read the slave’s
acknowledgement during all byte write operations.
Writing Multiple Bytes to a Slave: To write multiple
bytes to a slave, the master generates a start condition,
writes the slave address byte (R/W= 0), writes the
memory address, writes up to 8 data bytes, and gener-
ates a stop condition. The DS1863 writes 1 to 8 bytes (1
page or row) with a single write transaction. This is
internally controlled by an address counter that allows
data to be written to consecutive addresses without
transmitting a memory address before each data byte is
sent. The address counter limits the write to one 8-byte
page (one row of the memory map). Attempts to write to
additional pages of memory without sending a stop
condition between pages results in the address counter
wrapping around to the beginning of the present row.
Example:A 3-byte write starts at address 06h and
writes three data bytes (11h, 22h, and 33h) to three
“consecutive” addresses. The result is that addresses
06h and 07h would contain 11h and 22h, respectively,
and the third data byte, 33h, would be written to
address 00h.
To prevent address wrapping from occurring, the mas-
ter must send a stop condition at the end of the page,
then wait for the bus-free or EEPROM-write time to
elapse. Then the master can generate a new start con-
dition, and write the slave address byte (R/W= 0) and
the first memory address of the next memory row
before continuing to write data.
Acknowledge Polling:Any time an EEPROM location
is written, the DS1863 requires the EEPROM write time
(tW) after the STOP condition to write the contents of
the byte of data to EEPROM. During the EEPROM write
time, the device will not acknowledge its slave address
because it is busy. It is possible to take advantage of
that phenomenon by repeatedly addressing the
DS1863, which allows the next page to be written as
soon as the DS1863 is ready to receive the data. The
alternative to acknowledge polling is to wait for a maxi-
mum period of tWto elapse before attempting to write
again to the device.
EEPROM Write Cycles:When EEPROM writes occur to
the memory, the DS1863 will write to all three EEPROM
memory locations, even if only a single byte was modi-
fied. Because all three bytes are written, the bytes that
were not modified during the write transaction are still
subject to a write cycle. This can result in all three bytes
being worn out over time by writing a single byte repeat-
edly. The DS1863’s EEPROM write cycles are specified in
the NV Memory Characteristicstable. The specification
shown is at the worst-case temperature. If zero-crossing
detection is enabled, EEPROM write cycles cannot begin
until after the zero-crossing detection is complete.
Reading a Single Byte from a Slave:To read a single
byte from the slave, the master generates a START con-
dition, writes the slave address byte with R/W= 1, reads
the data byte with a NACK to indicate the end of the
transfer, and generates a STOP condition. When a single
byte is read, it will always be the Potentiometer 0 value.
Reading Multiple Bytes from a Slave:The read oper-
ation can be used to read multiple bytes with a single
transfer. When reading bytes from the slave, the master
simply ACKs the data byte if it desires to read another
byte before terminating the transaction. After the mas-
ter reads the last byte, it NACKs to indicate the end of
the transfer and generates a STOP condition. The first
byte read will be the Potentiometer 0 Wiper Setting. The
next byte will be the Potentiometer 1 Wiper Setting. The
third byte is the Configuration Register byte. If an ACK
is issued by the master following the Configuration
Register byte, then the DS1863 will send the
Potentiometer 0 Wiper Setting again. This round robin
reading will occur as long as each byte read is followed
by an ACK from the master.
THE DEFAULT SLAVE ADDRESS IS SHOWN, HOWEVER IT CAN BE CHANGED
USING THE DEVICE ADDRESS BYTE (TABLE 02h, BYTE 8Ch)., AND ASEL BIT.
MSB
SLAVE
ADDRESS*
LSB0001R/W
READ/WRITE
BIT
Figure 10. DS1863 Slave Address Byte (Default)
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
LOWER MEMORYWORD 0WORD 1WORD 2WORD 3ROW
(HEX)
ROW
NAMEBYTE 0/8BYTE 1/9BYTE 2/ABYTE 3/BBYTE 4/CBYTE 5/DBYTE 6/EBYTE 7/F<1>THRESHOLD0TEMP ALARM HITEMP ALARM LOTEMP WARN HITEMP WARN LO<1>THRESHOLD1VCC ALARM HIVCC ALARM LOVCC WARN HIVCC WARN LO<1>THRESHOLD2MON1 ALARM HIMON1 ALARM LOMON1 WARN HIMON1 WARN LO<1>THRESHOLD3MON2 ALARM HIMON2 ALARM LOMON2 WARN HIMON2 WARN LO<1>THRESHOLD4MON3 ALARM HIMON3 ALARM LOMON3 WARN HIMON3 WARN LO<1>SHADOWED EESEESEESEESEESEESEESEESEE<1>PW2 EEEEEEEEEEEEEEEEEE<1>PW2 EEEEEEEEEEEEEEEEEE<1>PW2 EEEEEEEEEEEEEEEEEE<1>PW2 EEEEEEEEEEEEEEEEEE<1>PW2 EEEEEEEEEEEEEEEEEE<1>PW2 EEEEEEEEEEEEEEEEEE<2>ADC VALUES0TEMP VALUEVCC VALUEMON1 VALUEMON2 VALUE<0> ADC VALUES1<2>MON3 VALUE<2>RESERVED<2>RESERVED<0>STATUS<3>UPDATE<2>ALARM/WARNALARM3ALARM2ALARM1ALARM0WARN3WARN2RESERVED<0>TABLE SELECT<6>RESERVED<6>RESERVED<6>RESERVED<6>PWE MSB<6>PWE LSB<5>TBL SEL
Access Code<0><1><2><3><4><5><6><7><8><9><10><11>
Read AccessAllAllAllPW2AllN/APW1PW2N/APW2All
Write Accessee eachi t /b yt eep ar at el y PW2N/AAl l and
DS1863
Har dwar e
PW2 +
mode bit
AllAllPW1PW2PW2N/APW1
Lower Memory Register MapThis register map shows each byte/word in terms of the
row it is on in the memory. The first byte in the row is
located in memory at the row address (hexadecimal) in
the left most column. Each subsequent byte on the row is
one/ two memory locations beyond the previous
byte/word’s address. A total of eight bytes are present
on each row. For more information about each of these
bytes see the corresponding register description.
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Table 01h. Register Map
TABLE 01h (PW1)WORD 0WORD 1WORD 2WORD 3ROW
(HEX)
ROW
NAMEBYTE 0/8BYTE 1/9BYTE 2/ABYTE 3/BBYTE 4/CBYTE 5/DBYTE 6/EBYTE 7/F<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<7>PW1 EEEEEEEEEEEEEEEEEE<11>ALARM TRAPALARM3ALARM2ALARM1ALARM0WARN3WARN2RESERVED
Access Code<0><1><2><3><4><5><6><7><8><9><10><11>
Read AccessAllAllAllPW2AllN/APW1PW2N/APW2All
Write Accessee eachi t /b yt es ep ar at el y PW2N/AAl l andDS1863
Har dwar e
PW2 +mode bitAllAllPW1PW2PW2N/APW1
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Table 02h. Register Map
TABLE 02h (PW2)WORD 0WORD 1WORD 2WORD 3ROW
(HEX)
ROW
NAMEBYTE 0/8BYTE 1/9BYTE 2/ABYTE 3/BBYTE 4/CBYTE 5/DBYTE 6/EBYTE 7/F<0>CONFIG0<8>MODE<4>TINDEX<4>MOD DAC<4>APC DAC< 4> BIAS DAC2< 4> BIAS DAC2< 10 > DEV ICE ID <10>DEVICE VER<8>CONFIG1UPDATE
RATECONFIGSTART-UP
STEP
MOD
RANGING
DEVICE
ADDRESS
COMP
RANGINGRSHIFT1RSHIFT0<8>SCALE0RESERVEDVCC SCALEMON1 SCALEMON2 SCALE<8>SCALE1MON3 SCALERESERVEDRESERVEDRESERVED<8>OFFSET0RESERVEDVCC OFFSETMON1 OFFSETMON2 OFFSET<8>OFFSET1MON3 OFFSETRESERVEDRESERVEDINTERNAL TEMP OFFSET*< 9> P WD V ALU EPW1 MSBPW1 LSBPW2 MSBPW2 LSB<8>INTERRUPTFETG EN1FETG EN0TX-F EN1TX-F EN0HTXPLTXPHBIASMAX IBIAS
C0-F7EMPTYEMPTYEMPTYEMPTYEMPTYEMPTYEMPTYEMPTYEMPTY<4>MAN IBIASMAN IBIAS0MAN IBIAS1MAN_CNTLRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
Access Code<0><1><2><3><4><5><6><7><8><9><10><11>
Read AccessAllAllAllPW2AllN/APW1PW2N/APW2All
Write Accessee eachi t /b yt eep ar at el y PW2N/AAl l and
DS1863
Har dwar e
PW2 +
mode bit
AllAllPW1PW2PW2N/APW1
*The Final Result must be XOR’ed with BB40h before writing to this register.
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Table 03h. Register Map
TABLE 03h (PW2)WORD 0WORD 1WORD 2WORD 3ROW
(HEX)
ROW
NAMEBYTE 0/8BYTE 1/9BYTE 2/ABYTE 3/BBYTE 4/CBYTE 5/DBYTE 6/EBYTE 7/F<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE<8>PW2 EEEEEEEEEEEEEEEEEE
Access Code<0><1><2><3><4><5><6><7><8><9><10><11>
Read AccessAllAllAllPW2AllN/APW1PW2N/APW2All
Write Accessee eachi t /b yt eep ar at el y PW2N/AAl l and
DS1863
Har dwar e
PW2 +
mode bit
AllAllPW1PW2PW2N/APW1
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Table 04h. Register Map
TABLE 04h (LUT FOR MOD)WORD 0WORD 1WORD 2WORD 3ROW
(HEX)
ROW
NAMEBYTE 0/8BYTE 1/9BYTE 2/ABYTE 3/BBYTE 4/CBYTE 5/DBYTE 6/EBYTE 7/F<8>LUT4MODMODMODMODMODMODMODMOD<8>LUT4MODMODMODMODMODMODMODMOD<8>LUT4MODMODMODMODMODMODMODMOD<8>LUT4MODMODMODMODMODMODMODMOD<8>LUT4MODMODMODMODMODMODMODMOD<8>LUT4MODMODMODMODMODMODMODMOD<8>LUT4MODMODMODMODMODMODMODMOD<8>LUT4MODMODMODMODMODMODMODMOD<8>LUT4MODMODMODMODMODMODMODMOD
Table 05h. Register Map
TABLE 05h (LUT FOR APC)WORD 0WORD 1WORD 2WORD 3ROW
(HEX)
ROW
NAMEBYTE 0/8BYTE 1/9BYTE 2/ABYTE 3/BBYTE 4/CBYTE 5/DBYTE 6/EBYTE 7/F<8>LUT5APC REFAPC REFAPC REFAPC REFAPC REFAPC REFAPC REFAPC REF<8>LUT5APC REFAPC REFAPC REFAPC REFAPC REFAPC REFAPC REFAPC REF<8>LUT5APC REFAPC REFAPC REFAPC REFAPC REFAPC REFAPC REFAPC REF<8>LUT5APC REFAPC REFAPC REFAPC REFAPC REFAPC REFAPC REFAPC REF<8>LUT5APC REFAPC REFAPC REFAPC REFRE SE RV ED RE SE RV ED RE SE RV ED RE SE RV ED
Access Code<0><1><2><3><4><5><6><7><8><9><10><11>
Read AccessAllAllAllPW2AllN/APW1PW2N/APW2All
Write Accessee eachi t /b yt es ep ar at el y PW2N/AAl l andDS1863
Har dwar e
PW2 +mode bitAllAllPW1PW2PW2N/APW1
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Lower Memory Register 00h to 01h: Temp Alarm HiFACTORY DEFAULT:7FFFh
READ ACCESSAll
WRITE ACCESSPW2
MEMORY TYPE:Nonvolatile (SEE)
00hS26252423222120
01h2-12-22-32-42-52-62-72-8
bit7bit0
Temperature measurements above this 2’s complement threshold will set its corresponding alarm bit. Measurements equal to or
below this threshold will clear its alarm bit.
Lower Memory Register 02h to 03h: Temp Alarm LoFACTORY DEFAULT:8000h
READ ACCESSAll
WRITE ACCESSPW2
MEMORY TYPE:Nonvolatile (SEE)
02hS26252423222120
03h2-12-22-32-42-52-62-72-8
bit7bit0
Temperature measurements above this 2’s complement threshold will set its corresponding alarm bit. Measurements equal to or
below this threshold will clear its alarm bit.
Lower Memory Register 04h to 05h: Temp Warn HiFACTORY DEFAULT:7FFFh
READ ACCESSAll
WRITE ACCESSPW2
MEMORY TYPE:Nonvolatile (SEE)
04hS26252423222120
05h2-12-22-32-42-52-62-72-8
bit7bit0
Temperature measurements above this 2’s complement threshold will set its corresponding warning bit. Measurements equal to or
below this threshold will clear its warning bit.
Lower Memory Registers Description
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Lower Memory Register 06h to 07h: Temp Warn LoFACTORY DEFAULT:8000h
READ ACCESSAll
WRITE ACCESSPW2
MEMORY TYPE:Nonvolatile (SEE)
06hS26252423222120
07h2-12-22-32-42-52-62-72-8
bit7bit0
Temperature measurements below this 2’s complement threshold will set its corresponding warning bit. Measurements above this
threshold will clear its warning bit.
Lower Memory Register 08h to 09h: VCC Alarm HiFACTORY DEFAULT:FFFFh
READ ACCESSAll
WRITE ACCESSPW2
MEMORY TYPE:Nonvolatile (SEE)
08h2152142132122112102928
09h2726252423222120
bit7bit0
Voltage measurements of the VCC input above this unsigned threshold will set its corresponding alarm bit. Measurements below
this threshold will clear its alarm bit.
Lower Memory Register 0Ah to 0Bh: VCC Alarm LoFACTORY DEFAULT:0000h
READ ACCESSAll
WRITE ACCESSPW2
MEMORY TYPE:Nonvolatile (SEE)
0Ah2152142132122112102928
0Bh2726252423222120
bit7bit0
Voltage measurements of the VCC below above this unsigned threshold will set its corresponding alarm bit. Measurements above
this threshold will clear its alarm bit.
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Lower Memory Register 0Eh to 0Fh: VCC Warn LoFACTORY DEFAULT:0000h
READ ACCESSAll
WRITE ACCESSPW2
MEMORY TYPE:Nonvolatile (SEE)
0Eh2152142132122112102928
0Fh2726252423222120
bit7bit0ol tag e m easur em ents of the V C C b el ow ab ove thi s unsi g ned thr eshol d w i l l set i ts cor r esp ond i ng w ar ni ng b i t. M easur em ents ab ove
thi s thr eshol d w i l l cl ear i ts w ar ni ng b i t.
Lower Memory Register 10h to 11h: MON1 Alarm HiFACTORY DEFAULT:FFFFh
READ ACCESSAll
WRITE ACCESSPW2
MEMORY TYPE:Nonvolatile (SEE)
10h2152142132122112102928
11h2726252423222120
bit7bit0
Voltage measurements of the MON1 input above this unsigned threshold will set its corresponding alarm bit. Measurements below
this threshold will clear its alarm bit.
Lower Memory Register 0Ch to 0Dh: VCC Alarm HiFACTORY DEFAULT:FFFFh
READ ACCESSAll
WRITE ACCESSPW2
MEMORY TYPE:Nonvolatile (SEE)
0Ch2152142132122112102928
0Dh2726252423222120
bit7bit0
Voltage measurements of the VCC input above this unsigned threshold will set its corresponding warning bit. Measurements below
this threshold will clear its warning bit.
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Lower Memory Register 12h to 13h: MON1 Alarm LoFACTORY DEFAULT:0000h
READ ACCESSAll
WRITE ACCESSPW2
MEMORY TYPE:Nonvolatile (SEE)
12h2152142132122112102928
13h2726252423222120
bit7bit0
Voltage measurements of the MON1 input below this unsigned threshold will set its corresponding alarm bit. Measurements above
this threshold will clear its alarm bit.
Lower Memory Register 14h to 15h: MON1 Warn HiFACTORY DEFAULT:FFFFh
READ ACCESSAll
WRITE ACCESSPW2
MEMORY TYPE:Nonvolatile (SEE)
14h2152142132122112102928
15h2726252423222120
bit7bit0
Voltage measurements of the MON1 input above this unsigned threshold will set its corresponding warning bit. Measurements
below this threshold will clear its warning bit.
Lower Memory Register 16h to 17h: MON1 Warn LoFACTORY DEFAULT:0000h
READ ACCESSAll
WRITE ACCESSPW2
MEMORY TYPE:Nonvolatile (SEE)
16h2152142132122112102928
17h2726252423222120
bit7bit0
Voltage measurements of the MON1 input below this unsigned threshold will set its corresponding warning bit. Measurements
above this threshold will clear its warning bit.
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Lower Memory Register 18h to 19h: MON2 Alarm HiFACTORY DEFAULT:FFFFh
READ ACCESSAll
WRITE ACCESSPW2
MEMORY TYPE:Nonvolatile (SEE)
18h2152142132122112102928
19h2726252423222120
bit7bit0
Voltage measurements of the MON2 input above this unsigned threshold will set its corresponding alarm bit. Measurements below
this threshold will clear its alarm bit.
Lower Memory Register 1Ah to 1Bh: MON2 Alarm LoFACTORY DEFAULT:0000h
READ ACCESSAll
WRITE ACCESSPW2
MEMORY TYPE:Nonvolatile (SEE)
1Ah2152142132122112102928
1Bh2726252423222120
bit7bit0
Voltage measurements of the MON2 input below this unsigned threshold will set its corresponding alarm bit. Measurements above
this threshold will clear its alarm bit.
Lower Memory Register 1Ch to 1Dh: MON2 Alarm HiFACTORY DEFAULT:FFFFh
READ ACCESSAll
WRITE ACCESSPW2
MEMORY TYPE:Nonvolatile (SEE)
1Ch2152142132122112102928
1Dh2726252423222120
bit7bit0
Voltage measurements of the MON2 input above this unsigned threshold will set its corresponding warning bit. Measurements
below this threshold will clear its warning bit.
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Lower Memory Register 1Eh to 1Fh: MON2 Warn LoFACTORY DEFAULT:0000h
READ ACCESSAll
WRITE ACCESSPW2
MEMORY TYPE:Nonvolatile (SEE)
1Eh2152142132122112102928
1Fh2726252423222120
bit7bit0
Voltage measurements of the MON2 input below this unsigned threshold will set its corresponding warning bit. Measurements
above this threshold will clear its warning bit.
Lower Memory Register 20h to 21h: MON3 Alarm HiFACTORY DEFAULT:FFFFh
READ ACCESSAll
WRITE ACCESSPW2
MEMORY TYPE:Nonvolatile (SEE)
20h2152142132122112102928
21h2726252423222120
bit7bit0
Voltage measurements of the MON3 input above this unsigned threshold will set its corresponding alarm bit. Measurements below
this threshold will clear its alarm bit.
Lower Memory Register 22h to 23h: MON3 Alarm LoFACTORY DEFAULT:0000h
READ ACCESSAll
WRITE ACCESSPW2
MEMORY TYPE:Nonvolatile (SEE)
22h2152142132122112102928
23h2726252423222120
bit7bit0
Voltage measurements of the MON3 input below this unsigned threshold will set its corresponding alarm bit. Measurements above
this threshold will clear its alarm bit.
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Lower Memory Register 24h to 25h: MON3 Warn HiFACTORY DEFAULT:FFFFh
READ ACCESSAll
WRITE ACCESSPW2
MEMORY TYPE:Nonvolatile (SEE)
24h2152142132122112102928
25h2726252423222120
bit7bit0
Voltage measurements of the MON3 input above this unsigned threshold will set its corresponding warning bit. Measurements
below this threshold will clear its warning bit.
Lower Memory Register 26h to 27h: MON3 Warn LoFACTORY DEFAULT:0000h
READ ACCESSAll
WRITE ACCESSPW2
MEMORY TYPE:Nonvolatile (SEE)
26h2152142132122112102928
27h2726252423222120
bit7bit0
Voltage measurements of the MON3 input below this unsigned threshold will set its corresponding warning bit. Measurements
above this threshold will clear its warning bit.
Lower Memory Register 28h to 2Fh: Shadowed EEPROMFACTORY DEFAULT:00h
READ ACCESSAll
WRITE ACCESSPW2
MEMORY TYPE:Nonvolatile (SEE)
28h-2FhSEESEESEESEESEESEESEESEE
bit7bit0
Shadowed EEPROM memory (see details in Memory Map section). PW2 level access controlled ROM data for end user.
DS1863
Burst-Mode PON Controller
With Integrated Monitoring
Lower Memory Register 30h to 5Fh: PW2 EEFACTORY DEFAULT:00h
READ ACCESSAll
WRITE ACCESSPW2
MEMORY TYPE:Nonvolatile (EE)
30h-5FhEEEEEEEEEEEEEEEE
bit7bit0
Nonvolatile EEPROM memory. PW2 level access controlled ROM data for end user.
Lower Memory Register 60h to 61h: Temp ValuePOWER-ON VALUE0000h
READ ACCESSAll
WRITE ACCESSN/A
MEMORY TYPE:Volatile
60hS26252423222120
61h2-12-22-32-42-52-62-72-8
bit7bit0
Signed 2’s complement Direct-to-Temperature measurement.
Lower Memory, Register 62h–63h: VCC Value
Lower Memory, Register 64h–65h: MON1 Value
Lower Memory, Register 66h–67h: MON2 Value
Lower Memory, Register 68h–69h: MON3 ValuePOWER-ON VALUE0000h
READ ACCESSAll
WRITE ACCESSN/A
MEMORY TYPE:Volatile
62h2152142132122112102928
63h2726252423222120
64h2152142132122112102928
65h2726252423222120
66h2152142132122112102928
67h2726252423222120
68h2152142132122112102928
69h2726252423222120
bit7bit0
Unsigned voltage measurement.
