DS1856E-050+T&R ,Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password ProtectionFeatures♦ SFF-8472 CompatibleThe DS1856 dual, temperature-controlled, nonvolatile♦ Five Monitored C ..
DS1857B-050 ,3.3 V or 5 V, dual temperature-controlled resistor with external temperature input and monitorApplications♦ SFF-8472 CompatibleOptical TransceiversOptical TranspondersOrdering InformationInstru ..
DS1857B-050+ ,Dual Temperature-Controlled Resistors with External Temperature Input and MonitorsFeaturesThe DS1857 dual temperature-controlled nonvolatile ♦ Four Total Monitored Channels (Tempera ..
DS1857E-050 ,3.3 V or 5 V, dual temperature-controlled resistor with external temperature input and monitorFeaturesThe DS1857 dual temperature-controlled nonvolatile ♦ Four Total Monitored Channels (Tempera ..
DS1857E-050+ ,Dual Temperature-Controlled Resistors with External Temperature Input and MonitorsApplications♦ SFF-8472 CompatibleOptical TransceiversOptical TranspondersOrdering InformationInstru ..
DS1858 ,Dual Temperature-Controlled Resistors with Three MonitorsFeaturesThe DS1858 dual temperature-controlled nonvolatile♦ Five Total Monitored Channels (Temperat ..
DZD9.1 ,0.2W Zener DiodesElectrical Characteristics at Ta = 25˚CZener voltage VZ will be subdivided into X, Y, Z at your req ..
DS1856-DS1856E-030+-DS1856E-050-DS1856E-050+-DS1856E-050+T&R
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password ProtectionEVALUATION KIT AVAILABLE
DS1856
General DescriptionThe DS1856 dual, temperature-controlled, nonvolatile
(NV) variable resistors with three monitors consists of
two 256-position, linear, variable resistors; three analog
monitor inputs (MON1, MON2, MON3); and a direct-to-
digital temperature sensor. The device provides an
ideal method for setting and temperature-compensating
bias voltages and currents in control applications using
minimal circuitry. The variable resistor settings are
stored in EEPROM memory and can be accessed over
the 2-wire serial bus.
Relative to other members of the family, the DS1856 is
essentially a DS1859 with a DS1852-friendly memory
map. In particular, the DS1856 can be configured so
the 128 bytes of internal Auxiliary EEPROM memory is
mapped into Main Device Table 00h and Table 01h,
maintaining compatibility between both the
DS1858/DS1859 and the DS1852. The DS1856 also
features password protection equivalent to the DS1852,
further enhancing compatibility between the two.
ApplicationsOptical Transceivers
Optical Transponders
Instrumentation and Industrial Controls
RF Power Amps
Diagnostic Monitoring
FeaturesSFF-8472 CompatibleFive Monitored Channels (Temperature, VCC,
MON1, MON2, MON3)Three External Analog Inputs (MON1, MON2, MON3)
That Support Internal and External CalibrationScalable Dynamic Range for External Analog InputsInternal Direct-to-Digital Temperature SensorAlarm and Warning Flags for All Monitored
ChannelsTwo Linear, 256-Position, Nonvolatile Temperature-
Controlled Variable ResistorsResistor Settings Changeable Every 2°CThree Levels of SecurityAccess to Monitoring and ID Information
Configurable with Separate Device Addresses2-Wire Serial InterfaceTwo Buffers with TTL/CMOS-Compatible Inputs and
Open-Drain OutputsOperates from a 3.3V or 5V Supply-40°C to +95°C Operating Temperature Range
Ordering Information
PART
RES0/RES1
RESISTANCE
(kΩ)
PIN-PACKAGEDS1856E-05050/5016 TSSOP
DS1856E-050/T&R50/5016 TSSOP
DS1856B-05050/5016 CSBGA
TOP VIEW
CSBGA (4mm x 4mm)
1.0mm PITCH24
MON3OUT1IN2
MON1L0GND
N.C.H0SDAOUT2VCCSCLIN1
MON2
SDAVCC
MON3
MON2
MON1
TSSOPSCL
OUT1
IN2
IN1
OUT2
N.C.
GND
DS1856
Pin ConfigurationsDS1856
SDA1
0.1µF
SCL
OUT1
IN1
OUT2
IN2
N.C.
GND
VCC
MON3
MON2
MON1
Rx POWER*
DIAGNOSTIC
INPUTS
TO LASER
MODULATION
CONTROL
TO LASER BIAS
CONTROL
DECOUPLING
CAPACITOR
Tx POWER*
Tx BIAS*
*SATISFIES SFF-8472 COMPATIBILITY
VCC
VCC = 3.3V
4.7kΩ4.7kΩ
Tx-FAULT
LOS
2-WIRE
INTERFACE
Typical Operating Circuit
Ordering Information continued at end of data sheet.+Denotes lead-free package.
T&R denotes tape-and-reel package.
Note:All devices are specified over the -40°C to +95°C tem-
perature range.
Visit www.maximintegrated.com/products/patentsfor
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
DS1856
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSupply VoltageVCC(Note 1)2.855.50V
Input Logic 1 (SDA, SCL)VIH(Note 2)0.7 x VccVCC + 0.3V
Input Logic 0 (SDA, SCL)VIL(Note 2)-0.3+0.3 x VCCV
Resistor Inputs (L0, L1, H0, H1)-0.3VCC + 0.3V
Resistor CurrentIRES-3+3mA
High-Impedance Resistor CurrentIROFF0.0010.1µA
Input logic 11.6Input Logic Levels (IN1, IN2)Input logic 00.9V
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on VCCRelative to Ground...........-0.5V to +6.0V
Voltage Range on Inputs Relative
to Ground*..............................................-0.5V to (VCC+ 0.5V)
Voltage Range on Resistor Inputs Relative
to Ground*..............................................-0.5V to (VCC+ 0.5V)
Current into Resistors............................................................5mA
Operating Temperature Range...........................-40°C to +95°C
Programming Temperature Range.........................0°C to +70°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature.......................................See IPC/JEDEC
J-STD-020A
RECOMMENDED OPERATING CONDITIONS(TA= -40°C to +95°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSupply CurrentICC(Note 3)12mA
Input LeakageIIL-200+200nA
VOL13mA sink current00.4Low-Level Output Voltage
(SDA, OUT1, OUT2)VOL26mA sink current00.6V
Full-Scale Input (MON1, MON2,
MON3)
At factory setting
(Note 4)2.48752.52.5125V
Full-Scale VCC MonitorAt factory setting (Note 5)6.52086.55366.5864V
I/O CapacitanceCI/O10pF
Digital Power-On ResetPOD1.02.2V
Analog Power-On ResetPOA2.02.6V
DC ELECTRICAL CHARACTERISTICS(VCC= 2.85V to 5.5V, TA= -40°C to +95°C, unless otherwise noted.)
*Not to exceed 6.0V.
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
DS1856
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSThermometer ErrorTERR-40°C to +95°C±3.0°C
DIGITAL THERMOMETER(VCC= 2.85V to 5.5V, TA= -40°C to +95°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSEEPROM Writes+70°C (Note 14)50,000Writes
NONVOLATILEMEMORYCHARACTERISTICS(VCC= 2.85V to 5.5V)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSInput ResolutionΔVMON610µV
Supply ResolutionΔVCC1.6mV
Input/Supply Accuracy
(MON1, MON2, MON3, VCC)ACCAt factory setting0.250.5% FS
(full scale)
Update Rate for MON1, MON2,
MON3, Temp, or VCCtframe4760ms
Input/Supply Offset
(MON1, MON2, MON3, VCC)VOS(Note 14)05LSB
ANALOG VOLTAGE MONITORING (VCC= 2.85V to 5.5V, TA= -40°C to +95°C, unless otherwise noted.)
PARAMETERCONDITIONSMINTYPMAXUNITSPosition 00h Resistance (50kΩ)TA = +25°C0.651.01.35kΩ
Position FFh Resistance (50kΩ)TA = +25°C405060kΩ
Position 00h Resistance (30kΩ)TA = +25°C0.1650.2750.400kΩ
Position FFh Resistance (30kΩ)TA = +25°C22.53037.5kΩ
Position 00h Resistance (20kΩ)TA = +25°C0.200.400.55kΩ
Position FFh Resistance (20kΩ)TA = +25°C152025kΩ
Position 00h Resistance (10kΩ)TA = +25°C0.0750.1250.200kΩ
Position FFh Resistance (10kΩ)TA = +25°C7.51012.5kΩ
Position 00h Resistance (2.5kΩ)TA = +25°C0.10.1750.250kΩ
Position FFh Resistance (2.5kΩ)TA = +25°C2.02.503.0kΩ
Absolute Linearity(Note 6)-2+2LSB
Relative Linearity(Note 7)-1+1LSB
Temperature Coefficient(Note 8)50ppm/°C
ANALOGRESISTOR CHARACTERISTICS(VCC= 2.85V to 5.5V, TA= -40°C to +95°C, unless otherwise noted.)
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
DS1856
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSFast mode0400SCL Clock Frequency (Note 9)fSCLStandard mode0100kHz
Fast mode1.3Bus Free Time Between STOP and
START Condition (Note 9)tBUFStandard mode4.7µs
Fast mode0.6Hold Time (Repeated)
START Condition (Notes 9, 10)tHD:STAStandard mode4.0µs
Fast mode1.3LOW Period of SCL Clock (Note 9)tLOWStandard mode4.7µs
Fast mode0.6H IG H P er i od of S C L C l ock ( N ote 9) tHIGHStandard mode4.0µs
Fast mode00.9Data Hold Time (Notes 9, 11, 12)tHD:DATStandard mode0µs
Fast mode100Data Setup Time (Note 9)tSU:DATStandard mode250ns
Fast mode0.6START Setup Time (Note 9)tSU:STAStandard mode4.7µs
Fast mode20 + 0.1CB300Rise Time of Both SDA and SCL
Signals (Note 13)tRStandard mode20 + 0.1CB1000ns
Fast mode20 + 0.1CB300Fall Time of Both SDA and SCL
Signals (Note 13)tFStandard mode20 + 0.1CB300ns
Fast mode0.6Setup Time for STOP ConditiontSU:STOStandard mode4.0µs
Capacitive Load for Each Bus LineCB(Note 13)400pF
EEPROM Write TimetW1020ms
ELECTRICAL CHARACTERISTICS(VCC= 2.85V to 5.5V, TA= -40°C to +95°C, unless otherwise noted. See Figure 6.)
Note 1:All voltages are referenced to ground.
Note 2: I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if VCCis switched off.
Note 3:SDA and SCL are connected to VCCand all other input signals are connected to well-defined logic levels.
Note 4: Full scale is user programmable.The maximum voltage that the MON inputs read is approximately full scale, even if the volt-
age on the inputs is greater than full scale.
Note 5:This voltage defines the maximum range of the analog-to-digital converter voltage, not the maximum VCC voltage.
Note 6: Absolute linearity is the difference of measured value from expected value at DAC position. The expected value is a
straight line from measured minimum position to measured maximum position.
Note 7: Relative linearity is the deviation of an LSB DAC setting change vs. the expected LSB change. The expected LSB change
is the slope of the straight line from measured minimum position to measured maximum position.
Note 8: See the Typical Operating Characteristics.
Note 9: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT> 250ns must then be met. This
is automatically the case if the device does not stretch the LOWperiod of the SCL signal. If such a device does stretch the
LOWperiod of the SCL signal, it must output the next data bit to the SDA line tRMAX+ tSU:DAT= 1000ns + 250ns = 1250ns
before the SCL line is released.
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
DS1856
Note 10: After this period, the first clock pulse is generated.
Note 11: The maximum tHD:DATonly has to be met if the device does not stretch the LOWperiod (tLOW) of the SCL signal.
Note 12: A device must internally provide a hold time of at least 300ns for the SDA signal (see the VIH MIN of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 13: CB—total capacitance of one bus line, timing referenced to 0.9 x VCCand 0.1 x VCC.
Note 14: Guaranteed by design.
Typical Operating Characteristics(VCC= 5.0V, TA= +25°C, for both 50kΩand 20kΩversions, unless otherwise noted.)
TEMPERATURE (°C)6080200-20
SUPPLY CURRENT vs. TEMPERATURE
DS1856 toc01
SUPPLY CURRENT (
SDA = SCL = VCC
SUPPLY CURRENT vs. VOLTAGEDS1856 toc02
VOLTAGE (V)
SUPPLY CURRENT (
SDA = SCL = VCC
RESISTANCE vs. SETTINGDS1856 toc03
SETTING (DEC)
RESISTANCE (k
50kΩ VERSION
RESISTANCE vs. SETTINGDS1856 toc04
SETTING (DEC)
RESISTANCE (k
20kΩ VERSION
ACTIVE SUPPLY CURRENT
vs. SCL FREQUENCYDS1856 toc05
SCL FREQUENCY (kHz)
ACTIVE SUPPLY CURRENT (
SDA = VCC
RESISTOR 0 INL (LSB)DS1856 toc06
SETTING (DEC)
RESISTOR 0 INL (LSB)
-1.0250
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
DS1856
Typical Operating Characteristics (continued)(VCC= 5.0V, TA= +25°C, for both 50kΩand 20kΩversions, unless otherwise noted.)
RESISTOR 0 DNL (LSB)DS1856 toc07
SETTING (DEC)
RESISTOR 0 DNL (LSB)
RESISTOR 1 INL (LSB)
DS1856 toc08
SETTING (DEC)
RESISTOR 1 INL (LSB)
RESISTOR 1 DNL (LSB)
DS1856 toc09
SETTING (DEC)
RESISTOR 1 DNL (LSB)
RESISTANCE
vs. POWER-UP VOLTAGE
DS1856 toc10
POWER-UP VOLTAGE (V)
RESISTANCE (k41
PROGRAMMED
RESISTANCE
(80h)
>1MΩ50kΩ VERSION
RESISTANCE
vs. POWER-UP VOLTAGEDS1856 toc11
POWER-UP VOLTAGE (V)
RESISTANCE (k41
PROGRAMMED
RESISTANCE
(80h)
>1MΩ20kΩ VERSION
POSITION 00h RESISTANCE
vs. TEMPERATUREDS1856 toc12
TEMPERATURE (°C)
RESISTANCE (k355065805-10-25
50kΩ VERSION
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
DS1856
Typical Operating Characteristics (continued)(VCC= 5.0V, TA= +25°C, for both 50kΩand 20kΩversions, unless otherwise noted.)
POSITION FFh RESISTANCE
vs. TEMPERATUREDS1856 toc14
TEMPERATURE (°C)
RESISTANCE (k655035205-10-25
50kΩ VERSION
POSITION FFh RESISTANCE
vs. TEMPERATUREDS1856 toc15
TEMPERATURE (°C)
RESISTANCE (k655035205-10-25
20kΩ VERSION
TEMPERATURE COEFFICIENT vs. SETTINGDS1856 toc16
SETTING (DEC)
TEMPERATURE COEFFICIENT (ppm/
50kΩ VERSION
+25°C TO +95°C
+25°C TO -40°C
TEMPERATURE COEFFICIENT vs. SETTINGDS1856 toc17
SETTING (DEC)
TEMPERATURE COEFFICIENT (ppm/
+25°C TO +95°C
+25°C TO -40°C
20kΩ VERSION
LSB ERROR vs. FULL-SCALE INPUTDS1856 toc18
NORMALIZED FULL SCALE (%)
LSB ERROR5025100
+3 SIGMA
-3 SIGMA
MEAN
LSB ERROR vs. FULL-SCALE INPUTDS1856 toc19
NORMALIZED FULL SCALE (%)
LSB ERROR
+3 SIGMA
-3 SIGMA
MEAN
POSITION 00h RESISTANCE
vs. TEMPERATUREDS1856 toc13
TEMPERATURE (°C)
RESISTANCE (k655035205-10-25
20kΩ VERSION
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
DS1856
Detailed DescriptionThe user can read the registers that monitor the VCC,
MON1, MON2, MON3, and temperature analog signals.
After each signal conversion, a corresponding bit is set
that can be monitored to verify that a conversion has
occurred. The signals also have alarm and warning flags
that notify the user when the signals go above or below
the user-defined value. Interrupts can also be set for
each signal.
The position values of each resistor can be indepen-
dently programmed. The user can assign a unique
value to each resistor for every 2°C increment over the
-40°C to +102°C range.
Two buffers are provided to convert logic-level inputs
into open-drain outputs. Typically, these buffers are
used to implement transmit (Tx) fault and loss-of-signal
(LOS) functionality. Additionally, OUT1 can be asserted
in the event that one or more of the monitored values
go beyond user-defined limits.
PINBALLNAMEFUNCTION1B2SDA2-Wire Serial Data I/O Pin. Transfers serial data to and from the device.A2SCL2-Wire Serial Clock Input. Clocks data into and out of the device.
3C3OUT1Open-Drain Buffer OutputA1IN1TTL/CMOS-Compatible Input to Buffer
5B1OUT2Open-Drain Buffer OutputC2IN2TTL/CMOS-Compatible Input to Buffer
7C1N.C.No Connection
8D1GNDGround
9D3MON1External Analog InputD4MON2External Analog InputC4MON3External Analog InputD2L0
Low-End Resistor 0 Terminal. It is not required that the low-end terminals be connected to a potential
less than the high-end terminals of the corresponding resistor. Voltage applied to any of the resistor
terminals cannot exceed the power-supply voltage, VCC, or go below ground.B3H0
High-End Resistor 0 Terminal. It is not required that the high-end terminals be connected to a
potential greater than the low-end terminals of the corresponding resistor. Voltage applied to any of
the resistor terminals cannot exceed the power-supply voltage, VCC, or go below ground.B4L1Low-End Resistor 1 TerminalA4H1High-End Resistor 1 TerminalA3VCCSupply Voltage
Pin Description
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
DS1856DEVICE
ADDRESS
AD (AUXILIARY DEVICE ENABLE A0h)
MD (MAIN DEVICE ENABLE)
DEVICE ADDRESS
ADDRESS
ADDRESS
ADDRESS
R/W
R/W
TxF
DATA BUS
R/W
TxF
RxL
LOS
ADENADFIX
SDA
SCL
IN1
OUT1
2-WIRE
INTERFACE
MINT
INV1
Tx FAULT
IN2
MON2
MON1
MON3
VCC
GND
OUT2
INV2
EEPROM
128 x 8 BIT
STANDARDS
IF ADEN = 0,
[00h - 7Fh OF AD]
IF ADEN = 1,
[80h-FFh OF MD,
TABLE 00/01h]MD
ADDRESS
TABLE
SELECT
TABLE
SELECT
R/W
EEPROM
72 x 8 BIT
80h-C7h
TABLE 04
RESISTOR 0
LOOK-UP
TABLE
EEPROM
96 x 8 BIT
00h-5Fh
LIMITS
SRAM
32 x 8 BIT
60h-7Fh
TEMP INDEXADEN (BIT)
ALARM FLAGS
WARNING FLAGS
MUX
CTRL
MEASUREMENT
ADDRESS
TABLE
SELECT
R/W
EEPROM
72 x 8 BIT
80h-C7h
TABLE 05
RESISTOR 1
LOOK-UP
TABLE
TEMP INDEX
MONITORS LIMIT
HIGH
MONITORS LIMIT
LOW
TABLE SELECT
TEMP INDEX
MINT (BIT)
INTERNAL
TEMPVCC
MUXADC
12-BIT
INTERNAL
CALIBRATION
A/D
CTRL
VCC
COMPARATOR
MEASUREMENT
ALARM FLAGSWARNING FLAGS
MONITORS LIMIT LOW
MONITORS LIMIT HIGH
COMP CTRL
INTERRUPT
MINT
TABLE 03
EEPROM
80h-B7h
VENDORR/W
DEVICE ADDRESS
ADDRESS
TABLE SELECT
MASKING (TMP, VCC, MON1, MON2, MON3)
ADFIX (BIT)
ADEN (BIT)
INV2 (BIT)
INV1 (BIT)
RESISTOR 0
256 POSITIONS
REGISTER
REGISTER
RESISTOR 1
256 POSITIONS
RIGHT
SHIFTING
DS1856
Figure 1. Block Diagram
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
DS1856
Monitored SignalsEach signal (VCC, MON1, MON2, MON3, and tempera-
ture) is available as a 16-bit value with 12-bit accuracy
(left-justified) over the serial bus. See Table 1 for signal
scales and Table 2 for signal format. The four LSBs
should be masked when calculating the value. The 3
LSBs are internally masked with 0s.
The signals are updated every frame rate (tframe) in a
round-robin fashion.
The comparison of all five signals with the high and low
user-defined values are done automatically. The corre-
sponding flags are set to 1 within a specified time of
the occurrence of an out-of-limit condition.
Calculating Signal ValuesThe LSB = 100µV for VCC, and the LSB = 38.147µV for
the MON signals when using factory default settings.
To calculate VCC, convert the unsigned 16-bit value to
decimal and multiply by 100µV.
To calculate MON1, MON2, or MON3, convert the
unsigned 16-bit value to decimal and multiply by
38.147µV.
To calculate the temperature, treat the two’s comple-
ment value binary number as an unsigned binary num-
ber, then convert to decimal and divide by 256. If the
result is greater than or equal to 128, subtract 256 from
the result.
Temperature: high byte: -128°C to +127°C signed; low
byte: 1/256°C.
SIGNAL+FS
SIGNAL
+FS
(hex)
-FS
SIGNAL
-FS
(hex)Temperature+127.984°7FFC-128°C8000
VCC6.5528VFFF80V0000
MON12.4997VFFF80V0000
MON22.4997VFFF80V0000
MON32.4997VFFF80V0000
Table 1. Scales for Monitor Channels at
Factory Setting
SIGNALFORMATVCCUnsigned
MON1Unsigned
MON2Unsigned
MON3Unsigned
TemperatureTwo’s complement
Table 2. Signal Comparison
TEMPERATURE
(°C)
CORRESPONDING LOOK-UP
TABLE ADDRESS<-4080h
-4080h
-3881h
-3682h
-3483h
+98C5h
+100C6h
+102C7h
>+102C7h
Table 3. Look-Up Table Address for
Corresponding Temperature ValuesMSB2152142132122112102928
LSB2726252423222120
MSB (BIN)LSB (BIN)VOLTAGE (V)MSB (BIN)LSB (BIN)TEMPERATURE (°C)
0100000000000000+64
0100000000001111+64.059
0101111100000000+95
MSB (BIN)LSB (BIN)VOLTAGE (V)
Monitor/VCCBit Weights
TemperatureBit Weights
Monitor Conversion Example
VCCConversion Examples
Temperature Conversion Examples
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
DS1856
Variable ResistorsThe value of each variable resistor is determined by
a temperature-addressed look-up table, which can
assign a unique value (00h to FFh) to each resistor for
every 2°C increment over the -40°C to +102°C range
(see Table 3). See the Temperature Conversion section
for more information.
The variable resistors can also be used in manual
mode. If the TEN bit equals 0, the resistors are in man-
ual mode and the temperature indexing is disabled.
The user sets the resistors in manual mode by writing
to addresses 82h and 83h in Table 03 to control resis-
tors 0 and 1, respectively.
Memory DescriptionThe memory of the DS1856 is divided into two areas
referred to as the Main Device and the Auxiliary
Device. The Main Device comprises all of the DS1856
specific memory while the Auxiliary Device consists of
128 bytes of general-purpose EEPROM and is espe-
cially useful in GBIC applications. Main and Auxiliary
ADEN
(ADDRESS
ENABLE)
NO. OF SEPARATE
DEVICE
ADDRESSES
ADDITIONAL
INFORMATION2See Figure 21 (Main Device Only)See Figure 3
Table 4. ADEN Address Configuration
ADENADFIXAUXILIARY
ADDRESSMAIN ADDRESS0A0hA2h1A0hEEPROM
(Table 03, 8Ch)0—A2h—EEPROM
(Table 03, 8Ch)
Table 5. ADEN and ADFIX BitsAUXILIARY DEVICE
EEPROM
AUXILIARY MEMORY
(128 BYTES)
00h
7Fh1277F1277F
183B7
199C7
200C8
255FF
2-WIRE ADDRRESS A0hDECHEX
MAIN DEVICE
LOWER MEMORY
TABLE SELECT BYTE
PASSWORD ENTRY
(PWE) (4 BYTES)
00h
7Fh
2-WIRE ADDRESS A2h (DEFAULT)
NOTE 1: ADEN BIT = 0. AUXILIARY MEMORY IS ADDRESSED USING THE AUXILIARY DEVICE
NOTE 1. 2-WIRE SLAVE ADDRESS OF A0h, AND THE REMAINDER OF THE MEMORY IS
NOTE 1. ADDRESSED USING THE MAIN DEVICE 2-WIRE SLAVE ADDRESS OF A2h
NOTE 1. (WHEN ADFIX = 0).
NOTE 2: TABLES 00h, 01h, AND 02h DO NOT EXIST.DEC
MAIN DEVICE
AUXILIAR
Y DEVICE
HEX
TABLE 03h
CONFIGURATION
TABLE
80h
B7h
TABLE 04h
RESISTOR 0
LOOK-UP TABLE
(72 BYTES)
80h
C7h
TABLE 05h
RESISTOR 1
LOOK-UP TABLE
(72 BYTES)
80h
C7h
RESERVED AND
CALIBRATION
CONSTANTS
RESERVED AND
CALIBRATION
CONSTANTS
F0h
FFh
F0h
FFh
Figure 2. Memory Organization, ADEN = 0
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
DS1856memories can be accessed by two separate 2-wire
slave addresses (see Table 4). The Main Device
address is A2h (or determined by the value in Table 03,
byte 8Ch, when ADFIX = 1) and the Auxiliary Device
address is A0h (fixed). A configuration bit, ADEN
(Table 03, byte 89h, bit 5), determines whether the
DS1856 uses one or two 2-wire slave addresses. This
feature can be used to save component count in SFF
applications or other applications where both GBIC
and monitoring functions are implemented and two
device addresses are needed.
The memory organization for ADEN = 0 is shown in
Figure 2. In this configuration, the 128 bytes of
Auxiliary Device EEPROM are located at memory loca-
tions 00h to 7Fh and accessed using the Auxiliary
Device 2-wire slave address of A0h (fixed). The
remainder of the DS1856’s memory is accessed using
the Main Device address.
The memory organization of the second configuration,
ADEN = 1, is shown in Figure 3. In this configuration, all
of the DS1856’s memory including the Auxiliary memo-
ry is accessed using only the Main Device address.
The Auxiliary Device memory is mapped into Table 00
and Table 01 in the Main Device. Both tables map to
the same block of physical memory. This is done to
improve the compatibility between previous members
of this IC family such as the DS1858/DS1859 and the
DS1852. In this configuration, the DS1856 ignores com-
munication using the Auxiliary Device address.
The value of the Main Device address can be changed
to a value other than the default value of A2h (see data
sheet Table 5). There can be up to 128 devices sharing
a common 2-wire bus, with each device having its own
unique address. To change the Main Device address,
first write the desired value to the Chip Address byte
(Table 03, byte 8Ch). Then, enable the new address by
setting ADFIX to a 1. Subsequent 2-wire communica-
tion must be performed using the new Main Device
address. When ADFIX = 0, the Chip Address byte is
ignored, and the Main Device address is set to A2h.
TABLE 00h/01h
EEPROM
AUXILIARY MEMORY
(128 BYTES)
80h
FFh255FF
1277F
183B7
199C7
200C8
LOWER MEMORY
TABLE SELECT BYTE
PASSWORD ENTRY
(PWE) (4 BYTES)
00h
7Fh
2-WIRE ADDRRESS A2h (DEFAULT)
NOTE 1: ADEN BIT = 1. ALL MEMORY (INCLUDING THE AUXILIARY MEMORY) IS ADDRESSED USING THE
NOTE 1: MAIN DEVICE 2-WIRE SLAVE ADDRESS.
NOTE 2: TABLES 00h AND 01h ACCESS THE SAME PHYSICAL MEMORY.
NOTE 3: TABLE 02h DOES NOT EXIST.DECHEX
TABLE 03h
CONFIGURATION
TABLE
80h
B7h
TABLE 04h
RESISTOR 0
LOOK-UP TABLE
(72 BYTES)
80h
C7h
TABLE 05h
RESISTOR 1
LOOK-UP TABLE
(72 BYTES)
80h
C7h
RESERVED AND
CALIBRATION
CONSTANTS
RESERVED AND
CALIBRATION
CONSTANTS
F0h
FFh
F0h
FFh
Figure 3. Memory Organization, ADEN = 1
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
DS1856The DS1856 2-wire interface uses 8-bit addressing,
which allows up to 256 bytes to be addressed tradi-
tionally on a given 2-wire slave address. However,
since the Main Device contains more than 256 bytes, a
table scheme is used. The lower 128 bytes of the Main
Device, memory locations 00h to 7Fh, function as
expected and are independent of the currently select-
ed table. Byte 7Fh is the Table Select byte. This byte
determines which memory table will be accessed by
the 2-wire interface when address locations 80h to FFh
are accessed. Memory locations 80h to FFh are acces-
sible only through the Main Device address. The
Auxiliary Device address has no access to the tables,
but the Auxiliary Device memory can be mapped into
the Main Device’s memory space (by setting ADEN =
1). Valid values for the Table Select byte are shown in
the table below.
Before attempting to read and write any of the bits or
bytes mentioned in this section, it is important to look at
the memory map provided in a subsequent section to
verify what level of password is required. Password
protection is described in the following section.
Password ProtectionThe DS1856 uses two 4-byte passwords to achieve
three levels of access to various memory locations. The
three levels of access are:
User Access:This is the default state after power-up. It
allows read access to standard monitoring and status
functions.
Level 1 Access:This allows access to customer data
table (Tables 00 and 01) in addition to everything grant-
ed by User access. This level is granted by entering
Password 1 (PW1).
Level 2 Access:This allows access to all memory, set-
tings, and features, in addition to everything granted by
Level 1 and User access. This level is granted by enter-
ing Password 2 (PW2).
To obtain a particular level of access, the correspond-
ing password must be entered in the Password Entry
(PWE) bytes located in the Main Device at 7Bh to 7Eh.
The value entered is compared to both the PW1 and
PW2 settings located in Table 03, bytes B0h to B3h and
Table 03, bytes B4h to B7h, respectively, to determine
if access should be granted. Access is granted until
the password is changed or until power is cycled.
Writing PWE can be done with any level of access,
although PWE can never be read.
Writing PW1 and PW2 requires PW2 access. However,
PW1 and PW2 can never be read, even with PW2 access.
On power-up, PWE is set to all 1s (FFFFh). As long as
neither of the passwords are ever changed to FFFFh,
then User access is the power-up default. Likewise,
password protection can be intentionally disabled by
setting the PW2 password to FFFFh.
Memory MapThe following table is the legend used in the memory
map to indicate the access level required for read and
write access.
Each table in the following memory map begins with a
higher level view of a particular portion of the memory
showing information such as row (8 bytes) and byte
names. The tables are then followed, where applicable,
by an Expanded Bytes table, which shows bit names
and values. Furthermore, both tables use the permis-
sion legend to indicate the access required on a row,
byte, and bit level.
The memory map is followed by a Register Description
section, which describes bytes and bits in further detail.
TABLE SELECT
BYTETABLE NAMEAuxiliary Device Memory
(When ADEN = 1)Does Not ExistConfigurationResistor 0 Look-up TableResistor 1 Look-up Table
PERMISSIONREADWRITE<0>
At least one byte in the row is different than
the rest of the row, so look at each byte
separately for permissions.
<1>allPW2
<2>allNA
<3>allall (The part also writes to
this byte.)
<4>PW2PW2 + mode_bit
<5>allall
<6>NAall
<7>PW1PW1
<8>PW2PW2
<9>NAPW2
<10>PW2NA
<11>allPW1
Table 6. Table Select Byte
Table 7. Password Permission
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
DS1856
LOWER MEMORYWord 0Word 1Word 2Word 3Row
(hex)
Row
NameByte 0/8Byte 1/9Byte 2/AByte 3/BByte 4/CByte 5/DByte 6/EByte 7/F<1>Threshold0Temp Alarm HiTemp Alarm LoTemp Warn HiTemp Warn Lo<1>Threshold1VCC Alarm HiVCC Alarm LoVCC Warn HiVCC Warn Lo<1>Threshold2Mon1 Alarm HiMon1 Alarm LoMon1 Warn HiMon1 Warn Lo<1>Threshold3Mon2 Alarm HiMon2 Alarm LoMon2 Warn HiMon2 Warn Lo<1>Threshold4Mon3 Alarm HiMon3 Alarm LoMon3 Warn HiMon3 Warn Lo<1>user ROMEEEEEEEEEEEEEEEE<1>user ROMEEEEEEEEEEEEEEEE<1>user ROMEEEEEEEEEEEEEEEE<1>user ROMEEEEEEEEEEEEEEEE<1>user ROMEEEEEEEEEEEEEEEE<1>user ROMEEEEEEEEEEEEEEEE<1>user ROMEEEEEEEEEEEEEEEE<2>Values0Temp ValueVcc ValueMon1 ValueMon2 Value<0>Values1<2>Mon3 Value<2>Reserved<2>Reserved<0>Status<3>Update<2>Alrm WrnAlarm1Alarm0ReservedReservedWarn1Warn0ReservedReserved<0>Table Select<6>Reserved<6>Reserved<6>Reserved<6>PWE msb<6>PWE lsb<5>Tbl Sel
EXPANDED BYTESBit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0Byte
(hex)
Byte
Namebit15bit14bit13bit12bit11bit10bit9bit8bit7bit6bit5bit4bit3bit2bit1bit0
User EEEEEEEEEEEEEEEEEE
Temp AlarmS262524232221202-12-22-32-42-52-62-72-8
Temp WarnS262524232221202-12-22-32-42-52-62-72-8
Volt Alarm21521421321221121029282726252423222120
Volt Warn21521421321221121029282726252423222120User ROMEEEEEEEEEEEEEEEEUser ROMEEEEEEEEEEEEEEEEUser ROMEEEEEEEEEEEEEEEEUser ROMEEEEEEEEEEEEEEEEUser ROMEEEEEEEEEEEEEEEEUser ROMEEEEEEEEEEEEEEEEUser ROMEEEEEEEEEEEEEEEE
Memory Map
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
DS1856Temp ValueS262524232221202-12-22-32-42-52-62-72-8VCC Value21521421321221121029282726252423222120Mon1 Value21521421321221121029282726252423222120Mon2 Value21521421321221121029282726252423222120Mon3 Value21521421321221121029282726252423222120Status<2>Rhiz<11>SoftHiz<2>Reserved<2>Reserved<2>Reserved<2>TxF<2>RxL<2>RdybUpdateTemp RdyVCC RdyMon1 RdyMon2 RdyMon3 RdyReservedReservedReservedAlarm1Temp HiTemp LoVCC HiVCC LoMon1 HiMon1 LoMon2 HiMon2 LoAlarm0Mon3 HiMon3 LoReservedReservedReservedReservedReservedMintWarn1Temp HiTemp LoVCC HiVCC LoMon1 HiMon1 LoMon2 HiMon2 LoWarn0Mon3 HiMon3 LoReservedReservedReservedReservedReservedReservedPWE msb231230229228227226225224223222221220219218217216PWE lsb21521421321221121029282726252423222120Tbl Sel2726252423222120
AUXILIARY (VALID WHEN ADEN = 0)Word 0Word 1Word 2Word 3Row
(hex)
Row
NameByte 0/8Byte 1/9Byte 2/AByte 3/BByte 4/CByte 5/DByte 6/EByte 7/F
00–7F<1>EEEEEEEEEEEEEEEEEE
TABLE 00/01 (VALID WHEN ADEN = 1)Word 0Word 1Word 2Word 3Row
(hex)
Row
NameByte 0/8Byte 1/9Byte 2/AByte 3/BByte 4/CByte 5/DByte 6/EByte 7/F
80–FF<7>EEEEEEEEEEEEEEEEEE
Memory Map (continued)
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
DS1856
TABLE 03 (CONFIGURATION)Word 0Word 1Word 2Word 3Row
(hex)
Row
NameByte 0/8Byte 1/9Byte 2/AByte 3/BByte 4/CByte 5/DByte 6/EByte 7/F<0>Config0<8>Mode<4>Tindex<4>Res0<4>Res1<8>Reserved<8>Reserved<8>Reserved<8>Reserved<8>Config1Int EnableConfigReservedReservedchip addrReservedRshift1Rshift0<8>Scale0ReservedVcc ScaleMon1 ScaleMon2 Scale<8>Scale1Mon3 ScaleReservedReservedReserved<8>Offset0ReservedVcc OffsetMON1 OffsetMON2 Offset<8>Offset1MON3 OffsetReservedReservedInternal Temp Offset*<9>Pwd ValuePW1 msbPW1 lsbPW2 msbPW2 lsb
EXPANDED BYTESBit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0Byte
(hex)
Byte
Namebit15bit14bit13bit12bit11bit10bit9bit8bit7bit6bit5bit4bit3bit2bit1bit0ModeReservedReservedReservedReservedReservedReservedTENAENTindex2726252423222120Res02726252423222120Res12726252423222120Int EnableTempVccMon1Mon2Mon3ReservedReservedReservedConfigReservedReservedADENADFIXReservedReservedInv 1Inv 2Chip Addr2726252423222120Rshift1ReservedMon12Mon11Mon10ReservedMon22Mon21Mon20Rshift0ReservedMon32Mon31Mon30ReservedReservedReservedReservedVCC Scale21521421321221121029282726252423222120Mon1 Scale21521421321221121029282726252423222120Mon2 Scale21521421321221121029282726252423222120Mon3 Scale21521421321221121029282726252423222120VCC OffsetSS2152142132122112102928272625242322Mon1 OffsetSS2152142132122112102928272625242322Mon2 OffsetSS2152142132122112102928272625242322Mon3 OffsetSS2152142132122112102928272625242322Temp Offset*S2827262524232221202-12-22-32-42-52-6PW1 msb231230229228227226225224223222221220219218217216PW1 lsb21521421321221121029282726252423222120PW2 msb231230229228227226225224223222221220219218217216PW2 lsb21521421321221121029282726252423222120
*The final result must be XOR’ed with BB40h.
Memory Map (continued)
