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DS1852
Optical Transceiver Diagnostic Monitor
FEATURES Implements proposals of SFF-8472 at device address A2h
[Note: requires use of external EEPROM at address
A0h for full compliance.]
Scaleable four-input muxing analog-to-digital converter (ADC)
Direct-to-digital temperature converter
Programmable alarm and warning conditions
Temperature-compensated, programmable three-input muxing
fast comparator
Access temperature, data, and device control through a 2-wire
interface
Operates from 3V or 5V supplies
Packaging: 25-ball BGA
Operating temperature: -40C to +100C
Programming temperature: 0C to +70C
Three levels of security
127 bytes EEPROM for security level 1
128 bytes EEPROM for security level 2
Address space is GBIC compliant (with use of external EEPROM at device address A0h)
ORDERING INFORMATION
DS1852B-000 25-BALL BGA
DS1852B-000+ 25-BALL BGA LF
DS1852B-000+T&R 25-BALL BGA LF T&R
DS1852B-000/T&R 25-BALL BGA T&R
+ Denotes lead-free package.
DESCRIPTION The DS1852 transceiver monitor manages all system monitoring functions in a fiber optic data
transceiver module, in accordance with proposal SFF-8472. Its functions include 2-wire communications
with the host system, EEPROM memory for identification, tracking, and calibration, an ADC with four
muxing inputs, three fast comparators, and a temperature sensor to monitor an optical transceiver. The
DS1852 has programmable alarm and warning flags for all four analog-to-digital (A/D) conversion
values (three user analog inputs plus supply voltage) as well as the temperature. These conditions can be
used to determine critical parameters inside each module. The three fast comparators have temperature-
compensated programmability. The temperature dependencies of the trip points aid in assessing critical
conditions.
5 x 5 BGA (0.8mm pitch)
1 2 3 4 5
Top View
DS1852
Optical Transceiver Diagnostic Monitor
DS1852
The DS1852 is offered for sale free of any royalty or licensing fees.2
pn
ap.
DS1852
PIN DESCRIPTIONS
Name Ball Locations Description
VCC D2, D4, E3 Power-Supply
Terminal. The DS1852 will support supply voltages
ranging from +2.7V to +5.5V.
GND B3, C2, C4, D3
Ground Terminal
SDA B5
2-Wire Serial Data. The serial data pin is for serial data transfer to and from the DS1852. The pin is open drain and may be wire-OR’ed with
other open-drain or open-collector interfaces.
SCL A5
2-Wire Serial Clock. The serial clock input is used to clock data into
the DS1852 on rising edges and clock data out on falling edges.
Bin A3
Analog Input Pin (Bias Value). Input to A/D.
Pin D1
Analog Input Pin (Power Level). Input to A/D.
Rin A2
Analog Input Pin (Received Power). Input to A/D.
ASEL B2
Address Select Pin. If set to logic 0, the device address is A0h. If set to logic 1, the value in Table 3, byte D0h determines the chip address
(factory default is A2h). For SFF-8472 compliance, this pin should be
connected high.
Din C5
Digital Input Pin (TX Disable). Digital input for mirroring in memory map.
RSin B4
Digital Input Pin (Rate Select). Digital input for mirroring in memory map.
Fin E5
Digital Input Pin (TX Fault). Digital input for mirroring in memory
map.
Lin A1
Digital Input Pin (LOS). Digital input for mirroring in memory map.
NC A4, B1, C1, D5,
No Connect E1, E2, E4, C3
DS1852
DS1852 BLOCK DIAGRAM Figure 1
EEPROM
2-WIRE
Interface
Control
Control
Control
Control
Control
Control
Control
Signals
ALARM
and
WARN
ADC
FAST
TRIP
5:1
MUX
3:1
MUX
CONTROL
LOGIC CUSTOMER
EEPROM
CONTROL
SETTINGS
OUTPUT REGISTERS
TEMP
SENSOR
FAST
ALARM
WARN
VCC
GND
SDA
SCL
BIN
PIN
RIN
DS1852
DEVICE OPERATION
Security
To prevent accidental overwrites of key device data, a data lockout feature is incorporated. A 32-bit
password provides access to the “manufacturer” memory locations. These locations are in addition to the
unprotected “user” memory locations:
1) User—This is the default state after power-up; it allows read access to standard IEEE identity table
and standard monitoring and status functions.
2) Manufacturer Level 1—This allows access to customer data table and some selected setups (password
1).
3) Manufacturer Level 2—This allows access to all memory, settings, and features (password 2).
The level 1 password is located in Table 03h EEPROM (bytes D3h to D6h) and may be changed by
gaining access through the level 2 password.
The level 2 password is set in protected EEPROM and is programmed during factory test.
During power-up, the 32-bit password entry (addresses 7Bh to 7Eh) is set to all 1s. This is the value that
is compared to the level 1 password entry in Table 03h to grant level 1 access. Therefore, the level 1
password should not be set to all 1s or the user will gain level 1 access after each power-on.
By default, both passwords are factory preset to 00h.
To gain access to a security level, a 4-byte password is written into Table 00h, bytes 7Bh to 7Eh. If the
written data matches one of the passwords, that corresponding level of access is granted until the
password entry is changed or the power is cycled. Entering the level 2 password allows access to both
the level 1 data and the level 2 data. The 4-byte password is write-only.
DS1852
ANALOG-TO-DIGITAL CONVERTER
The ADC reads a total of five inputs: VCC (internal), temperature (internal), and external inputs Bin, Pin,
and Rin. All conversions are updated every 13ms (nominal) or 20ms (max) in rotation. The conversions
are absolute and compared to an internal reference. While the 16-bit values are read, only the upper 12
are significant. The lower four bits are undefined.
The temperature and analog voltage inputs are calibrated by Dallas Semiconductor and read with the
following scale:
Temperature: High byte: -128C to +127C signed; low byte: 1/256C. The lower four bits
should be ignored.
S 26 25 24 23 22 21 20 -1 2-2 2-3 2-4 2-5 2-6 2-7 2-8
VCC: This reads as an unsigned 16-bit quantity at 100V LSB, with a maximum range of
6.5535V, when using the factory default value. The lower four bits should be ignored.
Bin, Pin, Rin: These read as an unsigned 16-bit quantity at 38.147V LSB, with a maximum range
of 2.500V, when using factory default values. The lower four bits should be ignored. 15 214 213 212 211 210 29 28 7 26 25 24 23 22 21 20
Each analog input has a 16-bit scaling calibration in Table 03h EEPROM. This allows the analog
conversion values to be calibrated for full scale at any input voltage from 0.2V to 6.5535V. The ADC
conversion value will clamp rather than roll over. Each external analog channel has a maximum input
voltage of VCC independent of the calibration factor.
The upper four bits of scaling select the coarse range; the lower 12 bits are for fine adjustments. The
algorithm to trim the scale is described below.
The scaling factors for each input (VCC, VBin, VPin, and VRin) are 16 bits wide. They are located in
Table 03h at addresses C8h to CFh, respectively. The 16 bits are a combination of two trims. The lower
12 bits are binary weighted and give the high resolution trim for scaling the input to output relationship.
The upper four bits are a coarse-adjust of the lower 12 bits. In other words, the upper four bits scale the
LSB value of the binary weighted lower 12 bits.
As an illustration, assume a value of 1V is needed to read full scale. Force a voltage less than 1V
(975mV, for example) to keep clamping out of the way. The closer to max voltage the better, but not too
close.
1) Set the scale trim to 0FFFh (the upper four bits to all zeros and the lower 12 bits to all ones).
2) Use a SAR approach on the upper four bits, starting with 1000b, to find the smallest 4-bit trim
necessary to cause the voltage reading to be above the input (in this case, greater than or equal to
DS1852
bits. This step has now adjusted the LSB of the lower 12 bits so that the best possible trim is
acquired with the lower 12 bits.
If too high a value is used in the four bits, then the resolution of the 12 bits is too high and absolute
accuracy is sacrificed. If too low a value is used in the four bits, then the resolution of the 12 bits is too
small, so a maximum reading is not possible and a large gain error is present through the entire range.
Example code can be found near the end of this data sheet.
POWER-ON LOGIC
VCC is compared to an internal reference voltage, and if it is below VCC minimum, all internal logic and
outputs are held in their reset state. When VCC rises above VCC minimum, the system reset is released.
The DS1852 will not begin monitoring operations until VCC has risen above the analog minimum
voltage. However, communication on the 2-wire bus can occur at a VCC level lower than the analog
minimum voltage. This allows access to the power-on logic bit located in Table 00h, address 6Eh, bit 0.
The analog minimum voltage is less than 2.7V but greater than the digital minimum voltage. Above the
analog minimum voltage, the DS1852 will begin to function in a predictable manner but will not satisfy
specifications until VCC is above 2.7V.
TEMPERATURE-DEPENDENT FAST ALARM COMPARATORS
The DS1852 has a three-input muxing fast alarm comparator with a response time of less than 10µs for
each input. This provides a coarse but fast approximation of whether analog inputs Bin, Pin, and Rin are
above their temperature-dependent value. Each comparator has an 8-bit max value set in Table 03h,
address D8h to E7h. The trip point range is adjustable from 10mV to 2.5V. Each LSB is approximately
10mV. The outputs of these comparators are readable in Table 00h (alarm bytes 1 and 0) and may be
overwritten if their corresponding fast alarm override bit is set in Table 03h EEPROM.
The Bin alarm can be set to eight unique temperature-dependent trip values, which allows the user to set
trip points for different temperature ranges. The Pin/Rin fast alarms act similarly, but can only be set to
four unique temperature-dependent values. For more information, refer to Table 03h.
HIGH-RESOLUTION ALARM COMPARATORS
There are 10 alarm comparators for the five analog channels. There is a 'high alarm' comparator whose
output is active if the analog signal is above its threshold and a 'low alarm' comparator whose output is
active if the analog signal is below its threshold. These comparators have a 2-byte set point in the same
format as the analog converter data in Table 03h. The outputs of these comparators are readable in Table
00h (70h) and may be overwritten if their corresponding alarm override bit is set in Table 03h
EEPROM.
WARNING COMPARATORS
The 10 warning comparators function the same way as the alarm comparators, but can be set to trip at
different levels. Typically, they would be set to trip prior to the alarm comparators. The set points are in
Table 03h and the outputs can be read from Table 00h.
DS1852
DIGITAL INPUTS
The four digital inputs (Din, RSin, Fin, and Lin) can be read through the 2-wire bus. The logic levels at
these inputs are mirrored in the “logic states” byte (6Eh) in Table 00h.
2-WIRE OPERATION
Clock and Data Transitions
The SDA pin is normally pulled high with an external resistor or device. Data on the SDA pin may only
change during SCL low time periods. Data changes during SCL high periods will indicate a start or stop
conditions depending on the conditions discussed below. See Figure 2 for further details.
Start Condition
A high-to-low transition of SDA with SCL high is a start condition that must precede any other
command. See Figure 2 for further details.
Stop Condition
A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop
command places the DS1852 into a low-power mode. See Figure 2 for further details.
Acknowledge Bit
All address bytes and data bytes are transmitted through a serial protocol. The DS1852 pulls SDA low
during the ninth clock pulse to acknowledge that it has received each word.
Standby Mode
The DS1852 features a low-power mode that is automatically enabled after power-on, after a stop
command, and after the completion of all internal operations.
2-Wire Interface Reset
After any interruption in protocol, power loss, or system reset, the following steps reset the DS1852:
1) Clock up to nine cycles.
2) Look for SDA high in each cycle while SCL is high.
3) Create a start condition while SDA is high.
Device Addressing
The DS1852 must receive an 8-bit device address word following a start condition to enable a specific
device for a read or write operation. The address word is clocked into the DS1852 MSB to LSB. The
address word defaults to A0h then the R/W (READ/WRITE) bit when ASEL is a logic zero. If the R/W
bit is high, a read operation is initiated. If R/W is low, a write operation is initiated. The device address
is changed to the internal chip address (Table 03h address D0h) when ASEL is logic one. The default
internal chip address from the factory is A2h.
DS1852
Write Operations
After receiving a matching address byte with the R/W bit set low, the device goes into the write mode of
operation. The master must transmit an 8-bit EEPROM memory address to the device to define the
address where the data is to be written. After the byte has been received, the DS1852 will transmit a zero
for one clock cycle to acknowledge the receipt of the address. The master must then transmit an 8-bit
data word to be written into this address. The DS1852 will again transmit a zero for one clock cycle to
acknowledge the receipt of the data. At this point the master must terminate the write operation with a
stop condition for the write to be initiated. If a start condition is sent in place of the stop condition, the
write is aborted and the data received during that operation is discarded. If the stop condition is received,
the DS1852 enters an internally timed write process (tw) to the EEPROM memory. The DS1852 will not
send an acknowledge bit for any 2-wire communication during the EEPROM write process.
The DS1852 is capable of an 8-byte page write. A page is any 8-byte block of memory starting with an
address evenly divisible by eight and ending with the starting address plus seven. For example,
addresses 00h through 07h constitute one page. Other pages would be addresses 08h through 0Fh, 10h
through 17h, 18h through 1Fh, etc.
A page write is initiated the same way as a byte write, but the master does not send a stop condition after
the first byte. Instead, after the slave has received the data byte, the master can send up to seven more
bytes using the same nine-clock sequence. The master must terminate the write cycle with a stop
condition or the data clocked into the DS1852 will not be latched into permanent memory.
The address counter rolls on a page during a write. The counter does not count through the entire
address space as during a read. For example, if the starting address is 06h and four bytes are written, the
first byte goes into address 06h. The second goes into address 07h. The third goes into address 00h (not
08h). The fourth goes into address 01h. If more than nine or more bytes are written before a stop
condition is sent, the first bytes sent are overwritten. Only the last eight bytes of data are written to the
page.
Acknowledge Polling
Once the internally timed write has started and the DS1852 inputs are disabled, acknowledge polling can
be initiated. The process involves transmitting a start condition followed by the device address. The
R/W bit signifies the type of operation that is desired. The read or write sequence will only be allowed to
proceed if the internal write cycle has completed and the DS1852 responds with a zero.
Read Operations
After receiving a matching address byte with the R/W bit set high, the device goes into the read mode of
operation. There are three read operations: current address read, random read, and sequential address
read.
CURRENT ADDRESS READ
The DS1852 has an internal address register that contains the address used during the last read or write
operation, incremented by one. This data is maintained as long as VCC is valid. If the most recent address
was the last byte in memory, then the register resets to the first address. This address stays valid between
operations as long as power is available.
DS1852
Once the device address is clocked in and acknowledged by the DS1852 with the R/W bit set to high,
the current address data word is clocked out. The master does not respond with a zero, but does generate
a stop condition afterwards.
RANDOM READ
A random read requires a dummy byte write sequence to load in the data word address. Once the device
and data address bytes are clocked in by the master, and acknowledged by the DS1852, the master must
generate another start condition. The master now initiates a current address read by sending the device
address with the R/W bit set high. The DS1852 will acknowledge the device address and serially clocks
out the data byte.
SEQUENTIAL ADDRESS READ
Sequential reads are initiated by either a current address read or a random address read. After the master
receives the first data byte, the master responds with an acknowledge. As long as the DS1852 receives
this acknowledge after a byte is read, the master may clock out additional data words from the DS1852.
After reaching address FFh, it resets to address 00h.
The sequential read operation is terminated when the master initiates a stop condition. The master does
not respond with a zero.
For a more detailed description of 2-wire theory of operation, see 2-WIRE SERIAL PORT OPERATION.
DS1852
2-WIRE SERIAL PORT OPERATION
The 2-wire serial port interface supports a bidirectional data transmission protocol with device
addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as
a receiver. The device that controls the message is called a “master.” The devices that are controlled by
the master are “slaves”. A master device that generates the serial clock (SCL), controls the bus access,
and generates the START and STOP conditions must control the bus. The DS1852 operates as a slave
on the 2-wire bus. Connections to the bus are made through the open-drain I/O lines SDA and SCL. The
following I/O terminals control the 2-wire serial port: SDA, SCL, and ASEL. Timing diagrams for the
2-wire serial port can be found in Figures 2 and 3. Timing information for the 2-wire serial port is
provided in the AC ELECTRICAL CHARACTERISTICS table for 2-wire serial communications.
The following bus protocol has been defined:
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
the data line while the clock line is HIGH will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line from HIGH to LOW while the clock is HIGH
defines a START condition.
Stop data transfer: A change in the state of the data line from LOW to HIGH while the clock line is
HIGH defines the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the HIGH period of the clock signal. The data on the line can be changed
during the LOW period of the clock signal. There is one clock pulse per bit of data. Figures 2 and 3
detail how data transfer is accomplished on the 2-wire bus. Depending upon the state of the R/W bit, two
types of data transfer are possible.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a
ninth bit.
Within the bus specifications a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate)
are defined. The DS1852 works in both modes.
Acknowledge: Each receiving device, when addressed, is obliged to generate an ‘acknowledge’ after
the byte has been received. The master device must generate an extra clock pulse, which is associated
with this acknowledge bit.
DS1852
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is a stable LOW during the HIGH period of the acknowledge-related clock pulse.
Of course, setup and hold times must be taken into account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.
1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is
the command/control byte. Next follows a number of data bytes. The slave returns an acknowledge
bit after each received byte.
2) Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the
command/control byte) to the slave. The slave then returns an acknowledge bit. Next follows a
number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit
after all received bytes other than the last byte. At the end of the last received byte, a ‘not
acknowledge’ can be returned.
The master device generates all serial clock pulses and the START and STOP conditions. A transfer is
ended with a STOP condition or with a repeated START condition. Since a repeated START condition
is also the beginning of the next serial transfer, the bus will not be released.
The DS1852 may operate in the following two modes:
1) Slave receiver mode: Serial data and clock are received through SDA and SCL, respectively. After
each byte is received, an acknowledge bit is transmitted. START and STOP conditions are
recognized as the beginning and end of a serial transfer. Address recognition is performed by
hardware after reception of the slave (device) address and direction bit.
2) Slave transmitter mode: The first byte is received and handled as in the slave receiver mode.
However, in this mode the direction bit will indicate that the transfer direction is reversed. Serial
data is transmitted on SDA by the DS1852 while the serial clock is input on SCL. START and STOP
conditions are recognized as the beginning and end of a serial transfer.
Slave Address: Command/control byte is the first byte received following the START condition from
the master device. The command/control byte consists of a 4-bit control code. For the DS1852, this is set
as 1010 000 (when ASEL is ‘0’) binary for R/W operations. The last bit of the command/control byte
(R/W) defines the operation to be performed. When set to a 1 a read operation is selected, and when set
to a 0 a write operation is selected.
Following the START condition, the DS1852 monitors the SDA bus checking the device type identifier
being transmitted. Upon receiving the chip address control code, and the R/W bit, the slave device
outputs an acknowledge signal on the SDA line.
DS1852
2-WIRE DATA TRANSFER PROTOCOL Figure 2
2-WIRE AC CHARACTERISTICS Figure 3
