DS1843 Fast Delivery |IC PHOENIX CO.,LIMITED

DS1843 ,Fast Sample-and-Hold CircuitApplications Ordering InformationGigabit Passive Optical Network (GPON) OLTPART TEMP RANGE PIN-PACK ..
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DS1844-010 ,Quad Digital PotentiometerPIN DESCRIPTIONV - 2.7V to 5.5VCCPS - Port SelectA0, A1, A2 - Device Select Pins (2-Wire)SDA - Seri ..
DS1844-050 ,Quad Digital PotentiometerFEATURES PIN ASSIGNMENT§ Four independent, digitally controlled 64- PS 1 20 VCCposition ..
DS1844-100 ,Quad Digital Potentiometer DS1844Quad Digital Potentiometerwww.dalsemi.com
DZ23C3V6-7-F , 300mW DUAL SURFACE MOUNT ZENER DIODE
DZ23C3V9-7-F , 300mW DUAL SURFACE MOUNT ZENER DIODE
DZ23C6V2-7-F , 300mW DUAL SURFACE MOUNT ZENER DIODE
DZ23C6V8-7-F , 300mW DUAL SURFACE MOUNT ZENER DIODE
DZ23C8V2 ,Zener DiodesAbsolute Maximum RatingsT = 25

DS1843
Fast Sample-and-Hold Circuit
General Description
The DS1843 is a sample-and-hold circuit useful for cap-
turing fast signals where board space is constrained. It
includes a differential, high-speed switched capacitor
input sample stage, offset nulling circuitry, and an out-
put buffer. The DS1843 is optimized for use in optical
line transmission (OLT) systems for burst-mode RSSI
measurement in conjunction with an external sense
resistor.
Applications
Gigabit Passive Optical Network (GPON) OLT
Gigabit Ethernet Passive Optical Network (GEPON) OLT
GPON Optical Network Unit
Sample and Hold
FeaturesFast Sample Time < 300nsHold Time > 100µsLow Input OffsetBuffered OutputSmall, 8-Pin µDFN (2mm x 2mm) Pb-Free Package
Fast Sample-and-Hold Circuit
Ordering Information
VOUTN
MAIN MEMORY
EEPROM/SRAM
A/D CONFIG/RESULTS,
SYSTEM STATUS BITS,
ALARMS/WARNINGS,
LOOKUP TABLES,
USER MEMORY
CONTROLLER
VINP
VCC
VINN
SEN
GND
VOUTP
VCC
DEN
SDA
SCL
MON1
BIAS
DAC
12-BIT
ADC
MOD
DAC
BMD
SENSTROBESTROBE
MON4
MON3P
MON3N
ANALOG MUX
3.3V
3.3V
TEMP
SENSOR
I2C
INTERFACE
DS1843
DS1842/
MAX4007
RINCIN
CIN
CONTROL
LOGIC
Typical Operating Circuit
19-4539; Rev 1; 2/12
+Denotes a lead(Pb)-free/RoHS-compliant package.
TRL = Tape and reel.
PARTTEMP RANGEPIN-PACKAGE
DS1843D+ -40°C to +85°C 8 µDFN
DS1843D+TRL -40°C to +85°C 8 µDFN
Pin Configuration appears at end of data sheet.
DS1843
Fast Sample-and-Hold Circuit
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
(TA= -40°C to +85°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on VCC.............................................-0.5V to +6V
Voltage Range on VOUTP, VOUTN,
VINP, VINN, SEN, DEN............................-0.5V to (VCC+ 0.5V)*
Continuous Power Dissipation (TA= +70°C)
µDFN (derate 4.8mW/°C above +70°C).....................380.6mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-55°C to +125°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Supply Voltage VCC(Note 1) +2.97 +5.5 V
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.97V to +5.5V, TA= -40°C to +85°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Current ICC (Note 1) 5.7 9 mA
Input Capacitance CINAll pins (Note 2) 7 pF
Sample Capacitance CSVINN and VINP (Note 2) 5 pF
Logic-Input Low VIL SEN and DEN inputs 0.3 x
VCCV
Logic-Input High VIHSEN and DEN inputs 0.7 x
VCC V
Input Leakage IINVINN or VINP, SEN = 0 1 µA
Input Voltage VINVIN = VINP - VINN 0 1.0 V
Output Voltage VOUT VOUT = VOUTP - VOUTN; 100k load on
each output pin 0 1.0 V
Output Impedance ROUTMAX (Note 2) 1 1.3 k
Output Capacitive Load COUT Capacitance for stable operation 50 pF
VCC = 2.9V, 1µs sample time, VIN = 6mV 3.6 6.1 mV Total Input Referenced Voltage
Offset: Differential VOS-DIFFVoltco (VCC = 2.9V to 5.5V) 1 mV/V
VCC = 2.9V, 1µs sample time, VIN = 6mV 3.4 8 mV Total Input Referenced Voltage
Offset: Single-Ended VOS-SEVoltco (VCC = 2.9V to 5.5V) 1 mV/V
*Subject to not exceeding +6V.
Fast Sample-and-Hold Circuit
Note 1:All voltages are referenced to ground. Currents entering the IC are specified positive and currents exiting the IC are negative.
Note 2:Guaranteed by design.
Note 3:VOUTat the end of the 10µs hold time is within specified level of VINduring the sample window; a 50Ωresistor connected in
series to both VINPand VINN(VINP- VINN= 1V). External capacitance to ground for both VINPand VINNis approximately 10pF.
Note 4:The sampling capacitor must be removed from the input signal before the input signal changes. Therefore, the SEN pin
must be low for a short period of time, tDEL, before the input changes.
Note 5:VOUTat the end of the hold time is within 1% of VINduring the sample window (VINP- VINN= 1V).
Note 6:Voltage step applied across VOUTPto VOUTNthrough a 5pF capacitor connected to each pin. This models the load presented
by an ADC while it is sampling the DS1843’s output. See the Output Buffer section. Settled within 1% of initial voltage.
AC ELECTRICAL CHARACTERISTICS
(VCC= +2.97V to +5.5V, TA= -40°C to +85°C, unless otherwise noted.) (See the Timing Diagram.)
PARAMETERSYMBOLCONDITIONS MINTYPMAXUNITS
Sample Time Minimum tSVOUT is within 0.4dB (Note 3) 300 ns
Delay Time Minimum tDEL (Note 4) 10 ns
Output Time tOUT Delay from SEN falling edge until valid
output at VOUT to 1% accuracy 2 µs
Hold Time tHOLD (Note 5) tOUT 100 µs
1V step, DEN = high 2 Output Step Recovery Time
(Note 6) tREC3V step, DEN = high or low 3.5 µs
Timing Diagram
VINP - VINN
VOUTP - VOUTN
EXTERNAL
ADC DATA
tADC:ST = EXTERNAL ADC SAMPLING TIME.
tADC:CT = EXTERNAL ADC CONVERSION TIME.
DEN IS CONNECTED TO VCC FOR DIFFERENTIAL OUTPUT.
NOTE: THIS TIMING DIAGRAM IS APPLICABLE FOR SINGLE-ENDED AND DIFFERENTIAL OUTPUT CONFIGURATIONS.
SENtDEL
tOUT
tADC:ST
DATA VALID
tADC:CT
tREC
tHOLD
VOLTAGE INVALID
DS1843
Fast Sample-and-Hold Circuit
ICC vs. VCC
DS1843 toc01
VCC (V)
(mA)
DEN = GND
DEN = VCC
ICC vs. TEMPERATURE
DS1843 toc02
TEMPERATURE (°C)
ICC
(mA)3510-15
DEN = VCC
VCC = 5V
VCC = 3.3V
ICC vs. TEMPERATURE
DS1843 toc03
TEMPERATURE (°C)
ICC
(mA)3510-15
DEN = GND
VCC = 5V
VCC = 3.3V
OUTPUT HOLD TIME vs. TEMPERATURE
DS1843 toc04
TEMPERATURE (°C)
OUTPUT HOLD TIME (SECONDS)3510-15
DEN = VCC
OUTPUT HOLD TIME vs. TEMPERATURE
DS1843 toc05
TEMPERATURE (°C)
OUTPUT HOLD TIME (SECONDS)3510-15
DEN = GND
DIFFERENTIAL OUTPUT DURING SAMPLING
(VINP = 6mV)
DS1843 toc06
500ns/div
5mV/div
VOUTPVOUTN
VSEN
VOUTP - VOUTN
100mV/div
1.5V/div
SINGLE-ENDED OUTPUT DURING SAMPLING
(VINP = 6mV)
DS1843 toc07
2mV/div
1.5V/div
100mV/div
VOUTP
VSEN
ZOOMED
VOUTP ZOOM
500ns/div
DIFFERENTIAL OUTPUT, TRANSIENT
WITH 10% VCC STEP (VINP = 6mV)
DS1843 toc08
5mV/div
VOUTPVOUTN
VSEN
VOUTP - VOUTN
100mV/div
VCC = 3.3V
1V/div
VCC = 3.0V
SINGLE-ENDED OUTPUT, TRANSIENT
WITH 10% VCC STEP (VINP = 6mV)
DS1843 toc09
2.0V/div
100mV/div
VCC = 3.0V
VCC = 3.3V
VOUTP
VSEN
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
Fast Sample-and-Hold Circuit
DIFFERENTIAL OUTPUT, TRANSIENT
WITH 10% VCC STEP (VINP = 1V)
DS1843 toc10
100μs/div
200mV/div
2V/div
1V/div
VCC = 3.3V
VCC = 3.0V
VOUTP
VOUTN
VSEN
VOUTP - VOUTN
SINGLE-ENDED OUTPUT, TRANSIENT
WITH 10% VCC STEP (VINP = 1V)
DS1843 toc11
100μs/div
2V/div
1V/div
VCC = 3V
VCC = 3.3V
VOUTP
VSEN
DIFFERENTIAL OUTPUT STEP RECOVERY,
1V OUTPUT STEP (VINP = 6mV)
DS1843 toc12
50μs/div
10mV/div
200mV/div
VOUTP (200mV/div)
VSEN (1V/div)
VOUTN (200mV/div)
VOUTP - VOUTN
SINGLE-ENDED STEP RECOVERY,
1V OUTPUT STEP (VINP = 1V)
DS1843 toc13
50μs/div
VOUTP (200mV/div)
VSEN (1V/div)
VOUTP STEP (200mV/div)
SINGLE-ENDED OUTPUT, STEP RECOVERY,
1V OUTPUT STEP (VINP = 1V, ZOOMED IN)
DS1843 toc14
50ns/div
500mV/div
500mV/div
VOUTP
DIFFERENTIAL OUTPUT STEP RECOVERY,
1V OUTPUT STEP (VINP = 1V)
DS1843 toc15
50μs/div
VOUTP (200mV/div)
VSEN (1V/div)
VOUTP - VOUTN
OUTPUT STEP (200mV/div)
VOUTN (200mV/div)
200mV/div
DIFFERENTIAL OUTPUT STEP RECOVERY,
1V OUTPUT STEP (VINP = 1V, ZOOMED IN)
DS1843 toc16
VOUTP
VOUTP - VOUTN
(200mV/div)VOUTN (200mV/div)
200mV/div
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
DS1843
Fast Sample-and-Hold Circuit
Detailed Description
The DS1843 consists of a fully differential sampling
capacitor, switches, and a differential output buffer. It is
designed to operate in fiber optic burst-mode systems;
however, it can be used in other applications requiring
a fast sample-and-hold circuit. The output can be con-
figured for single-ended operations.
Input Sampling Capacitor
The input voltage is sampled using a 5pF capacitor on
the positive input and another on the negative input.
The capacitors are connected to the input when SEN is
high. In addition to the sampling capacitors, the inputs
also have parasitic capacitance (CIN). These capaci-
tors must fully charge before SEN is switched to low in
order to ensure accurate sampling. An RC time con-
stant is created by the resistance of the voltage source
connected to the DS1843’s input and the capacitances
on this node. See the Applications Informationsection
for details.
Output Buffer
After sampling is complete, the sampling capacitor is
switched to the output buffer. This buffer requires a
small amount of time to settle, tOUT. When an ADC is
used to measure the DS1843’s output, a step occurs at
the ADC’s input caused by the ADC’s internal sampling
capacitor. The DS1843’s recovery time, tREC, is depen-
dent on the size of the ADC’s sampling capacitor and
the voltage applied across the ADC. To maximize
accuracy, the ADC’s sampling speed (ADC clock fre-
quency) should be reduced until the ADC’s conversion
window (tADC:ST, as shown in the Timing Diagram) is
larger than the DS1843’s recovery time. Refer to the
ADC’s documentation for tADC:ST.
Sampling Time and Output Error
As the sampling time (tS) is decreased, the output error
increases. The output error is largely dependent on the
settling time of the sampling capacitor and, to a lesser
degree, the output buffer’s gain error and offset volt-
age. Settling time can be reduced by driving the
DS1843 with a lower impedance. In a typical fiber optic
application, a current is applied across a 5kΩresistor.
By using a stronger current source, the resistance and
the settling time can be reduced (see the Applications
Informationsection for details).
Pin Description
PINNAMEFUNCTION
1 VCC Power-Supply Input
2 VINP Positive Voltage Input. Input to sample circuit.
3 VINN Negative Voltage Input. Input to sample circuit. DEN Differential Output Enable. Connect to VCC for differential output or GND for single-ended output.
5 GND Ground Terminal
6 VOUTNSampled Voltage Negative Output. Buffered output of the hold capacitor. Keep unconnected or
connect to GND for single-ended output mode.
7 VOUTP Sampled Voltage Positive Output and Single-Ended Output. Buffered output of the hold capacitor. SEN Sample Enable. Enables input sampling. This input is pulsed.
Block Diagram
DS1843
VOUTN
VCC
VINP
VINN
SEN
GND
CIN
CINVOUTP
CONTROL
LOGIC
DEN

Partno	Mfg	Dc	Qty	Available	Descript
DS1843		N/a	677	avai	Fast Sample-and-Hold Circuit