DS1842 Fast Delivery |IC PHOENIX CO.,LIMITED

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DZ23C3V6-7-F , 300mW DUAL SURFACE MOUNT ZENER DIODE
DZ23C3V9-7-F , 300mW DUAL SURFACE MOUNT ZENER DIODE
DZ23C6V2-7-F , 300mW DUAL SURFACE MOUNT ZENER DIODE
DZ23C6V8-7-F , 300mW DUAL SURFACE MOUNT ZENER DIODE
DZ23C8V2 ,Zener DiodesAbsolute Maximum RatingsT = 25

DS1842
76V, APD, Bias Output Stage with Current Monitoring
General Description
The DS1842 integrates the discrete high-voltage com-
ponents necessary for avalanche photodiode (APD)
bias and monitor applications. A switch FET is used in
conjunction with an external DC-DC controller to create
a boost DC-DC converter. A current clamp limits cur-
rent through the APD and also features an external
shutdown. The device also includes a dual current mir-
ror to monitor the APD current.
Applications
APD Biasing
GPON Optical Network Unit and Optical Line
Transmission
Features76V Maximum Boost VoltageSwitch FETCurrent Monitor with a Wide 1µA to 2mA Range,
Fast 50ns Time Constant, and 10:1 and 5:1 Ratio2mA Current Clamp with External ShutdownMultiple External Filtering Options3mm x 3mm, 14-Pin TDFN Package with Exposed Pad
DS1842
76V, APD, Bias Output Stage with
Current Monitoring
Ordering Information
19-4557; Rev 1; 3/11
PART TEMP RANGE PIN-PACKAGE
DS1842N+ -40°C to +85°C 14 TDFN-EP*
DS1842N+T&R -40°C to +85°C 14 TDFN-EP*
Pin Configuration appears at end of data sheet.+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
*EP = Exposed pad.
DS1875
DS1842
COMP
MON3
GATE
GND
MIRIN
MIR1
CLAMP
MIROUT
3.3V
CURRENT MIRROR
CURRENT
LIMITMIR2
CBULK
CCOMPRCOMP
EXTERNAL MONITOR
TIA
APD
ROSA
Typical Application Circuit
DS1842
76V, APD, Bias Output Stage with
Current Monitoring
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(TA= -40°C to +85°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 2:Rising MIROUT transition from 10µA to 1mA; VMIRIN= 40V, 2.5kΩload.
Note 3:Guaranteed by design; not production tested.
Voltage Range on GATE and CLAMP
Relative to GND...................................................-0.3V to +12V
Voltage Range on MIRIN, MIROUT,
MIR1, and MIR2 Relative to GND........................-0.3V to +80V
Voltage Range on LX Relative to GND...................-0.3V to +85V
Continuous Power Dissipation (TA= +70°C)
TDFN (derate 24.4mW/°C above +70°C).................1951.2mW
Operating Junction Temperature Range...........-40°C to +150°C
Storage Temperature Range.............................-55°C to +135°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TDFN
Junction-to-Ambient Thermal Resistance (θJA)............41°C/W
Junction-to-Case Thermal Resistance (θJC)...................8°C/W
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Switching Frequency fSW 0 1.2 MHz
CGATE VGS = 0V, VDS = 25V 40 FET Capacitance
CLX fSW= 1MHz 90
pF
FET Gate Resistance RG 22
VGS = 3V, ID= 170mA 4.6 10 FET On-Resistance RDSON VGS = 10V, ID= 170mA 3.7 8
GATE Voltage VGS 0 11 V
Switching Current ILX Duty cycle = 10%, fSW= 100kHz 680 mA
LX Voltage VLX 80 V
LX Leakage IIL(LX) VGATE = 0V, VLX = 76V -1 +1μA
CLAMP Voltage VCLAMP 0 11 V
CLAMP Threshold VCLT 2 4 7 V
CLAMP = low1.75 2.6 4 mA Maximum MIROUT Current IMIROUT CLAMP = high 10 μA
IMIROUT = 1mA 0.095 0.100 0.105
IMIROUT = 1μA 0.094 0.100 0.106 MIR1 to MIROUT Ratio KMIR1
15V < VMIRIN < 76V
A/A
IMIROUT = 1mA 0.190 0.200 0.210
IMIROUT = 1μA 0.188 0.200 0.212 MIR2 to MIROUT Ratio KMIR2
15V < VMIRIN < 76V
A/A
MIR1, MIR2 Rise Time (20%/80%) tRC (Note 2) 30 ns
Shutdown Temperature TSHDN (Note 3) +150 °C
Leakage on GATE and CLAMP IIL -1 +1 μA
Note 1:Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to /thermal-tutorial.
DS1842
76V, APD, Bias Output Stage with
Current Monitoring
MIRIN vs. MIROUT CURRENT
(VMIRIN = 40V)
DS1842 toc01
MIROUT CURRENT (µA)
MIRIN CURRENT (
10,00010,000
MIRIN CURRENT vs. TEMPERATURE
(VMIRIN = 40V, IMIROUT = 250nA)
DS1842 toc02
TEMPERATURE (°C)
MIRIN CURRENT (6020400-20
MIRIN CURRENT vs. TEMPERATURE
(VMIRIN = 40V, IMIROUT = 2mA)
DS1842 toc03
TEMPERATURE (°C)
MIRIN CURRENT (mA)6040200-20
MIR ERROR vs. TEMPERATURE
(IMIROUT = 1µA)
DS1842 toc04
TEMPERATURE (°C)
ERROR (%)6040200-20
MIR1
MIR2
MIR ERROR vs. TEMPERATURE
(IMIROUT = 1mA)
DS1842 toc05
TEMPERATURE (°C)
ERROR (%)6040200-20
MIR1
MIR2
MIR ERROR vs. MIROUT CURRENT
DS1842 toc06
MIROUT CURRENT (µA)
ERROR (%)
10001001010,000
MIR1
MIR2
MIR ERROR vs. MIRIN VOLTAGE
DS1842 toc07
MIRIN VOLTAGE (V)
ERROR (%)605040302080
MIR2 1µA
MIR2 1mA
MIR1 1µA
MIR1 1mA
MIROUT CLAMP CURRENT
vs. TEMPERATURE
DS1842 toc08
TEMPERATURE (°C)
IMIROUT
(mA)6040200-20
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
DS1842
76V, APD, Bias Output Stage with
Current Monitoring
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
FET ON-RESISTANCE vs. DRAIN CURRENT
DS1842 toc09
IDS (mA)
DSON
VGS = 2.5V
VGS = 3.0V
VGS = 3.6V
VGS = 5VVGS = 10V
FET DRAIN CURRENT vs. DRAIN VOLTAGE
DS1842 toc10
DRAIN VOLTAGE (V)
IDS
(mA)21
VGS = 2.5V
VGS = 3.0V
VGS = 3.6V
VGS = 5V
VGS = 10V
Pin Description
PINNAMEFUNCTIONMIR1 Current Mirror Monitor Output, 10:1 Ratio MIR2 Current Mirror Monitor Output, 5:1 Ratio
3 N.C. No Connection. Can be connected to
GND for compatibility with the DS1842A.
9–12 N.C.No Connection. Not internally
connected.
5 CLAMPClamp Input. Disables the current mirror
output (MIROUT).
6 GATEFET Gate Connection
7 GNDGround
8 LXFET Drain Connection. Connect to
switching inductor.
13 MIRINCurrent Mirror Input
14 MIROUTCurrent Mirror Output. Connect to APD
bias pin. EP Exposed Pad. Connect to ground.
Block Diagram
DS1842LX
GATE
GND
MIRIN
MIR1
CLAMP
MIROUT
CURRENT MIRROR
CURRENT
LIMIT
MIR2
THERMAL
SHUTDOWN
DS1842
76V, APD, Bias Output Stage with
Current Monitoring
Detailed Description
The DS1842 contains discrete high-voltage compo-
nents required to create an APD bias voltage and to
monitor the APD bias current. The device’s mirror out-
puts are a current that is a precise ratio of the output
current across a large dynamic range. The mirror
response time is fast enough to comply with GPON Rx
burst-mode monitoring requirements. The device has a
built-in current-limiting feature to protect APDs. The
APD current can also be shut down by CLAMP or ther-
mal shutdown. The internal FET is used in conjunction
with a DC-DC boost controller to precisely create the
APD bias voltage.
Current Mirror
The DS1842 has two current mirror outputs. One is a
10:1 mirror connected at MIR1, and the other is a 5:1
mirror connected to MIR2.
The mirror output is typically connected to an ADC
using a resistor to convert the mirrored current into a
voltage. The resistor to ground should be selected such
that the maximum full-scale voltage of the ADC is
reached when the maximum mirrored current is
reached. For example, if the maximum monitored cur-
rent through the APD is 2mA with a 1V ADC full scale,
and the 10:1 mirror is used, then the correct resistor is
approximately 5kΩ. If both MIR1 and MIR2 are con-
nected together, the correct resistor is 1.6kΩ.
The mirror response time is dominated by the amount
of capacitance placed on the output. For burst-mode
Rx systems where the fastest response times are
required (approximately a 50ns time constant), a 3.3pF
capacitor and external op amp should be used to
buffer the signal sent to the ADC. For continuous mode
applications, a 10nF capacitor is all that is required on
the output.
Current Clamp
The DS1842 has a current clamping circuit to protect
the APD by limiting the amount of current from MIROUT.
There are three methods of current clamping available.
1) Internally Defined Current Limit
The device’s current clamp circuit automatically clamps
the current when it exceeds ICLAMP.
2) External Shutdown Signal
The CLAMP pin can completely shut down the current
from MIROUT. The CLAMP pin is active high.
3) Precise Level Set by External Feedback Circuit
A feedback circuit is used to control the level applied to
the CLAMP pin. Figure 1 shows an example feedback
circuit.
Thermal Shutdown
As a safety feature, the DS1842 has a thermal-shut-
down circuit that turns off the MIROUT and MIRIN cur-
rents when the internal die temperature exceeds
TSHDN. These currents resume after the device has
cooled.
Switch FET and Diode
The DS1842 switching FET is designed to complement
the DS1875 controller’s built-in DC-DC boost controller.
Other DC-DC converters are also compatible, including
the MAX1932. APD biasing of 16V to 76V can be
achieved using the DS1842.
CLAMP
MIR1
REF
Figure 1. Current Clamp from Current Feedback
DS1842
76V, APD, Bias Output Stage with
Current Monitoring
TDFN
TOP VIEW
MIRIN
N.C.
N.C.
MIR2
N.C.
CLAMP14MIROUTMIR112N.C.N.C.9N.C.GATE8LXGND
DS1842
*EP
*EXPOSED PAD.
Pin ConfigurationPackage Information
For the latest package outline information and land patterns
(footprints), go to /packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
14 TDFN-EPT1433+221-013790-0063

Partno	Mfg	Dc	Qty	Available	Descript
DS1842	DS	N/a	55	avai	76V, APD, Bias Output Stage with Current Monitoring