DS1780E ,CPU Peripheral MonitorApplications include monitoring of personal SCL - 2-Wire Serial Clock computers or any microprocess ..
DS1780E ,CPU Peripheral MonitorPin Description Table 1 PIN SIGNAL DIRECTION DESCRIPTION The lowest order programmable bit of the 2 ..
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DS17885-5 ,3V/5V Real-Time Clockfeatures:X1 23 SQW2 Y2K compliantVBAUXX2 3 22 +3V or +5V operationAD0 4 21 RCLR SMI recovery sta ..
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DVIULC6-2P6 ,Ultra Low capacitance 2 lines ESD protectionApplicationsBenefits■ DVI ports up to 1.65 Gb/s■ ESD standards compliance guaranteed at ■ IEEE 1394 ..
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DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DS1780E
CPU Peripheral Monitor
FEATURES Direct-to-digital temperature sensor requires
no external components or user calibration
Two fan speed sensors
Monitors 6 power supply voltages
8-bit DAC for fan speed control
Intrusion detect for security (detects when
chassis lid has been removed, even if power is
off)
Remote system reset
System interrupt availability on all monitored
functions (temperature, voltages, fan speed,
chassis intrusion)
2-wire interface with 2-bit addressability
Integrated NAND TREE for board level
testability
Wide power supply range (2.8V VDD
5.75V)
High integration in a small 24-pin 173-mil
TSSOP
Applications include monitoring of personal
computers or any microprocessor-based
system
PIN ASSIGNMENT
PIN DESCRIPTION A0/NTOUT - Address Input / NAND
TREE Output
A1 - Address Input
SDA - 2-Wire Serial Data Input/Output
SCL - 2-Wire Serial Clock
FANx - Tachometer Inputs
CHS - Chassis Intrusion Detector Input
GNDD - Digital Ground
VDD - Power Supply Voltage (2.8V to 5.75V)
INT - Hardware Interrupt output
VOUT/NTIN - DAC output / NAND TREE Input
RST - Remote System Reset
GNDA - Analog Ground
+xxVIN - Positive Voltage Inputs
+2.5VS/+VCCP2 - Positive/negative Voltage Input
VIDx - Processor Voltage Supply Readout Inputs
See Table 11 on page 27 for Ordering Information
DS1780
CPU Peripheral Monitor
www.dalsemi.com DS1780E+
24-Pin TSSOP (173-mil)
VID0
VID
VID2
VID3
VID4
+VCCP1
+2.5 VIN
+3.3 VIN
+5 VIN
+12 VIN
+2.5 VS/+VCCP2
GNDA
SDA
FAN1
CHS
GNDD
VDD
INT
VOUT/NTIN
RST
SCL
FAN2
A0/NTOUT
DS1780
DESCRIPTION The DS1780 is a highly integrated system instrumentation monitor ideal for use in personal computers, or
any microprocessor-based system. It monitors ambient temperature, six power supply voltages, and the
speed of two fans. Fan speed can also be controlled with the use of an internal 8-bit DAC. All
measurements are internally converted to a digital format for easy processing by the CPU.
The DS1780 can be reset to its default power-up state via a remote reset function with internal debounce
and delay. It features an interrupt that can be programmed to become active should any of the functions
the DS1780 is monitoring fall out of spec.
For board-level testability, an internal NAND TREE function simplifies the system design. A chassis
intrusion input is featured to enhance system security.
Programming and data readout are accessed via a simple 2-wire interface with 2-bit addressability. The
DS1780 power supply range of 2.8V to 5.75V allows for monitoring of parameters for 3V or 5V systems.
The DS1780 is assembled in a compact 173-mil TSSOP package.
Detailed Pin Description Table 1
PIN SIGNAL DIRECTION DESCRIPTION 1 A0/NTOUT Digital I/O The lowest order programmable bit of the 2-wire bus address. This pin
functions as an output when doing a NAND TREE test. A1 Digital Input The highest order programmable bit of the 2-wire bus address. SDA Digital I/O 2-wire bus bi-directional data. Open-drain output. SCL Digital Input 2-wire bus synchronous clock. FAN1 Digital Input 0 to VDD amplitude fan tachometer input. FAN2 Digital Input 0 to VDD amplitude fan tachometer input.
7 CHS Digital I/O
An active high input from an external circuit, which latches a Chassis
Intrusion event. This line can go high without any clamping action regardless
of the powered state of the DS1780. The DS1780 provides an internal open
drain on this line, controlled by Bit 6 of Configuration Register, to provide a
minimum 20 ms reset of this signal. GNDD GROUND Internally connected to all digital circuitry.
9 VDD POWER +3.3V or +5V VDD power. Bypass with the parallel combination of 10 µF
(Electrolytic or Tantalum) and 0.1 µF (ceramic) bypass capacitors.
10 INT Digital Output Active-low Programmable interrupt output. The output is enabled when Bit 1
of the Configuration Register is set to 1. The default state is disabled.
11 VOUT/NTIN Digital Input/
Analog Output
An active-high input that enables NAND Tree board-level connectivity
testing. Refer to “NAND Tree Testing” Section. Used as DAC output when
NAND Tree is not selected.
12 RST Digital I/O
Master Reset, 5 mA open drain driver, active low output with at least a 20 ms
minimum pulse width. Available when enabled via Bit 4 in Configuration
Register. This is a bi-directional I/O pin. It acts as power on RESET input.
13 GNDA GROUND Internally connected to all analog circuitry. The ground reference for all
analog inputs.
14 +2.5VS/+VCCP2 Analog Input
Analog input for monitoring -12V or +VCCP2. DS1780 will measure voltages
on this pin from 0V to 3.6V. An external resistor ladder is required for
monitoring a -12V supply (see Figure 1).
15-19 +xxVIN Analog Inputs A/D inputs for 5 positive voltages.
20-24 VIDx Digital Inputs Voltage supply readouts from the processor. These values are read in the VID
and VID4 Status Registers.
DS1780
OVERVIEW A block diagram of the DS1780 is shown in Figure 1.
The DS1780 provides six analog inputs, an analog output, five digital inputs, two fan speed inputs, a
temperature sensor, and interrupt registers on a single chip, which communicates on a 2-wire serial bus.
The DS1780 performs power supply, temperature, and fan monitoring for personal computers.
The analog voltages are divided internally by the DS1780. The inputs are then converted to 8-bit digital
words. The analog inputs are intended to be connected to the several power supplies present in a typical
computer. Temperature can be converted to a 9-bit two’s-complement digital word with a 0.5°C LSb.
The analog output is approximately a 0-1.25V output from an 8-bit D/A converter, which is used to
control fan speeds.
Fan inputs measure the period of tachometer pulses from the fans, providing a higher count for lower fan
speeds. The fan inputs are digital inputs with an acceptable range of 0 to VDD volts and a transition level
of approximately 1.4 volts. Full-scale fan counts are 255 (8-bit counter) and this represents a stopped or
very slow fan. Nominal speeds, based on a count of 153, are programmable from 1100 to 8800 RPM on
FAN1 and FAN2. Signal conditioning circuitry is included to accommodate slow rise and fall times.
The DS1780 provides a number of internal registers, as detailed in Table 1. These include:
Configuration Register: Provides control and configuration, as well as initialization.
Interrupt (INT) Status Registers: Two registers to provide status of each interrupt limit or interrupt event.
Interrupt (INT) Mask Registers: Allows masking of individual Interrupt sources, as well as separate
masking for the hardware interrupt output.
Temperature Configuration Register: The lower 2 bits of this register configure the type of
temperature interrupt mode to be used. Bit 7 reflects the lowest bit of the temperature reading.
VID Register, VID4 Register: Bits 0-3 of the VID register reflect the status of the VID0-VID3 pins, bit 0 of the VID4 register reflect the status of VID4 pin. These are simply input pins - not processed in any
way. In a multiprocessor system, these signals will be multiplexed externally from the various processor
sources, with the source being controlled by software.
Value RAM: The monitoring results and limits for temperature, voltages, and fan counts are all
contained in the Value RAM.
When the DS1780 is started, it cycles through each measurement in sequence, and it continuously loops
through the sequence approximately once every second. Each measured value is compared to values
stored in limit registers. When the measured value violates the programmed limit the DS1780 will set a
corresponding System Management Interrupt (SMI) in the Interrupt Status Registers. One hardware
interrupt line, INT, is available to generate an SMI. INT is fully programmable with masking of each
Interrupt source, and masking of the output. In addition, the configuration register has control bits to
DS1780
A CHS (Chassis Intrusion) digital input is provided. The Chassis Intrusion input is designed to accept an
active high signal from an external circuit that latches when the case is removed from the computer; this
pin is a dual purpose pin which will be driven low by the DS1780 to reset the external circuit.
DS1780 FUNCTIONAL BLOCK DIAGRAM Figure 1
Note: R1 and R2 on the -12V resistance ladder should be ratioed such that approximately +2.5V appears at the input pin (i.e., R1=4kΩ, R2=23.2 kΩ). If a second processor voltage needs to be monitored (VCCP2),
leave R2 empty, and make R1 500Ω, with VCCP2 appearing here.
2-WIRE SERIAL DATA BUS When using the 2-wire bus, a write will always consist of the DS1780 2-wire slave address, followed by
the Internal Address Register byte, then the data byte. The Internal Address Register addresses are listed
below in Table 2. There are two cases for a read:
1. If the Internal Address Register is known to be at the desired Address, simply read the DS1780 with
the 2-wire slave address, followed by the data byte read from the DS1780.
2. If the Internal Address Register value is unknown, write to the DS1780 with the 2-wire slave address,
followed by the Internal Address Register byte. Then restart the Serial Communication with a Read
consisting of the 2-wire slave address, followed by the data byte read from the DS1780.
The default power-on 2-wire slave address for the DS1780 is 01011(A1)(A0) binary, where A0-A1
reflects the state of the pins defined by the same names. The address can be changed by writing any
desired value to the 2-wire Serial Address Register (excluding the 2 LSBs). This communication protocol
DS1780
INTERNAL ADDRESS REGISTER MAP Table 2
REGISTER DS1780 INTERNAL
HEX ADDRESS POWER ON VALUE NOTES Configuration Register 40h 0000 1000
Interrupt (INT) Status
Register 1 41h 0000 0000
Interrupt (INT) Status
Register 2 42h 0000 0000
Interrupt (INT) Mask
Register 1 43h 0000 0000
Interrupt (INT) Mask
Register 2 44h 0000 0000
Chassis Intrusion Clear
Register 46h 0000 0000
Bit 7 of this register
clears Chassis Intrusion.
The other bits are
reserved.
VID Register 47h 0101 XXXX
The lower 4 bits reflect
the state of
VID0-VID3 pins.
Serial Address Register 48h 0010 11XY X Reflects state of A1
and Y Reflects A0 state
VID4 Register 49h 1000 000X Bit 0 = VID 4. The rest
are reserved.
Temperature
Configuration
Register
4Bh 0000 0001
Test Register 15h 0000 0000 Do not alter the
contents of the register.
Analog output 19h 1111 1111 Full on
Value RAM 20h-3Dh
Company ID 3Eh 1101 1010 Read only
Stepping 3Fh 0000 0001 Read only
DS1780
2-WIRE SERIAL COMMUNICATION WITH THE DS1780 Figure 2
OPERATION - Power-on Applying power to the DS1780 causes a reset of several of the registers. Power-on conditions of the
registers are shown in Table 2 above. Some registers have indeterminate power-on values, such as the
Limit and RAM registers of the Value RAM page, and these are not shown in the table. Upon power-up
the ADC is inactive. Writing Limits into the Value RAM should usually be the first action performed
after power up. The RST pin is bi-directional. It forces RESET at power-on, but can also be pulled low to
force RESET internally.
OPERATION - Resets The DS1780 features four distinct resetting functions. Each one has a different effect on register contents
and the state of the RST output following the event. Each one is explained below:
Power-on Reset - On POR, all internal logic is reset, and registers are cleared to their default state (see tables 10.x). Because Value RAM is typically the first area programmed upon power-up, it does not have
a defined state upon POR. Also, on POR, the RST output will be pulled to an active low state for 20 ms
(minimum).
A POR occurs every time VDD crosses the voltage level approximately equivalent to the sum of one n-
channel threshold (VTN) and one p-channel threshold (VTP), on a power-up or power-down condition.
DS1780 SRAM contents get “scrambled” when VDD falls below the greater of one n-channel VT or one p-
channel VT. Therefore, SRAM contents will always be in a defined state as supply voltage reaches the
DS1780
Software Reset - This condition is generated by writing a 1 to bit 4 of the configuration register. It has no effect on DS1780 register contents. It will however pull the RST output to the active low state for a
duration of 20 ms (minimum). When the RST output goes active, this bit in the configuration register will
clear itself. A Software Reset is only possible if Bit 7 of the INT Mask Register 2 (0x44h) is set to “1”.
Device Initialization - This condition is generated by writing a 1 to bit 7 of the configuration register. It will clear all registers in DS1780 memory to their default state except the Value RAM (0x20h - 0x3Dh)
and analog output (0x19h). These locations will remain unchanged from their state before the
initialization. This condition has no effect on the RST output. This bit is self-clearing.
Hardware Reset - This condition is generated by some external source pulling the RST pin below
VIN(0) (see DC Electrical Characteristics). The DS1780 will then force the RST signal to remain in the
active low state for >20 ms. It will clear all registers in DS1780 memory to their default state except the
Value RAM (0x20h - 0x3Dh) and analog output (0x19h). These locations will remain unchanged from
their state before the Hardware Reset.
OPERATION - Configuration Register Control of the DS1780 is provided through the configuration register. The Configuration Register is used
to start and stop the DS1780, enable or disable interrupt output and modes, and provide the initialization
function described above.
Bit 0 of the Configuration Register controls the monitoring loop of the DS1780. Setting Bit 0 low stops
the monitoring loop and puts the DS1780 into a standby mode. 2-Wire Bus communication is still
possible with any register in the DS1780 during the standby mode, however. Additionally, the DS1780
will continue to monitor the RST and CHS inputs while in a standby mode. Setting Bit 0 high starts the
monitoring loop.
Bit 1 of the Configuration Register enables or disables the INT Interrupt output. Setting Bit 1 high
enables the INT output, setting bit 1 low disables the output.
Bit 3 of the Configuration Register is used to clear the INT interrupt output when set high. The DS1780
monitoring function will stop until bit 3 is set low. Interrupt Status register contents will not be affected.
Bit 4 of the Configuration Register is used to initiate a minimum 20 ms RESET signal on the RST output
if the pin is configured for the RESET mode (via bit 7 of the INT Mask Register 2 - 0x44h).
Bit 6 of the Configuration Register is used to reset the Chassis Intrusion (CHS) output pin when set high.
Bit 7 of the Configuration Register is used to start a Configuration Register Initialization when taken
high, as described in the “OPERATION - Resets” section.
OPERATION - Monitoring Loop The DS1780 monitoring function is started by doing a write to the Configuration Register and setting the
INT_Clear (Bit 3) low, and Start (Bit 0) high. At this point the INT_Enable (Bit 1) should be set high to
enable interrupts (INT). The DS1780 then performs a “round robin” sampling of the inputs, sampling
each approximately once a second, in the order (corresponding to locations in the Value RAM) shown
DS1780
DS1780 MONITORING ORDER Table 3 TEMPERATURE READING
ANALOG +2.5 VS/VCCP2
ANALOG +12V
ANALOG +5V
ANALOG +3.3V
ANALOG +2.5V
ANALOG +VCCP1
FAN1
FAN2
If conversions are terminated by either of the methods described in the “OPERATION - Configuration
Register” section, the current “round-robin” loop will be completed and the results stored in RAM.
Monitoring will then terminate. When the monitoring again commences, monitoring always starts with
the temperature reading.
OPERATION - Temperature Data Format The DS1780 internally converts measured temperature data to a two’s complement data format (in °C).
The host can read the last completed temperature conversion at any time by setting the Internal Address
Register pointer to location 27h, and reading the 8 bits in the register. The format of the data is shown
below in Table 4. The MSb of the register represents the sign bit of the temperature reading. For
Fahrenheit usage, a lookup table or conversion routine must be used.
TEMPERATURE/DATA RELATIONSHIPS Table 4 S 26 25 24 23 22 21 20
MSb (unit = °C) LSb
TEMPERATURE DIGITAL OUTPUT
(BINARY) DIGITAL OUTPUT (HEX) +125°C 0111 1101 7Dh
+25°C 0001 1001 19h
+1°C 0000 0001 01h
0°C 0000 0000 00h
-1°C 1111 1111 FFh
-25°C 1110 0111 E7h
-40°C 1101 1000 D8h
OPERATION - Voltage Data Format The DS1780 contains inputs for directly monitoring the power supplies typically found in a PC (+12V, -
12V, +5V, +3.3V, +2.5V, +VCCP). These inputs are scaled internally to a reference source, and converted
via an 8-bit Delta-Sigma ADC (Analog-to-Digital Converter), thus allowing for a more accurate means of
measurement since the voltages are referenced to a known value.
Since these inputs can be greater than VDD, they are not diode protected to the power rails. In addition,
small external series resistors such as 510Ω should be put into the lines driving the DS1780 to prevent
DS1780
The worse such accident would be connecting -12V to +12V; a total of 24V difference, with the series
resistors this would draw a maximum of approximately 24 ma.
The internal scaling factor depends upon the particular input. The +12VIN, +5VIN, +3.3VIN, and +2.5VIN
inputs are internally scaled such that the nominal value of the respective supply corresponds to 3/4 of full
range, or a decimal count of 192. The approximate resolution is thus equal to:
LSb (VNOM) 256 4/3NOM
This is depicted below in Table 5.
VOLTAGE/DATA RELATIONSHIPS FOR POSITIVE ONLY VOLTAGE INPUTS
(+12VIN, +5VIN, +3.3VIN, and +2.5VIN) Table 5
INPUT PIN +12VIN +5VIN +3.3VIN +2.5VIN
LSb WEIGHTING
(mV) 62.5 26.0 17.2 13.0
ADC RESULT (BASE
10)
PIN VOLTAGE (V) PIN VOLTAGE (V) PIN VOLTAGE (V) PIN VOLTAGE (V) 0 0 0 0 0
1 0.063 0.026 0.017 0.013
2 0.125 0.052 0.034 0.026
3 0.188 0.078 0.052 0.039
4 0.25 0.104 0.069 0.052
190 11.875 4.948 3.266 2.474
191 11.938 4.974 3.283 2.487
192 12.0 5.0 3.3 2.5
193 12.063 5.026 3.317 2.513
252 15.75 6.563 4.331 3.281
253 15.813 6.589 4.348 3.294
254 15.875 6.615 4.366 3.307
255 15.938 6.641 4.383 3.32
The other two voltage inputs use a slightly different scaling technique, due to the nature of the PC voltage
they are monitoring. Because processor voltage (VCCP) can vary to 3.6V, the +VCCP1 and +2.5VS/+VCCP1
inputs are internally scaled such that the ADC result is 0h for a 0V input and the maximum value of FFh
is returned for a voltage of 3.60V. This corresponds to an LSb weighting of 14.1 mV.
The inputs can also be used to monitor a negative supply, such as -12V. However, a resistor ladder and
positive reference voltage (VREF) must be used (see Figure 1) such that input voltage to the DS1780
swings between OV and +3.6V. Assuming the DS1780 +VCCP1 and +2.5VS/+VCCP2 pins have infinite
input impedance and the VREF is a perfect supply, then the resolution and range of -12V input are:
3.61R
DS1780
VMIN (VREF, R1, R2) - VREF
VMAX (VREF, R1, R2) VREF-(VREF-3.6) 1R
If the +2.5VS/+VCCP2 is to be used to monitor a secondary processor core voltage (VCCP2), R2 should be
removed and R1=500Ω. Table 6 below shows the voltage/data relationship for these inputs in the ideal
case. In this example, VREF=+5.0V, R1=4.0 kΩ, and R2=23.2 kΩ.
Analog inputs will provide best accuracy when referred to the GNDA pin. A separate, low-impedance
ground plane for analog ground, which provides a ground point for the voltage dividers and analog
components will provide best performance but is not mandatory. Analog components such as voltage
dividers should be located physically as close as possible to the DS1780.
The power supply bypass, the parallel combination of 10 µF (electrolytic or tantalum) and 0.1 µF
(ceramic) bypass capacitors connected between pin 9 and ground, should also be located as close as
possible to the DS1780.
VOLTAGE/DATA RELATIONSHIPS FOR VCCP VOLTAGE INPUTS
(+VCCP1, +2.5VS/ +VCCP2) Table 6
INPUT PIN +VCCP1 +2.5VS/+VCCP2
LSb WEIGHTING (mV) 14.1 96.0 (Used to monitor VCCP) (Used to monitor -12V)
ADC RESULT (BASE 10) PIN VOLTAGE (V) SUPPLY VOLTAGE (V) 0 0 -29.0
1 0.014 -28.90
2 0.028 -28.81
3 0.042 -28.71
4 0.056 -28.62
136 1.920 -15.94
137 1.934 -15.85
138 1.948 -15.75
139 1.962 -15.66
252 3.558 -4.808
253 3.572 -4.712
254 3.586 -4.616
255 3.60 -4.52
OPERATION - FAN Speed Data Format Inputs are provided for signals from fans equipped with tachometer outputs. These are logic-level inputs
with an approximate threshold of 1.4V. Signal conditioning in the DS1780 accommodates the slow rise
and fall times typical of fan tachometer outputs. The maximum input signal range is 0 to VDD. In the
event these inputs are supplied from fan outputs which exceed 0 to VDD, either resistive division or diode
DS1780
maximum possible input up to VDD for best noise immunity. Alternatively, use a shunt reference or Zener
diode to clamp the input level.
Tables 7 and 8 describe the format of the data stored in the FAN reading registers (Internal Address
Registers 28h and 29h).
FAN TACHOMETER INPUT OPTIONS Figure 3
VOLTAGE/DATA RELATIONSHIPS FOR FAN INPUTS (FAN1, FAN2) UNDER
DEFAULT (÷2) MODE Table 7
RPM Timer Per Revolution Counts for “Divide by 2” (default mode) in decimal Comments 4400 13.64 ms 153 Typical RPM
3080 19.48 ms 219 70% RPM
2640 22.73 ms 255 (maximum) 60% RPM
VOLTAGE/DATA RELATIONSHIPS FOR FAN INPUTS (FAN1, FAN 2) Table 8
MODE
SELECT
NOMINAL
RPM
TIME PER
REVOLUTION
COUNTS FOR THE
NOMINAL
SPEED IN DECIMAL
70% RPM
TIME PER
REVOLUTION FOR
70% RPM Divide by 1 8800 6.82 ms 153 6160 9.74 ms
Divide by 2 4400 13.64 ms 153 3080 19.48 ms
Divide by 4 2200 27.27 ms 153 1540 38.96 ms
Divide by 8 1100 54.54 ms 153 770 77.92 ms
In general, the value stored in the FAN registers (in decimal) follows the equation:
Count (RPM, Divisor) Divisor RPM x 1.356
If fans can be powered while the power to the DS1780 is off, the DS1780 inputs will provide diode
clamping. Limit input current to the Input Current at Any Pin specification shown in the ABSOLUTE
MAXIMUM RATINGS section. In most cases, open collector outputs with pullup resistors inherently
limit this current. If this maximum current could be exceeded, either a larger pullup resistor should be
used or resistors connected in series with the fan inputs.
The Fan Inputs gate an internal 22.5 kHz oscillator for one period of the Fan signal into an 8-bit counter
(maximum count = 255). The default divisor, located in the Fan Divisor/RST_Register, is set to 2
(choices are 1, 2, 4, and 8) providing a nominal count of 153 for a 4400 rpm fan with two pulses per
DS1780
OPERATION - Interrupts An external interrupt can come from the following sources. While the label suggests a specific type or
source of interrupt, this label is not a restriction on the usage; it could come from any desired source.
1.
Analog Voltage: An interrupt will be generated if a analog voltage high or low limit has been
exceeded; this is generally when a power supply is out of its normal operating range.
2.
Temperature: An interrupt will be generated if a high or a low hot temperature limit has been exceeded.
3.
Fan speed: An interrupt will be generated if a fan count limit has been exceeded. 4.
Chassis Intrusion: This is an active high interrupt from any type of device that detects and captures chassis intrusion violations. This could be accomplished mechanically, optically, or electrically, and
circuitry external to the DS1780 is expected to latch the event.
All System Management Interrupts (SMIs) are indicated in the two Interrupt Status Registers. The INT
output has individual mask registers and individual masks for each Interrupt. As described in the
“OPERATION - Configuration Register” Section, this hardware Interrupt line can also be
enabled/disabled in the Configuration Register.
Reading an Interrupt Status Register will output the contents of the Register, and reset the Register. A
subsequent read done before the analog ‘round-robin’ monitoring loop is complete will indicate a cleared
Register. Allow at least 1 second to allow all Registers to be updated between reads. In summary, the
Interrupt Status Register clears upon being read, and requires at least 1 second to be updated. When the
Interrupt Status Register clears, the hardwire interrupt line will also clear until the Registers are updated
by the monitoring loop.
The INT hardware Interrupt output is cleared with the INT_Clear bit, which is Bit 3 of the Configuration
Register, without affecting the contents of the Interrupt Status Registers. When this bit is high, the
DS1780 monitoring loop will stop. It will resume when the bit is low.
Analog Voltage Limits The limits for the analog voltage comparison are programmed into the Value RAM at Internal Address
Registers 2Bh - 36h. A high and low limit is associated with each of the 6 analog voltage inputs of the
DS1780. Care must be taken to program the limit registers in the same format as the respective voltage
data register. Please see “OPERATION - Voltage Data Format” for details. For setting a voltage
interrupt, the DS1780 compares on a “greater than” basis for high limits and a “less than or equal to”
basis for low limits. The host can mask any or all of the voltage limits for interrupt contention.
Temperature Limits and Interrupt Modes The host programs an 8-bit high temperature limit and hysteresis/low temperature limit into the DS1780
at Internal Address Registers 39h and 3 Ah in the same two’s complement format described in the
“OPERATION - Temperature Data Format” section. The temperature mode is programmed into the
Temperature Configuration Register (0x4Bh). A digital 8-bit comparator is also incorporated that
compares the temperature readings to the programmed limits.
There are three interrupt modes of operation. The INT output can be programmed for either of the three
DS1780
1.
One-time Interrupt mode: Exceeding hot temperature limit causes an SMI that will remain active indefinitely until reset by reading Interrupt Status Register 1 or cleared by the INT_Clear bit in the
Configuration register. Once an SMI event has occurred by crossing the hot temperature limit, then
subsequently reset, an SMI will not occur again until the temperature goes below hot temperature
hysteresis (low) limit.
2.
Default Interrupt mode: Exceeding hot temperature limit causes an System Management Interrupt (SMI) that will remain active indefinitely until reset by reading Interrupt Status Register 1 or cleared
by the INT_Clear bit in the Configuration Register. Once an Interrupt event has occurred by crossing
the Hot Temperature limit, then reset, an Interrupt will occur again once the next temperature
conversion has completed. The interrupts will continue to occur in this manner until the temperature
goes below the hot temperature hysteresis value.
3.
Comparator mode: Exceeding hot temperature limit causes the SMI output to go active. SMI will remain active until the temperature goes below the hot temperature limit. Once the temperature goes
below the hot temperature limit, SMI will become inactive. As in the default and one-time interrupt
modes, the SMI can also be cleared by reading Interrupt Status Register 1 or by setting the INT_Clear
bit in the configuration register.
Figure 4 below illustrates the three temperature interrupt modes.
Fan Speed Limits The host programs 8-bit fan speed low limits for FAN1 and FAN2 inputs into Internal Address Registers
3Bh and 3Ch, respectively. Care must be taken to program the limit with respect to the divisor chosen for
each of the tachometer inputs. Refer to the “OPERATION - FAN Speed Data Format” section for details.
An interrupt will occur if measured fan speed falls below the programmed limit. Due to the nature of the
algorithm implemented, a count of 255 (max) represents a slow (or stopped) fan; i.e., tachometer counts
are inversely proportional to fan speed. Thus, the fan limit register will contain the maximum number of
counts (or the minimum fan speed) before which an interrupt will occur.
Chassis Intrusion Detection The CHS input is an active high interrupt from any type of device that detects and captures chassis
intrusion violations. This could be accomplished mechanically, optically, or electrically, and circuitry
external to the DS1780 is expected to latch the event.
The design of the DS1780 allows this input to go high even with no power applied to the DS1780, and no
clamping or other interference with the line will occur. This line can also be pulled low for at least 20 ms
by the DS1780 to reset a typical Chassis Intrusion circuit. Accomplish this reset by setting Bit 6 of
Configuration Register high. The bit in the Register is self-clearing.
A possible chassis intrusion detector/latch is shown below in Figure 5.
DS1780
TEMPERATURE INTERRUPT MODE ILLUSTRATION Figure 4
SAMPLE CHASSIS INTRUSION DETECTOR/LATCH Figure 5
