DS1747-70IND ,Y2K-Compliant, Nonvolatile Timekeeping RAMsFEATURES PIN CONFIGURATIONS Integrated NV SRAM, Real-Time Clock (RTC), Crystal, Power-Fail Cont ..
DS1747P-70 ,Y2K-Compliant, Nonvolatile Timekeeping RAMsPIN DESCRIPTION A0–A18 – Address Input CE – Chip Enable OE – Output Enable WE – Write Enable V ..
DS1747P-70 ,Y2K-Compliant, Nonvolatile Timekeeping RAMsFEATURES PIN CONFIGURATIONS Integrated NV SRAM, Real-Time Clock (RTC), Crystal, Power-Fail Cont ..
DS1747P-70 ,Y2K-Compliant, Nonvolatile Timekeeping RAMs DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
DS1747P-70+ ,Y2K-Compliant, Nonvolatile Timekeeping RAMsFEATURES PIN CONFIGURATIONS Integrated NV SRAM, Real-Time Clock (RTC), Crystal, Power-Fail Cont ..
DS1747P-70+ ,Y2K-Compliant, Nonvolatile Timekeeping RAMsFEATURES PIN CONFIGURATIONS Integrated NV SRAM, Real-Time Clock (RTC), Crystal, Power-Fail Cont ..
DV74AC244 , Octal buffer/Line Driver with 3-state Outputs
DVIULC6-2P6 ,Ultra Low capacitance 2 lines ESD protectionApplicationsBenefits■ DVI ports up to 1.65 Gb/s■ ESD standards compliance guaranteed at ■ IEEE 1394 ..
DVIULC6-4SC6 ,Ultralow capacitance ESD protectionFeatures■ 4-line ESD protection (IEC 61000-4-2)■ Protects V when applicableBUS■ Ultralow capacitanc ..
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DS1747-70IND-DS1747P-70-DS1747W-120-DS1747W-120IND-DS1747WP-120
Y2K-Compliant, Nonvolatile Timekeeping RAMs
FEATURES ��Integrated NV SRAM, Real-Time Clock
(RTC), Crystal, Power-Fail Control Circuit,
and Lithium Energy Source
��Clock Registers are Accessed Identically to
the Static RAM. These Registers are Resident in the Eight Top RAM Locations.
��Century Byte Register (Y2K Compliant)
��Totally Nonvolatile with Over 10 Years of
Operation in the Absence of Power
��BCD-Coded Century, Year, Month, Date, Day, Hours, Minutes, and Seconds with
Automatic Leap-Year Compensation Valid
Up to the Year 2100
��Battery Voltage-Level Indicator Flag
��Power-Fail Write Protection Allows for ±10% VCC Power-Supply Tolerance
��Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until
Power is Applied for the First Time
��DIP Module Only: Standard JEDEC Byte-Wide 512k x 8 Static
RAM Pinout
��PowerCap� Module Board Only:
Surface-Mountable Package for Direct Connection to PowerCap Containing
Battery and Crystal
Replaceable Battery (PowerCap)
Power-On Reset Output
Pin-for-Pin Compatible with Other Densities of DS174xP Timekeeping RAM
��Also Available in Industrial Temperature
Range: -40°C to +85°C
PIN CONFIGURATIONS
DS1747/DS1747P
Y2K-Compliant, Nonvolatile Timekeeping RAMsPowerCap is a registered trademark of Dallas Semiconductor.
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
PIN DESCRIPTION A0–A18 – Address Input
CE – Chip Enable
OE – Output Enable WE – Write Enable
VCC – Power-Supply Input
GND – Ground
DQ0–DQ7 – Data Input/Output
N.C. – No Connection RST – Power-On Reset Output (PowerCap Module board only)
X1, X2 – Crystal Connection
VBAT – Battery Connection
ORDERING INFORMATION DESCRIPTION The DS1747 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and
512k x 8 nonvolatile static RAM. User access to all registers within the DS1747 is accomplished with a
byte-wide interface as shown in Figure 1. The RTC information and control bits reside in the eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes,
and seconds data in 24-hour BCD format. Corrections for the date of each month and leap year are made
automatically. The RTC clock registers are double buffered to avoid access of incorrect data that can
occur during clock update cycles. The double-buffered system also prevents time loss as the
timekeeping countdown continues unabated by access to time register data. The DS1747 also contains its own power-fail circuitry that deselects the device when the VCC supply is in an out-of-tolerance
condition. This feature prevents loss of data from unpredictable system operation brought on by low VCC
as errant access and update cycles are avoided.
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Figure 1. Block Diagram
PACKAGES
The DS1747 is available in two packages (32-pin DIP and 34-pin PowerCap module). The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap
(DS9034PCX) that contains the crystal and battery. This design allows the Power-Cap to be mounted on top of the DS1747P after the completion of the surface mount process. Mounting the PowerCap after the
surface mount process prevents damage to the crystal and battery due to the high temperatures required
for solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board
and PowerCap are ordered separately and shipped in separate containers. The part number for the
PowerCap is DS9034PCX.
CLOCK OPERATIONS—READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal
updates to the DS1747 clock registers should be halted before clock data is read to prevent reading of
data in transition. However, halting the internal clock register updating process does not affect clock
accuracy. Updating is halted when a one is written into the read bit, bit 6 of the century register, see
Table 2. As long as a one remains in that position, updating is halted. After a halt is issued, the registers reflect the count, that is day, date, and time that was current at the moment the halt command was
issued. However, the internal clock registers of the double-buffered system continue to update so that
the clock accuracy is not affected by the access of data. All the DS1747 registers are updated
simultaneously after the internal clock register updating process has been re-enabled. Updating is within
a second after the read bit is written to zero. The READ bit must be set to a zero for a minimum of
500 �s to ensure the external registers will be updated.
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Table 1. Truth Table
SETTING THE CLOCK As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a one, like the
read bit, halts updates to the DS1747 registers. The user can then load them with the correct day, date
and time data in 24 hour BCD format. Resetting the write bit to a zero then transfers those values to the
actual clock counters and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers,
see Table 2. Setting it to a one stops the oscillator.
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to
logic “1” and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the
seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for access remain valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and
stable).
CLOCK ACCURACY (DIP MODULE)
The DS1747 is guaranteed to keep time accuracy to within �1 minute per month at 25�C. The RTC is calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not
require additional calibration. For this reason, methods of field clock calibration are not available and
not necessary. The electrical environment also affects the clock accuracy, and caution should be taken to
place the RTC in the lowest-level EMI section of the PC board layout. For additional information, please
refer to Application Note 58.
CLOCK ACCURACY (PowerCap MODULE)
The DS1747 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module typically keeps time accuracy to within �1.53 minutes per month (35 ppm) at 25°C. Clock
accuracy is also affected by the electrical environment and caution should be taken to place the RTC in
the lowest-level EMI section of the PC board layout. For additional information, please refer to
Application Note 58.
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Table 2. Register Map
OSC = Stop Bit R = Read Bit FT = Frequency Test
W = Write Bit X = See Note BF = Battery Flag
NOTE: All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1747 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE
(chip enable) is low. The device architecture allows ripple-through access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is
stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times and states are not met, valid data will be available at the latter of chip-enable access (tCEA) or at output enable
access time (tOEA). The state of the data input/output pins (DQ) is controlled by CE and OE. If the
outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If the address
inputs are changed while CE and OE remain valid, output data will remain valid for output data hold
time (tOH) but will then go indeterminate until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1747 is in the write mode whenever WE, and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE. The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or
write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active provided
that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the data bus can become active with read data defined by the address inputs. A low transition on WE
will then disable the output tWEZ after WE goes active.
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
DATA-RETENTION MODE
The 5V device is fully accessible and data can be written or read only when VCC is greater than VPF.
However, when VCC is below the power failing point, VPF, (point at which write protection occurs) the internal clock registers and SRAM are blocked from any access. At this time the power fail reset output
signal (RST) is driven active and will remain active until VCC returns to nominal levels. When VCC falls
below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to
the backup battery. RTC operation and SRAM data are maintained from the battery until VCC is returned
to nominal levels. The 3.3V device is fully accessible and data can be written or read only when VCC is greater than VPF. When VCC falls below the power fail point, VPF, access to the device is inhibited. At
this time the power fail reset output signal (RST) is driven active and will remain active until VCC returns
to nominal levels. If VPF is less than VSO, the device power is switched from VCC to the backup supply
(VBAT) when VCC drops below VPF. If VPF is greater than Vso, the device power is switched from VCC to
the backup supply (VBAT) when VCC drops below VSO. RTC operation and SRAM data are maintained
from the battery until VCC is returned to nominal levels. The RST signal is an open drain output and requires a pull up. Except for the RST, all control, data, and address signals must be powered down
when VCC is powered down.
BATTERY LONGEVITY
The DS1747 has a lithium power source that is designed to provide energy for clock activity, and clock
and RAM data retention when the VCC supply is not present. The capability of this internal power supply is sufficient to power the DS1747 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at +25�C with the internal clock oscillator running
in the absence of VCC power. Each DS1747 is shipped from Dallas Semiconductor with its lithium
energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VPF, the lithium energy source is enabled for battery backup operation. Actual life
expectancy of the DS1747 will be much longer than 10 years since no lithium battery energy is
consumed when VCC is present.
BATTERY MONITOR
The DS1747 constantly monitors the battery voltage of the internal battery. The Battery Flag bit (bit 7)
of the day register is used to indicate the voltage level range of the battery. This bit is not writable and should always be a one when read. If a zero is ever present, an exhausted lithium energy source is
indicated and both the contents of the RTC and RAM are questionable.
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground……………………………………………………………..-0.3V to +6.0V
Storage Temperature Range………………………………………………………………………………...-40°C to +85°C Soldering Temperature………………………….See IPC/JEDEC Standard J-STD-020A for Surface-Mount Devices.
See Note 7 for Through-Hole Mounted Devices.
This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the
operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
OPERATING RANGE
RECOMMENDED DC OPERATING CONDITIONS
(TA = Over the Operating Range) DC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V � 10%, TA = Over the Operating Range.)
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V �10%, TA = Over the Operating Range.)
AC CHARACTERISTICS—READ CYCLE (5V)
(VCC = 5.0V �10%, TA = Over the Operating Range.)
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
AC CHARACTERISTICS—READ CYCLE (3.3V)
(VCC = 3.3V �10%, TA = Over the Operating Range.)
READ CYCLE TIMING DIAGRAM
