DS1746P-70 ,Y2K-Compliant, Nonvolatile Timekeeping RAMsPIN DESCRIPTIONA0–A16 – Address InputCE – Chip EnableOE – Output EnableWE – Write EnableV – Po ..
DS1746P-70 ,Y2K-Compliant, Nonvolatile Timekeeping RAMsPIN DESCRIPTIONA0–A16 – Address InputCE – Chip EnableOE – Output EnableWE – Write EnableV – Po ..
DS1746P-70+ ,Y2K-Compliant, Nonvolatile Timekeeping RAMsFEATURES PIN CONFIGURATIONS Integrated NV SRAM, Real-Time Clock, TOP VIEW Crystal, Power-Fail C ..
DS1746W/120 ,Y2K-Compliant, Nonvolatile Timekeeping RAMsFEATURES PIN ASSIGNMENT Integrated NV SRAM, real time clock,NC1 32 VCCcrystal, power-fail control ..
DS1746W/120+ ,Y2K-Compliant, Nonvolatile Timekeeping RAMs DS1746/DS1746P Y2K-Compliant, N onvolatile Timekeeping RAMs
DS1746W+120 ,Y2K-Compliant, Nonvolatile Timekeeping RAMs DS1746/DS1746P Y2KC Nonvolatile Timekeeping RAMwww.dalsemi.com
DV74AC244 , Octal buffer/Line Driver with 3-state Outputs
DVIULC6-2P6 ,Ultra Low capacitance 2 lines ESD protectionApplicationsBenefits■ DVI ports up to 1.65 Gb/s■ ESD standards compliance guaranteed at ■ IEEE 1394 ..
DVIULC6-4SC6 ,Ultralow capacitance ESD protectionFeatures■ 4-line ESD protection (IEC 61000-4-2)■ Protects V when applicableBUS■ Ultralow capacitanc ..
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DS1746-70IND-DS1746P-70-DS1746W/120-DS1746W+120-DS1746W-120-DS1746W-120IND-DS1746WP-120
Y2K-Compliant, Nonvolatile Timekeeping RAMs
FEATURESIntegrated NV SRAM, real time clock,
crystal, power-fail control circuit and lithium
energy sourceClock registers are accessed identical to thestatic RAM. These registers are resident in the
eight top RAM locations.Century byte register; ie., Y2K compliantTotally nonvolatile with over 10 years of
operation in the absence of powerBCD coded century, year, month, date, day,
hours, minutes, and seconds with automatic
leap year compensation valid up to the year
2100Battery voltage level indicator flagPower-fail write protection allows for ±10%
VCC power supply toleranceLithium energy source is electrically
disconnected to retain freshness until power is
applied for the first timeDIP Module onlyStandard JEDEC bytewide 128k x 8 static
RAM pinoutPowerCap Module Board only-Surface mountable package for direct
connection to PowerCap containing
battery and crystalReplaceable battery (PowerCap)Power-On Reset Output-Pin for pin compatible with other densities
of DS174XP Timekeeping RAM
PIN ASSIGNMENT
DS1746/DS1746P
Y2KC Nonvolatile Timekeeping RAMNCA15A16RSTVCC
WEOECEDQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ0GNDNC
34-Pin PowerCap Module Board
(Uses DS9034PCX PowerCap)
32-Pin Encapsulated Package
A14
DQ1
DQ0
VCC
DQ7
DQ5
DQ6
A16
A12
DQ2
GND
DQ4
DQ3
DS1746/DS1746P
PIN DESCRIPTIONA0–A16 – Address Input– Chip Enable– Output Enable– Write Enable
VCC – Power Supply Input
GND– Ground
DQ0–DQ7 – Data Input/Output
NC – No Connection
RST – Power–on Reset Output (Power– Cap Module board only)
X1, X2 – Crystal Connection
VBAT – Battery Connection
ORDERING INFORMATIONDS1746P (5V)blank 32-pin DIP Module 34-pin PowerCap Module board*
DS1746WP(3.3V)
blank 32-pin DIP Module
P 34-pin PowerCap Module board*
*DS9034PCX (PowerCap) Required:
(must be ordered separately)
DESCRIPTIONThe DS1746 is a full function, year 2000 compliant (Y2KC), real-time clock/calendar (RTC) and 128k x8 non-volatile static RAM. User access to all registers within the DS1746 is accomplished with a
bytewide interface as shown in Figure 1. The Real Time Clock (RTC) information and control bits reside
in the eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours,
minutes, and seconds data in 24-hour BCD format. Corrections for the date of each month and leap year
are made automatically. The RTC clock registers are double buffered to avoid access of incorrect datathat can occur during clock update cycles. The double buffered system also prevents time loss as the
timekeeping countdown continues unabated by access to time register data. The DS1746 also contains its
own power-fail circuitry which deselects the device when the VCC supply is in an out of tolerance
condition. This feature prevents loss of data from unpredictable system operation brought on by low VCC
as errant access and update cycles are avoided.
DS1746/DS1746P
DS1746 BLOCK DIAGRAM Figure 1
PACKAGESThe DS1746 is available in two packages (32-pin DIP and 34-pin PowerCap module). The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1746P after the completion of the surface mount process. Mounting the PowerCap after the surfacemount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
CLOCK OPERATIONS-READING THE CLOCKWhile the double buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1746 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a one is written into the read bit, bit 6 of the century register, see Table 2. As
long as a one remains in that position, updating is halted. After a halt is issued, the registers reflect thecount, that is day, date, and time that was current at the moment the halt command was issued. However,
the internal clock registers of the double buffered system continue to update so that the clock accuracy is
not affected by the access of data. All of the DS1746 registers are updated simultaneously after the
internal clock register updating process has been re-enabled. Updating is within a second after the read bit
is written to zero. The READ bit must be a zero for a minimum of 500 μs to ensure the external registerswill be updated.
DS1746/DS1746P
DS1746 TRUTH TABLE Table 1
SETTING THE CLOCKAs shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a one, like the
read bit, halts updates to the DS1746 registers. The user can then load them with the correct day, date and
time data in 24 hour BCD format. Resetting the write bit to a zero then transfers those values to the actual
clock counters and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATORThe clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers, see
Table 2. Setting it to a one stops the oscillator.
FREQUENCY TEST BITAs shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to
logic “1” and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the
seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for
access remain valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and
stable).
CLOCK ACCURACY (DIP MODULE)The DS1746 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require
additional calibration. For this reason, methods of field clock calibration are not available and notnecessary. Clock accuracy is also effected by the electrical environment and caution should be taken to
place the RTC in the lowest level EMI section of the PCB layout. For additional information please see
application note 58.
CLOCK ACCURACY (POWERCAP MODULE)The DS1746 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within ±1.53 minutes per month (35 ppm) at 25°C. Clock
accuracy is also effected by the electrical environment and caution should be taken to place the RTC in
the lowest level EMI section of the PCB layout. For additional information please see application note
58.
DS1746/DS1746P
DS1746 REGISTER MAP Table 2OSC = STOP BIT R = READ BIT FT = FREQUENCY TEST
W = WRITE BIT X = SEE NOTE BELOW BF = BATTERY FLAG
NOTE:All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCKThe DS1746 is in the read mode wheneverOE (output enable) is low,WE (write enable) is high, and CE(chip enable) is low. The device architecture allows ripple-through access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is
stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times
and states are not met, valid data will be available at the latter of chip enable access (tCEA) or at output
enable access time (tOEA). The state of the data input/output pins (DQ) is controlled by CE and OE. If the
outputs are activated before tAA , the data lines are driven to an intermediate state until tAA . If the address
inputs are changed while CE and OE remain valid, output data will remain valid for output data hold
time (tOH) but will then go indeterminate until the next address access.
WRITING DATA TO RAM OR CLOCKThe DS1746 is in the write mode whenever WE, and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE, or CE. The addresses must be held valid throughout
the cycle. CE or WEmust return inactive for a minimum of tWR prior to the initiation of another read orwrite cycle. Data in must be valid tDS prior to the end of write and remain valid for tDS afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active
provided that care is taken with the data bus to avoid bus contention. If OE is low prior totransitioning low the data bus can become active with read data defined by the address inputs. A low
transition on WEwill then disable the output tWEZ after WEgoes active.
DS1746/DS1746P
DATA RETENTION MODEThe 5-volt device is fully accessible and data can be written or read only when VCC is greater than VPF.
However, when VCC is below the power fail point, VPF , (point at which write protection occurs) the
internal clock registers and SRAM are blocked from any access. At this time the power fail reset output
signal )RST( is driven active and will remain active until VCC returns to nominal levels. When VCC falls
below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to
the backup battery. RTC operation and SRAM data are maintained from the battery until VCC is returnedto nominal levels. The 3.3 volt device is fully accessible and data can be written or read only when VCC is
greater than VPF . When VCC falls below the power fail point, VPF , access to the device is inhibited. At this
time the power fail reset output signal (RST) is driven active and will remain active until VCC returns to
nominal levels. If VPF is less than VSO, the device power is switched from VCC to the backup supply
(VBAT) when VCC drops below VPF. If VPF is greater than VSO, the device power is switched from VCC to
the backup supply (VBAT) when VCC drops below VSO. RTC operation and SRAM data are maintained
from the battery until VCC is returned to nominal levels. The RST signal is an open drain output and
requires a pull up. Except for the RST, all control, data, and address signals must be powered downwhen VCC is powered down.
BATTERY LONGEVITYThe DS1746 has a lithium power source that is designed to provide energy for clock activity, and clock
and RAM data retention when the VCC supply is not present. The capability of this internal power supply
is sufficient to power the DS1746 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at 25°C with the internal clock oscillator running in
the absence of VCC power. Each DS1746 is shipped from Dallas Semiconductor with its lithium energy
source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than
VPF , the lithium energy source is enabled for battery backup operation. Actual life expectancy of the
DS1746 will be much longer than 10 years since no lithium battery energy is consumed when VCC ispresent.
BATTERY MONITORThe DS1746 constantly monitors the battery voltage of the internal battery. The Battery Flag bit (bit 7) of
the day register is used to indicate the voltage level range of the battery. This bit is not writable and
should always be a one when read. If a zero is ever present, an exhausted lithium energy source isindicated and both the contents of the RTC and RAM are questionable.
DS1746/DS1746P
ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground –0.3V to +6.0V
Storage Temperature –40°C to +85°C
Soldering Temperature 260°C for 10 seconds (DIP Package) (See Note 7)
See IPC/JEDEC Standard J-STD-020A forSurface Mount Devices
* This is a stress rating only and functional operation of the device at these or any other condition above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
OPERATING RANGE
RECOMMENDED DC OPERATING CONDITIONS (Over the Operating Range)
DC ELECTRICAL CHARACTERISTICS(Over the Operating Range; VCC = 5.0V ± 10%)
DS1746/DS1746P
DC ELECTRICAL CHARACTERISTICS (Over the Operating Range; VCC = 3.3V ± 10%)
READ CYCLE, AC CHARACTERISTICS(Over the Operating Range; VCC = 5.0V ± 10%)
DS1746/DS1746P
READ CYCLE, AC CHARACTERISTICS(Over the Operating Range; VCC = 3.3V ± 10%)
READ CYCLE TIMING DIAGRAM
