DS1743P-100 ,Y2KC nonvolatile timekeeping RAM, 100nsFEATURES PIN ASSIGNMENT Integrated NV SRAM, real time clock, crystal, power-fail control circuit a ..
DS1743P-100 ,Y2KC nonvolatile timekeeping RAM, 100nsPIN DESCRIPTION-70 70 ns accessA0-A12 - Address Input-100 100 ns accessCE - Chip Enableblank 28-pin ..
DS1743P-100 ,Y2KC nonvolatile timekeeping RAM, 100nsPIN DESCRIPTION-70 70 ns accessA0-A12 - Address Input-100 100 ns accessCE - Chip Enableblank 28-pin ..
DS1743P-100+ ,Y2K-Compliant, Nonvolatile Timekeeping RAMsPIN DESCRIPTION PIN PIN NAME FUNCTION NAME FUNCTION PDIP PowerCap PDIP PowerCap 1, 2, 3, Chip Enabl ..
DS1743W-120 ,Y2K-Compliant, Nonvolatile Timekeeping RAMsPIN DESCRIPTION PIN PIN NAME FUNCTION NAME FUNCTION PDIP PowerCap PDIP PowerCap 1, 2, 3, Chip Enabl ..
DS1743W-120+ ,Y2K-Compliant, Nonvolatile Timekeeping RAMsPIN DESCRIPTION PIN PIN NAME FUNCTION NAME FUNCTION PDIP PowerCap PDIP PowerCap 1, 2, 3, Chip Enabl ..
DV74AC244 , Octal buffer/Line Driver with 3-state Outputs
DVIULC6-2P6 ,Ultra Low capacitance 2 lines ESD protectionApplicationsBenefits■ DVI ports up to 1.65 Gb/s■ ESD standards compliance guaranteed at ■ IEEE 1394 ..
DVIULC6-4SC6 ,Ultralow capacitance ESD protectionFeatures■ 4-line ESD protection (IEC 61000-4-2)■ Protects V when applicableBUS■ Ultralow capacitanc ..
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DS1743P+100-DS1743P-100-DS1743WP-120-DS1743WP-150
Y2KC Nonvolatile Timekeeping RAM
FEATURESIntegrated NV SRAM, real time clock, crystal, power-fail control circuit and lithium energy sourceClock registers are accessed identical to the static
RAM. These registers are resident in the eight topRAM locations.Century byte registerTotally nonvolatile with over 10 years of operation inthe absence of powerBCD coded century, year, month, date, day, hours,minutes, and seconds with automatic leap year
compensation valid up to the year 2100� Battery voltage level indicator flagPower-fail write protection allows for ±10% VCCpower supply toleranceLithium energy source is electrically disconnected toretain freshness until power is applied for the first timeDIP Module onlyStandard JEDEC bytewide 8k x 8 static RAMpinoutPowerCap Module Board onlySurface mountable package for direct connectionto PowerCap containing battery and crystal– Replaceable battery (PowerCap)Power-On Reset Output– Pin for pin compatible with other densities of
DS174XP Timekeeping RAM
ORDERING INFORMATIONDS1743P-XXX(5V)
-70 70 ns access-100 100 ns access
blank 28-pin DIP Module34-pin PowerCap Moduleboard*
*DS1743WP-XXX(3.3V)-120 120 ns access
-150150 ns access
blank 28-pin DIP Module34-pin PowerCap Moduleboard**DS9034PCX (PowerCap) Required:
PIN ASSIGNMENT
PIN DESCRIPTIONA0-A12 - Address Input- Chip Enable
CE2- Chip Enable 2 (DIP
Module only) - Output Enable - Write Enable
VCC- Power Supply Input
GND - GroundDQ0-DQ7- Data Input/Output
NC - No Connection
RST - Power-On Reset Output
(PowerCap Module board only)
DS1743/DS1743P
Y2KC Nonvolatile Timekeeping RAMVCC
CE2
DQ7
DQ6
DQ5
DQ4
DQ3
A12
DQ0
DQ1
DQ2
GND
28-Pin Encapsulated PackageNCNCNCRSTVCC WEOECEDQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ0GNDNCNC
34-Pin Powercap Module Board(Uses DS9034PCX Powercap)
DS1743/DS1743P
DESCRIPTIONThe DS1743 is a full function, year 2000-compliant (Y2KC), real-time clock/calendar (RTC) and 8k x 8
non-volatile static RAM. User access to all registers within the DS1743 is accomplished with a bytewide
interface as shown in Figure 1. The Real Time Clock (RTC) information and control bits reside in the
eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours,
minutes, and seconds data in 24-hour BCD format. Corrections for the day of the month and leap year aremade automatically. The RTC clock registers are double buffered to avoid access of incorrect data that
can occur during clock update cycles. The double buffered system also prevents time loss as the
timekeeping countdown continues unabated by access to time register data. The DS1743 also contains its
own power-fail circuitry, which deselects the device when the VCC supply is in an out of tolerance
condition. This feature prevents loss of data from unpredictable system operation brought on by low VCCas errant access and update cycles are avoided.
PACKAGESThe DS1743 is available in two packages (28-pin DIP and 34-pin PowerCap module). The 28-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1743P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap isDS9034PCX.
CLOCK OPERATIONS-READING THE CLOCKWhile the double buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1743 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, bit 6 of the century register, see Table 2. As longas a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count, that
is day, date, and time that was current at the moment the halt command was issued. However, the internal
clock registers of the double-buffered system continue to update so that the clock accuracy is not affected
by the access of data. All of the DS1743 registers are updated simultaneously after the internal clockregister updating process has been re-enabled. Updating is within a second after the read bit is written to
The READ bit must be a zero for a minimum of 500 μs to ensure the external registers will be updated.
DS1743/DS1743P
DS1743 BLOCK DIAGRAM Figure 1
DS1743 TRUTH TABLE Table 1
SETTING THE CLOCKAs shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a 1, like the read
bit, halts updates to the DS1743 registers. The user can then load them with the correct day, date and time
data in 24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock
counters and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATORThe clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers, see
Table 2. Setting it to a 1 stops the oscillator.
FREQUENCY TEST BITAs shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to
logic 1 and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When theseconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for
access remain valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and
stable).
DS1743/DS1743P
CLOCK ACCURACY (DIP MODULE)The DS1743 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require
additional For this reason, methods of field clock calibration are not available and not necessary. Clock
accuracy is also effected by the electrical environment and caution should be taken to place the RTC in thelowest level EMI section of the PCB layout. For additional information please see application note 58.
CLOCK ACCURACY (POWERCAP MODULE)The DS1743 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within ±1.53 minutes per month (35 ppm) at 25°C. Clock
accuracy is also effected by the electrical environment and caution should be taken to place the RTC in the
lowest level EMI section of the PCB layout. For additional information please see application note 58.
DS1743 REGISTER MAP Table 2FUNCTION/RANGE10 YearXFTXX
OSC = STOP BITR = READ BITFT = FREQUENCY TEST
W = WRITE BITX = SEE NOTE BELOWBF = BATTERY FLAG
NOTE:All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCKThe DS1743 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE(chip enable) is low. The device architecture allows ripple-through access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is
stable, providing that the CE, and OE access times and states are satisfied. If CE, or OE access times and
states are not met, valid data will be available at the latter of chip enable access (tCEA) or at output enable
access time (tCEA). The state of the data input/output pins (DQ) is controlled by CE, and OE. If the
outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If the address
inputs are changed while CE, and OE remain valid, output data will remain valid for output data hold time
(tOH) but will then go indeterminate until the next address access.
DS1743/DS1743P
WRITING DATA TO RAM OR CLOCKThe DS1743 is in the write mode whenever WE, and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE, on CE. The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read orwrite cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active provided
that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the
data bus can become active with read data defined by the address inputs. A low transition on WE will
then disable the outputs tWEZ after WE goes active.
DATA RETENTION MODEThe 5-volt device is fully accessible and data can be written or read only when VCC is greater than VPF.
However, when VCC is below the power fail point, VPF, (point at which write protection occurs) the internal
clock registers and SRAM are blocked from any access. At this time(PowerCap only)the power fail reset
output signal (RST) is driven active and will remain active until VCC returns to nominal levels. When VCCfalls below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to
the backup battery. RTC operation and SRAM data are maintained from the battery until VCC is returned to
nominal levels. The 3.3-volt device is fully accessible and data can be written or read only when VCC is
greater than VPF. When VCC falls below the power fail point, VPF, access to the device is inhibited. At this
time the power fail reset output signal (RST) is driven active and will remain active until VCC returns to
nominal levels. If VPF is less than Vso, the device power is switched from VCC to the backup supply (VBAT)
when VCC drops below VPF. If VPF is greater than Vso, the device power is switched from VCC to the backupsupply (VBAT) when VCC drops below Vso. RTC operation and SRAM data are maintained from the battery
until VCC is returned to nominal levels. The RST(PowerCap only) signal is an open drain output and
requires a pull up. Except for the RST, all control, data, and address signals must be powered down when
VCC is powered down.
BATTERY LONGEVITYThe DS1743 has a lithium power source that is designed to provide energy for clock activity and clock and
RAM data retention when the VCC supply is not present. The capability of this internal power supply issufficient to power the DS1743 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at 25°C with the internal clock oscillator running in
the absence of VCC power. Each DS1743 is shipped from Dallas Semiconductor with its lithium energy
source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater thanVPF, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the
DS1743 will be much longer than 10 years since no lithium battery energy is consumed when VCC is
present.
BATTERY MONITORThe DS1743 constantly monitors the battery voltage of the internal battery. The Battery Flag bit (bit 7) of
the day register is used to indicate the voltage level range of the battery. This bit is not writable and shouldalways be a 1 when read. If a 0 is ever present, an exhausted lithium energy source is indicated and both
the contents of the RTC and RAM are questionable.
DS1743/DS1743P
ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground -0.3V to +6.0V
Operating Temperature 0°C to 70°C
Storage Temperature -40°C to +85°C
Soldering Temperature See J-STD-020A Specification (See Note 8)
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
OPERATING RANGE
RECOMMENDED DC OPERATING CONDITIONS
(Over the Operating Range)
DC ELECTRICAL CHARACTERISTICS
(Over the Operating Range; VCC = 5.0V ± 10%)
DS1743/DS1743P
DC ELECTRICAL CHARACTERISTICS(Over the Operating Range; VCC = 3.3V ± 10%)
READ CYCLE, AC CHARACTERISTICS(Over the Operating Range; VCC = 5.0V ± 10%)
DS1743/DS1743P
READ CYCLE, AC CHARACTERISTICS
(Over the Operating Range; VCC = 3.3V ± 10%)
READ CYCLE TIMING DIAGRAMSEE NOTES
DS1743/DS1743P
WRITE CYCLE, AC CHARACTERISTICS(Over the Operating Range; VCC = 5.0V ± 10%)
WRITE CYCLE, AC CHARACTERISTICS(Over the Operating Range; VCC = 3.3V ± 10%)
