DS1743P-100+ ,Y2K-Compliant, Nonvolatile Timekeeping RAMsPIN DESCRIPTION PIN PIN NAME FUNCTION NAME FUNCTION PDIP PowerCap PDIP PowerCap 1, 2, 3, Chip Enabl ..
DS1743W-120 ,Y2K-Compliant, Nonvolatile Timekeeping RAMsPIN DESCRIPTION PIN PIN NAME FUNCTION NAME FUNCTION PDIP PowerCap PDIP PowerCap 1, 2, 3, Chip Enabl ..
DS1743W-120+ ,Y2K-Compliant, Nonvolatile Timekeeping RAMsPIN DESCRIPTION PIN PIN NAME FUNCTION NAME FUNCTION PDIP PowerCap PDIP PowerCap 1, 2, 3, Chip Enabl ..
DS1743W-120IND+ ,Y2K-Compliant, Nonvolatile Timekeeping RAMsFEATURES PIN CONFIGURATIONS Integrated NV SRAM, Real-Time Clock, Crystal, Power-Fail Control Ci ..
DS1743WP-120 ,Y2KC Nonvolatile Timekeeping RAMPIN DESCRIPTION-70 70 ns accessA0-A12 - Address Input-100 100 ns accessCE - Chip Enableblank 28-pin ..
DS1743WP-120 ,Y2KC Nonvolatile Timekeeping RAMDS1743/DS1743PY2KC Nonvolatile Timekeeping RAMwww.dalsemi.com
DV74AC244 , Octal buffer/Line Driver with 3-state Outputs
DVIULC6-2P6 ,Ultra Low capacitance 2 lines ESD protectionApplicationsBenefits■ DVI ports up to 1.65 Gb/s■ ESD standards compliance guaranteed at ■ IEEE 1394 ..
DVIULC6-4SC6 ,Ultralow capacitance ESD protectionFeatures■ 4-line ESD protection (IEC 61000-4-2)■ Protects V when applicableBUS■ Ultralow capacitanc ..
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DS1743/100-DS1743/100IND+-DS1743-100-DS1743-100+-DS1743-100IND+-DS1743P-100+-DS1743W-120-DS1743W-120+-DS1743W-120IND+-DS1743WP-120+-DS1743WP-150+
Y2K-Compliant, Nonvolatile Timekeeping RAMs
FEATURES Integrated NV SRAM, Real-Time Clock, Crystal, Power-Fail Control Circuit, and Lithium Energy Source Clock Registers are Accessed Identically to the Static RAM. These Registers Reside in the Eight Top RAM Locations. Century Byte Register Totally Nonvolatile with Over 10 Years of Operation in the Absence of Power BCD-Coded Century, Year, Month, Date, Day, Hours, Minutes, and Seconds with Automatic Leap Year Compensation Valid through 2099 Low-Battery-Voltage Level Indicator Flag Power-Fail Write Protection Allows for ±10% VCC Power-Supply Tolerance Lithium Energy Source is Electrically Disconnected to Retain Freshness Until Power is Applied for the First Time DIP Module Only Standard JEDEC Bytewide 8k x 8 Static RAM Pinout PowerCap Module Board Only Surface-Mountable Package for Direct Connection to PowerCap Containing Battery and Crystal Replaceable Battery (PowerCap) Power-On Reset Output Pin-for-Pin Compatible with Other Densities of DS174XP Timekeeping RAM Underwriters Laboratories (UL) Recognized to Prevent Charging of the Internal Lithium Battery
PIN CONFIGURATIONS VCC
WE CE2 A8 A9 A11
OE A10
CE DQ7 DQ6 DQ5 DQ4 DQ3 2 3 4 5 6 7 8 9 10 11 12 13 14
N.C. A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND
28 27 26 25 24 23 22 21 20 19 18 17 16 15
28-Pin Encapsulated Package (28 PIN 740)
DS1743 N.C. 2 3 N.C. N.C.
RST VCC
WE OE
CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND 5 6 7 8 9 10 11 12 13 14 15 16 17
N.C. N.C. 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18
N.C. A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
34 N.C.
X1 GND VBAT X2
34-Pin PowerCap Module Board (Uses DS9034PCX+ or DS9034I-PCX+ PowerCap)
DS1743P TOP VIEW
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
PIN DESCRIPTION
PIN NAME FUNCTION PDIP PowerCap 1, 2, 3, 31–34 N.C. No Connection 30 A12
Address Input 25 A7 24 A6 23 A5 22 A4 21 A3 20 A2 19 A1
10 18 A0
11 16 DQ0 Data Input/ Output 12 15 DQ1
13 14 DQ2
14 17 GND Ground
15 13 DQ3
Data Input/ Output
16 12 DQ4
17 11 DQ5
18 10 DQ6
19 9 DQ7
PIN NAME FUNCTION PDIP PowerCap 20 8 CE Chip Enable, Active Low 21 28 A10 Address Input
22 7 OE Output Enable, Active Low 23 29 A11
Address Input 24 27 A9
25 26 A8
26 — CE2 Chip Enable 2
27 6 WE Write Enable, Active Low
28 5 VCC Power-Supply Input 4 RST Power-On Reset Output, Active Low X1, X2 Crystal Connection VBAT Battery Connection
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE VOLTAGE (V) TOP MARK**
DS1743-85+ 0°C to +70°C 28 EDIP Module 5 DS1743-85 DS1743-100+ 0°C to +70°C 28 EDIP Module 5 DS1743-100 DS1743-100 IND+ -40°C to +85°C 28 EDIP Module 5 DS1743-100-IND DS1743P-85+ 0°C to +70°C 34 PowerCap* 5 DS1743P-85 DS1743P-100+ 0°C to +70°C 34 PowerCap* 5 DS1743P-100 DS1743P-100IND+ -40°C to +85°C 34 PowerCap* 5 DS1743P-100 IND DS1743W-120+ 0°C to +70°C 28 EDIP Module 3.3 DS1743W-120 DS1743W-120 IND+ -40°C to +85°C 28 EDIP Module 3.3 DS1743W-120 IND DS1743W-150+ 0°C to +70°C 28 EDIP Module 3.3 DS1743W-150 DS1743W-150 IND+ -40°C to +85°C 28 EDIP Module 3.3 DS1743W-150 IND DS1743WP-120+ 0°C to +70°C 34 PowerCap* 3.3 DS1743WP-120 DS1743WP-120 IND+ -40°C to +85°C 34 PowerCap* 3.3 DS1743WP-120 IND
DS9034PCX+ 0°C to +70°C PowerCap — DS9034PC DS9034I-PCX+ -40°C to +85°C PowerCap IND — DS9034PCI
+Denotes a lead(Pb)-free/RoHS-compliant package. *DS9034PCX+ or DS9034I-PCX+ required (must be ordered separately). **A ‘+’ indicates lead(Pb)-free. The top mark will include a ‘+’ symbol on lead(Pb)-free devices.
DESCRIPTION The DS1743 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and 8k x 8 nonvolatile static RAM. User access to all registers within the DS1743 is accomplished with a bytewide interface as shown in Figure 1. The RTC information and control bits reside in the eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour binary-coded decimal (BCD) format. Corrections for the day of the month and leap year are made automatically. The RTC clock registers are double buffered to avoid access of incorrect data that can occur during clock update cycles. The double-buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The DS1743 also contains its own power-fail circuitry, which deselects the device when the VCC supply is in an out-of-tolerance condition. When VCC is above VPF, the device is fully accessible. When VCC is below VPF, the internal CE signal is forced high, preventing any access. When VCC rises above VPF, access remains inhibited for TREC, allowing time for the system to stabilize. These features prevent loss of data from unpredictable system operation brought on by low VCC as errant access and update cycles are avoided.
PACKAGES The DS1743 is available in two packages: the 28-pin DIP and the 34-pin PowerCap module. The 28-pin DIP-style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX) that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the DS1743P after the completion of the surface-mount process. Mounting the PowerCap after the surface-mount process prevents damage to the crystal and battery due to the high temperatures required for solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap are ordered separately and shipped in separate containers.
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
TIME AND DATE OPERATION The time and date information is obtained by reading the appropriate register bytes. Table 2 shows the RTC registers. The time and date are set or initialized by writing the appropriate register bytes. The contents of the time and date registers are in the BCD format. The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined, but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday and so on). Illogical time and date entries result in undefined operation.
CLOCK OPERATIONS-READING THE CLOCK While the double-buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1743 clock registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock register updating process does not affect clock accuracy. Updating is halted when a 1 is written into the read bit, bit 6 of the century register (see Table 2). As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count that is day, date, and time that was current at the moment the halt command was issued. However, the internal clock registers of the double-buffered system continue to update so that the clock accuracy is not affected by the access of data. All the DS1743 registers are updated simultaneously after the internal clock register updating process has been re-enabled. Updating is within a second after the read bit is written to 0. The READ bit must be a zero for a minimum of 500µs to ensure the external registers are updated.
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Figure 1. Block Diagram Table 1. Truth Table
VCC CE
CE2 OE WE
MODE DQ POWER VCC > VPF
VIH X X X Deselect High-Z Standby X VIL X X Deselect High-Z Standby VIL VIH X VIL Write Data In Active VIL VIH VIL VIH Read Data Out Active VIL VIH VIH VIH Read High-Z Active VSO < VCC < VPF X X X X Deselect High-Z CMOS Standby
VCC
SETTING THE CLOCK As shown in Table 2, bit 7 of the Control register is the W (write) bit. Setting the W bit to 1 halts updates to the DS1743 registers. The user can subsequently load correct date and time values into all eight registers, followed by a write cycle of 00h to the Control register to clear the W bit and transfer those new settings into the clock, allowing timekeeping operations to resume from the new set-point. Again referring to Table 2, bit 6 of the Control register is the R (read) bit. Setting the R bit to 1 halts updates to the DS1743 registers. The user can subsequently read the date and time values from the eight registers without those contents possibly changing during those I/O operations. A subsequent write cycle of 00h to the Control register to clear the R bit allows timekeeping operations to resume from the previous set-point. The pre-existing contents of the Control register bits 0:5 (Century value) are ignored/unmodified by a write cycle to Control if either the W or R bits are being set to 1 in that write operation. The pre-existing contents of the Control register bits 0:5 (Century value) will be modified by a write cycle to Control if the W bit is being cleared to 0 in that write operation.
Dallas Semiconductor DS1743
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
The pre-existing contents of the Control register bits 0:5 (Century value) will not be modified by a write cycle to Control if the R bit is being cleared to 0 in that write operation. STOPPING AND STARTING THE CLOCK OSCILLATOR The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers, see Table 2. Setting it to a 1 stops the oscillator. FREQUENCY TEST BIT As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the oscillator is running, the LSB of the seconds register will toggle at 512Hz. When the seconds register is being read, the DQ0 line will toggle at the 512Hz frequency as long as conditions for access remain valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and stable). CLOCK ACCURACY (DIP MODULE) The DS1743 is guaranteed to keep time accuracy to within ±1 minute per month at +25°C. The RTC is calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require additional calibration. For this reason, methods of field clock calibration are not available and not necessary. The electrical environment also affects clock accuracy, so caution should be taken to place the RTC in the lowest-level EMI section of the PC board layout. For additional information, please refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks. CLOCK ACCURACY (PowerCap MODULE) The DS1743 and DS9034PCX are each individually tested for accuracy. Once mounted together, the module will typically keep time accuracy to within ±1.53 minutes per month (35ppm) at +25°C. The electrical environment also affects clock accuracy, so caution should be taken to place the RTC in the lowest-level EMI section of the PC board layout. For additional information, please refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks.
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Table 2. Register Map
ADDRESS DATA FUNCTION RANGE B7 B6 B5 B4 B3 B2 B1 B0
1FFF 10 Year Year Year 00–99
1FFE X X X 10 Month Month Month 01–12
1FFD X X 10 Date Date Date 01–31
1FFC BF FT X X X Day Day 01–07
1FFB X X 10 Hour Hour Hour 00–23
1FFA X 10 Minutes Minutes Minutes 00–59
1FF9 OSC 10 Seconds Seconds Seconds 00–59
1FF8 W R 10 Century Century Control 00–39
OSC = STOP BIT R = READ BIT FT = FREQUENCY TEST
W = WRITE BIT X = SEE NOTE BELOW BF = BATTERY FLAG Note: All indicated “X” bits must be set to “0” when written to ensure proper clock operation. RETRIEVING DATA FROM RAM OR CLOCK The DS1743 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE (chip enable) is low. The device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is stable, providing that the, CE and OE access times and states are satisfied. If CE, or OE access times and states are not met, valid data will be available at the latter of chip enable access (tCEA) or at output enable access time (tCEA). The state of the data input/output pins (DQ) is controlled by CE and OE. If the outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate until the next address access.
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
WRITING DATA TO RAM OR CLOCK The DS1743 is in the write mode whenever WE, and CE are in their active state. The start of a write is referenced to the latter occurring transition of WE, on CE. The addresses must be held valid throughout the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the data bus can become active with read data defined by the address inputs. A low transition on WE will then disable the outputs tWEZ after WE goes active. DATA-RETENTION MODE The 5V device is fully accessible and data can be written or read only when VCC is greater than VPF. However, when VCC is below the power-fail point, VPF, (point at which write protection occurs) the internal clock registers and SRAM are blocked from any access. At this time (PowerCap only) the power-fail reset-output signal (RST) is driven active and remains active until VCC returns to nominal levels. When VCC falls below the battery switch point VSO (battery supply level), device power is switched from the VCC in to the backup battery. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. The 3.3V device is fully accessible and data can be written or read only when VCC is greater than VPF. When VCC falls below the power-fail point, VPF, access to the device is inhibited. At this time the power-fail reset-output signal (RST) is driven active and remains active until VCC returns to nominal levels. If VPF is less than VSO, the device power is switched from VCC to the backup supply (VBAT) when VCC drops below VPF. If VPF is greater than VSO, the device power is switched from VCC to the backup supply (VBAT) when VCC drops below VSO. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. The RST (PowerCap only) signal is an open-drain output and requires a pullup resistor. Except for RST, all control, data, and address signals must be powered down when VCC is powered down. BATTERY LONGEVITY The DS1743 has a lithium power source that is designed to provide energy for clock activity and clock and RAM data retention when the VCC supply is not present. The capability of this internal power supply is sufficient to power the DS1743 continuously for the life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at +25°C with the internal clock oscillator running in the absence of VCC power. Each DS1743 is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VPF, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the DS1743 will be longer than 10 years since no lithium battery energy is consumed when VCC is present. BATTERY MONITOR The DS1743 constantly monitors the battery voltage of the internal battery. The battery flag bit (bit 7) of the day register is used to indicate the voltage level range of the battery. This bit is not writeable and should always be a 1 when read. If a 0 is ever present, an exhausted lithium energy source is indicated and both the contents of the RTC and RAM are questionable.
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………………………-0.3V to +6.0V Storage Temperature Range……………………………………………………………………….-40°C to +85°C Soldering Temperature (EDIP) (leads, 10 seconds)…………………….……………………………..…+260°C Soldering Temperature…………………………………………..….See J-STD-020 Specification (See Note 8) This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. OPERATING RANGE RANGE TEMP RANGE VCC Commercial 0°C to +70°C 3.3V ±10% or 5V ±10% Industrial -40°C to +85°C 3.3V ±10% or 5V ±10% RECOMMENDED DC OPERATING CONDITIONS (TA = Over the Operating Range.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Logic 1 Voltage All Inputs VIH VCC = 5V ±10% 2.2 VCC +0.3V V 1
VCC = 3.3V ±10% 2.0 VCC +0.3V V 1
Logic 0 Voltage All Inputs VIL VCC = 5V ±10% -0.3 +0.8 V 1
VCC = 3.3V ±10% -0.3 +0.6 V 1 DC ELECTRICAL CHARACTERISTICS (5V)
( VCC = 5.0V ±10%, TA = Over the Operating Range.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Active Supply Current ICC 15 50 mA 2, 3
TTL Standby Current (CE = VIH, CE2 = VIL) ICC1 1 3 mA 2, 3
CMOS Standby Current (CE ≥ VCC - 0.2V; CE2 = GND + 0.2V) ICC2 1 3 mA 2, 3
Input Leakage Current (Any Input) IIL -1 +1 µA
Output Leakage Current (Any Output) IOL -1 +1 µA
Output Logic 1 Voltage (IOUT = -1.0mA) VOH 2.4 1
Output Logic 0 Voltage (IOUT = 2.1mA) VOL1 0.4 1
Write-Protection Voltage VPF 4.20 4.50 V 1
Battery Switchover Voltage VSO VBAT 1, 4
