DS1742 ,Y2KC Nonvolatile Real Time Clocks RAMPIN DESCRIPTION PIN NAM33B E FUNCTION 1 A7 2 A6 3 A5 4 A4 5 A3 6 A2 Address Input 7 A1 8 A0 19 A10 ..
DS1742-100 ,Y2KC Nonvolatile Timekeeping RAMPIN DESCRIPTIONleap year compensation valid up to the year2100 A0-A10 - Address Inputs Battery vol ..
DS1742-100+ ,Y2KC Nonvolatile Timekeeping RAMFEATURES PIN CONFIGURATION Integrated NV SRAM, Real-Time Clock, TOP VIEW Crystal, Power-Fail Co ..
DS1742-100+ ,Y2KC Nonvolatile Timekeeping RAM DS1742 Y2KC Nonvolatile Timekeeping RAM
DS1742-70 ,Y2KC Nonvolatile Timekeeping RAMFEATURES Integrated NV SRAM, real time clock,A7 1 24 VCCcrystal, power-fail control circuit and li ..
DS1742-70+ ,Y2KC Nonvolatile Timekeeping RAMPIN DESCRIPTION PIN NAM33B E FUNCTION 1 A7 2 A6 3 A5 4 A4 5 A3 6 A2 Address Input 7 A1 8 A0 19 A10 ..
DV74AC244 , Octal buffer/Line Driver with 3-state Outputs
DVIULC6-2P6 ,Ultra Low capacitance 2 lines ESD protectionApplicationsBenefits■ DVI ports up to 1.65 Gb/s■ ESD standards compliance guaranteed at ■ IEEE 1394 ..
DVIULC6-4SC6 ,Ultralow capacitance ESD protectionFeatures■ 4-line ESD protection (IEC 61000-4-2)■ Protects V when applicableBUS■ Ultralow capacitanc ..
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DS1742
Y2KC Nonvolatile Real Time Clocks RAM
FEATURES Integrated NV SRAM, Real-Time Clock, Crystal, Power-Fail Control Circuit and Lithium Energy Source Clock Registers are Accessed Identically to the Static RAM; These Registers are Resident in the Eight Top RAM Locations Century Byte Register Totally Nonvolatile with Over 10 Years of Operation in the Absence of Power BCD Coded Century, Year, Month, Date, Day, Hours, Minutes, and Seconds with Automatic Leap Year Compensation Valid Up to the year 2100 Battery Voltage Level Indicator Flag Power-Fail Write Protection Allows for ±10% VCC Power Supply Tolerance Lithium Energy Source is Electrically Disconnected to Retain Freshness until Power is Applied for the First Time Standard JEDEC Bytewide 2k x 8 Static RAM Pinout Quartz Accuracy ±1 Minute a Month at +25°C, Factory Calibrated Underwriters Laboratories (UL) Recognized
PIN CONFIGURATION
ORDERING INFORMATION
PART VOLTAGE (V) TEMP RANGE PIN-PACKAGE TOP MARK** DS1742-85+ 5.0 0°C to +70°C 24 EDIP (0.740a) DS1742-85+
DS1742-100+ 5.0 0°C to +70°C 24 EDIP (0.740a) DS1742-100+ DS1742-100IND+ 5.0 -40°C to +85°C 24 EDIP (0.740a) DS1742-100IND+ DS1742W-120+ 3.3 0°C to +70°C 24 EDIP (0.740a) DS1742W-120+ DS1742W-150+ 3.3 0°C to +70°C 24 EDIP (0.740a) DS1742W-150+
+Denotes a lead(Pb)-free/RoHS-compliant device. **The top mark will include a “+” on lead(Pb)-free devices.
VCC A8 A9
WE
OE A10
CE DQ7 DQ6 DQ5 DQ4 DQ3 2 3 4 5 6 7 8 9 10 11 12
A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2GND
24 23 22 21 20 19 18 17 16 15 14 13
DS1742
ENCAPSULATED DIP TOP VIEW
DS1742 Y2KC Nonvolatile Timekeeping RAM DS1742
PIN DESCRIPTION PIN 33BNAME
FUNCTION 1 A7
Address Input A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 A0 19 A10 22 A9 23 A8 9 DQ0
Data Input/Output
10 DQ1 11 DQ2 13 DQ3 14 DQ4 15 DQ5 16 DQ6 17 DQ7 12 GND Ground 18 CE Active-Low Chip-Enable Input 20 OE Active-Low Output-Enable Input 21 WE Active-Low Write-Enable Input 24 VCC Power-Supply Input
DESCRIPTION The DS1742 is a full-function, year 2000-compliant (Y2KC), real-time clock/calendar (RTC) and 2k x 8 nonvolatile static RAM. User access to all registers within the DS1742 is accomplished with a bytewide interface as shown in Figure 1. The RTC information and control bits reside in the eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day of the month and leap year are made automatically. The RTC clock registers are double-buffered to avoid access of incorrect data that can occur during clock update cycles. The double-buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The DS1742 also contains its own power-fail circuitry, which deselects the device when the VCC supply is in an out-of-tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by low VCC as errant access and update cycles are avoided.
DS1742
CLOCK OPERATIONS—READING THE CLOCK While the double-buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1742 clock registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock register updating process does not affect clock accuracy. Updating is halted when a 1 is written into the read bit, bit 6 of the century register, see Table 2. As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count, that is day, date, and time that was current at the moment the halt command was issued. However, the internal clock registers of the double-buffered system continue to update so that the clock accuracy is not affected by the access of data. All of the DS1742 registers are updated simultaneously after the internal clock register updating process has been re-enabled. Updating is within a second after the read bit is written to 0. The READ bit must be a zero for a minimum of 500µs to ensure the external registers will be updated.
Figure 1. DS1742 BLOCK DIAGRAM Table 1. TRUTH TABLE 0BVCC
CE OE WE 1BMODE 2BDQ 3BPOWER
VCC > VPF
VIH X X Deselect High-Z Standby VIL X VIL Write Data In Active VIL VIL VIH Read Data Out Active VIL VIH VIH Read High-Z Active VSO < VCC < VPF X X X Deselect High-Z CMOS Standby VCC < VSO < VPF X X X Deselect High-Z 32BData Retention Mode
DS1742
SETTING THE CLOCK As shown in Table 2, bit 7 of the Control register is the W (write) bit. Setting the W bit to 1 halts updates to the DS1742 registers. The user can subsequently load correct date and time values into all eight registers, followed by a write cycle of 00h to the Control register to clear the W bit and transfer those new settings into the clock, allowing timekeeping operations to resume from the new set point. Again referring to Table 2, bit 6 of the Control register is the R (read) bit. Setting the R bit to 1 halts updates to the DS1742 registers. The user can subsequently read the date and time values from the eight registers without those contents possibly changing during those I/O operations. A subsequent write cycle of 00h to the Control register to clear the R bit allows timekeeping operations to resume from the previous set-point. The pre-existing contents of the Control register bits 0:5 (Century value) are ignored/unmodified by a write cycle to Control if either the W or R bits are being set to 1 in that write operation. The pre-existing contents of the Control register bits 0:5 (Century value) will be modified by a write cycle to Control if the W bit is being cleared to 0 in that write operation. The pre-existing contents of the Control register bits 0:5 (Century value) will not be modified by a write cycle to Control if the R bit is being cleared to 0 in that write operation. STOPPING AND STARTING THE CLOCK OSCILLATOR The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off to minimize current drain from the battery. The OSCbit is the MSB (bit 7) of the seconds registers, see Table 2. Setting it to a 1 stops the oscillator. FREQUENCY TEST BIT As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency
as long as conditions for access remain valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and stable). CLOCK ACCURACY The DS1742 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. Dallas Semiconductor calibrates the RTC at the factory using nonvolatile tuning elements. The DS1742 does not require additional calibration. For this reason, methods of field clock calibration are not available and not necessary. Clock accuracy is also affected by the electrical environment and caution should be taken to place the RTC in the lowest level EMI section of the PCB layout. For additional information, refer to Application Note 58.
DS1742 Table 2. REGISTER MAP ADDRESS DATA
42BFUNCTION 43BRANGE B7 B6 B5 B4 B3 B2 B1 B0
7FF 10 Year Year Year 00–99
7FE X X X 10 Month Month Month 01–12
7FD X X 10 Date Date Date 01–31
7FC BF FT X X X Day Day 01–07 7FB X X 10 Hour Hour Hour 00–23
7FA X 10 Minutes Minutes Minutes 00–59 7F9 OSC 10 Seconds Seconds Seconds 00–59
7F8 W R 10 Century Century Control 00–39 OSC = STOP BIT R = READ BIT FT = FREQUENCY TEST
W = WRITE BIT X = SEE NOTE BELOW BF = BATTERY FLAG
Note: All indicated “X” bits are not used but must be set to “0” during write cycle to ensure proper clock operation.
DS1742
RETRIEVING DATA FROM RAM OR CLOCK
The DS1742 is in the read mode whenever OE (output enable) is low, WE (write enable) is
high, and CE (chip enable) is low. The device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid data will be available at the DQ pins within tAA
after the last address input is stable, providing that the CE and OE access times and states are
satisfied. If CE or OE access times and states are not met, valid data will be available at the latter of chip enable access (tCEA) or at output enable access time (tOEA). The state of the data
input/output pins (DQ) is controlled by CE, and OE. If the outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If the address inputs are changed while and OE remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate until the next address access. WRITING DATA TO RAM OR CLOCK
The DS1742 is in the write mode whenever WE and CE are in their active state. The start of a
write is referenced to the latter occurring transition of WE on CE. The addresses must be held
valid throughout the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a typical application, the OE signal will be high during a write
cycle. However, OE can be active provided that care is taken with the data bus to avoid bus
contention. If OE is low prior to WE transitioning low the data bus can become active with read
data defined by the address inputs. A low transition on WE will then disable the outputs tWEZ
after WE goes active. DATA RETENTION MODE The 5V device is fully accessible and data can be written or read only when VCC is greater than VPF. However, when VCC is below the power fail point, VPF, (point at which write protection occurs) the internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to the backup battery. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. The 3.3V device is fully accessible and data can be written or read only when VCC is greater than VPF. When VCC falls below the power fail point, VPF, access to the device is inhibited. If VPF is less than Vso, the device power is switched from VCC to the backup supply (VBAT) when VCC drops below VPF. If VPF is greater than Vso, the device power is switched from VCC to the backup supply (VBAT) when VCC drops below Vso. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels.
DS1742
BATTERY LONGEVITY The DS1742 has a lithium power source that is designed to provide energy for clock activity, and clock and RAM data retention when the VCC supply is not present. The capability of this internal power supply is sufficient to power the DS1742 continuously for the life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at 25°C with the internal clock oscillator running in the absence of VCC power. Each DS1742 is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VPF, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the DS1742 will be much longer than 10 years since no lithium battery energy is consumed when VCC is present. BATTERY MONITOR The DS1742 constantly monitors the battery voltage of the internal battery. The Battery Flag bit (bit 7) of the day register is used to indicate the voltage level range of the battery. This bit is not writable and should always be a 1 when read. If a 0 is ever present, an exhausted lithium energy source is indicated and both the contents of the RTC and RAM are questionable.
DS1742
ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………..-0.3V to +6.0V Storage Temperature Range………………………………………………………...-40°C to +85°C Soldering Temperature (EDIP, leads)..……………………..+260°C for 10 seconds (See Note 7) This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. OPERATING RANGE RANGE TEMPERATURE VCC Commercial 0°C to +70°C (noncondensing) 3.3V ±10% or 5V ±10% Industrial -40°C to +85°C (noncondensing) 3.3V ±10% or 5V ±10% RECOMMENDED DC OPERATING CONDITIONS (Over the operating range)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Logic 1 Voltage (All Inputs)
VCC = 5V ±10% VIH 2.2 VCC + 0.3V V 1
VCC = 3.3V ±10% VIH 2.0 VCC + 0.3V V 1
Logic 0 Voltage (All Inputs)
VCC = 5V ±10% VIL -0.3 +0.8 V 1
VCC = 3.3V ±10% VIL -0.3 +0.6 V 1 DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ±10%, Over the operating range.)
4BPARAMETER 5BSYMBOL 6BMIN 7BTYP 8BMAX 9BUNITS 10BNOTES
Active Supply Current ICC 15 50 mA 2, 3
TTL Standby Current (CE= VIH) ICC1 1 3 mA 2, 3
CMOS Standby Current (CE ≥VCC - 0.2V) ICC2 1 3 mA 2, 3
Input Leakage Current (Any Input) IIL -1 +1 µA
Output Leakage Current (Any Output) IOL -1 +1 µA
Output Logic 1 Voltage (IOUT = -1.0mA) VOH 2.4 1
Output Logic 0 Voltage (IOUT = +2.1mA) VOL 0.4 1
Write Protection Voltage VPF 4.25 4.50 V 1
Battery Switchover Voltage VSO VBAT 1, 4
DS1742
DC ELECTRICAL CHARACTERISTICS (VCC = 3.3V ±10%, Over the operating range.)
11BPARAMETER 12BSYMBOL 13BMIN 14BTYP 15BMAX 16BUNITS 17BNOTES
Active Supply Current ICC 10 30 mA 2, 3
TTL Standby Current (CE = VIH) ICC1 0.7 2 mA 2, 3
CMOS Standby Current CE ≥VCC - 0.2V) ICC2 0.7 2 mA 2, 3
Input Leakage Current (any input) IIL -1 +1 µA
Output Leakage Current (Any Output) IOL -1 +1 µA
Output Logic 1 Voltage (IOUT = -1.0mA) VOH 2.4 1
Output Logic 0 Voltage (IOUT =2.1mA) VOL 0.4 1
Write Protection Voltage VPF 2.80 2.97 V 1
Battery Switchover Voltage VSO VBAT or VPF V 1, 4 AC CHARACTERISTICS—READ CYCLE (5V) (VCC = 5.0V ±10%, Over the operating range.)
34BPARAMETER 35BSYMBOL 85ns ACCESS 100ns ACCESS UNITS
MIN MAX MIN MAX
Read Cycle Time tRC 85 100 ns
Address Access Time tAA 85 100 ns to DQ Low-Z tCEL 5 5 ns Access Time tCEA 85 100 ns Data Off time tCEZ 30 35 ns to DQ Low-Z tOEL 5 5 ns Access Time tOEA 45 55 ns Data Off Time tOEZ 30 35 ns
Output Hold from Address tOH 5 5 ns
