DS1742-100 ,Y2KC Nonvolatile Timekeeping RAMPIN DESCRIPTIONleap year compensation valid up to the year2100 A0-A10 - Address Inputs Battery vol ..
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DS1742-100+ ,Y2KC Nonvolatile Timekeeping RAM DS1742 Y2KC Nonvolatile Timekeeping RAM
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DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DS1742-100-DS1742-70-DS1742W-120-DS1742W-150
Y2KC Nonvolatile Timekeeping RAM
FEATURESIntegrated NV SRAM, real time clock,
crystal, power-fail control circuit and lithiumenergy sourceClock registers are accessed identical to the
static RAM. These registers are resident in
the eight top RAM locationsCentury byte registerTotally nonvolatile with over 10 years of
operation in the absence of powerBCD coded century, year, month, date, day,
hours, minutes, and seconds with automatic
leap year compensation valid up to the year2100Battery voltage level indicator flagPower-fail write protection allows for ±10%
VCC power supply toleranceLithium energy source is electrically
disconnected to retain freshness until power is
applied for the first timeStandard JEDEC bytewide 2k x 8 static RAM
pinoutQuartz accuracy ±1 minute a month @ 25°C,
factory calibrated
PIN ASSIGNMENT
PIN DESCRIPTIONA0-A10 - Address Inputs - Chip Enable - Output Enable - Write Enable
VCC- Power Supply Input
GND - Ground
DQ0-DQ7 - Data Input/Outputs
ORDERING INFORMATIONDS1742-XXX(5V)-70 70 ns access
-100 100 ns access
DS1742W-XXX(3.3V)
-120 120 ns access
-150150 ns access
DESCRIPTIONThe DS1742 is a full function, year 2000-compliant (Y2KC), real-time clock/calendar (RTC) and 2k x 8
non-volatile static RAM. User access to all registers within the DS1742 is accomplished with a bytewide
interface as shown in Figure 1. The Real Time Clock (RTC) information and control bits reside in the
eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours,
minutes, and seconds data in 24-hour BCD format. Corrections for the day of the month and leap year
DS1742
Y2KC Nonvolatile Timekeeping RAM
www.dalsemi.comVCC
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
GND
DS1742
The RTC clock registers are double-buffered to avoid access of incorrect data that can occur during clock
update cycles. The double buffered system also prevents time loss as the timekeeping countdown
continues unabated by access to time register data. The DS1742 also contains its own power-fail
circuitry, which deselects the device when the VCC supply is in an out of tolerance condition. This featureprevents loss of data from unpredictable system operation brought on by low VCC as errant access and
update cycles are avoided.
CLOCK OPERATIONS-READING THE CLOCKWhile the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1742 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.Updating is halted when a 1 is written into the read bit, bit 6 of the century register, see Table 2. As long
as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count,
that is day, date, and time that was current at the moment the halt command was issued. However, the
internal clock registers of the double-buffered system continue to update so that the clock accuracy is not
affected by the access of data. All of the DS1742 registers are updated simultaneously after the internalclock register updating process has been re-enabled. Updating is within a second after the read bit is
written to 0. The READ bit must be a zero for a minimum of 500 μs to ensure the external registers will
be updated.
DS1742 BLOCK DIAGRAM Figure 1
DS1742 TRUTH TABLE Table 1
SETTING THE CLOCKAs shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a 1, like the read
DS1742
STOPPING AND STARTING THE CLOCK OSCILLATORThe clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned
off to minimize current drain from the battery. The OSCbit is the MSB (bit 7) of the seconds registers,
see Table 2. Setting it to a 1 stops the oscillator.
FREQUENCY TEST BITAs shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to
logic 1 and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the
seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for
access remain valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and
stable).
CLOCK ACCURACYThe DS1742 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements. The DS1742 does
not require additional calibration. For this reason, methods of field clock calibration are not available andnot necessary. Clock accuracy is also effected by the electrical environment and caution should be taken
to place the RTC in the lowest level EMI section of the PCB layout. For additional information please
see application note 58.
DS1742 REGISTER MAP Table 2FUNCTION/RANGE10 YearXFTXX
OSC = STOP BITR = READ BITFT = FREQUENCY TEST
W = WRITE BITX = SEE NOTE BELOWBF = BATTERY FLAG
NOTE:All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCKThe DS1742 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE
(chip enable) is low. The device architecture allows ripplethrough access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is
stable, providing that the CE, and OE access times and states are satisfied. If CE, or OE access times
and states are not met, valid data will be available at the latter of chip enable access (tCEA) or at output
enable access time (tOEA). The state of the data input/output pins (DQ) is controlled by CE, and OE. If
DS1742
address inputs are changed while CE, and OE remain valid, output data will remain valid for output datahold time (tOH) but will then go indeterminate until the next address access.
WRITING DATA TO RAM OR CLOCKThe DS1742 is in the write mode whenever WE, and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE, on CE. The addresses must be held valid throughout
the cycle. CE, or WE must return inactive for a minimum of tWR prior to the initiation of another read or
write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active provided
that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low
the data bus can become active with read data defined by the address inputs. A low transition on WE will
then disable the outputs tWEZ after WE goes active.
DATA RETENTION MODEThe 5-volt device is fully accessible and data can be written or read only when VCC is greater than VPF.However, when VCC is below the power fail point, VPF, (point at which write protection occurs) the
internal clock registers and SRAM are blocked from any access. At this time the power fail reset output
signal (RST) is driven active and will remain active until VCC returns to nominal levels. When VCC falls
below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to
the backup battery. RTC operation and SRAM data are maintained from the battery until VCC is returned
to nominal levels. The 3.3 volt device is fully accessible and data can be written or read only when VCC is
greater than VPF. When VCC falls below the power fail point, VPF, access to the device is inhibited. At this
time the power fail reset output signal (RST) is driven active and will remain active until VCC returns to
nominal levels. If VPF is less than Vso, the device power is switched from VCC to the backup supply (VBAT)when VCC drops below VPF. If VPF is greater than Vso, the device power is switched from VCC to the
backup supply (VBAT) when VCC drops below Vso. RTC operation and SRAM data are maintained from
the battery until VCC is returned to nominal levels. The RSTsignal is an open drain output and requires a
pull up. Except for the RST, all control, data, and address signals must be powered down when VCC is
powered down.
BATTERY LONGEVITYThe DS1742 has a lithium power source that is designed to provide energy for clock activity, and clock
and RAM data retention when the VCC supply is not present. The capability of this internal power supply
is sufficient to power the DS1742 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at 25°C with the internal clock oscillator running inthe absence of VCC power. Each DS1742 is shipped from Dallas Semiconductor with its lithium energy
source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than
VPF, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the
DS1742 will be much longer than 10 years since no lithium battery energy is consumed when VCC is
present.
BATTERY MONITORThe DS1742 constantly monitors the battery voltage of the internal battery. The Battery Flag bit (bit 7) of
the day register is used to indicate the voltage level range of the battery. This bit is not writable and
should always be a 1 when read. If a 0 is ever present, an exhausted lithium energy source is indicated
and both the contents of the RTC and RAM are questionable.
DS1742
ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground -0.3V to +6.0V
Operating Temperature 0°C to 70°C
Storage Temperature -20°C to +70°C
Soldering Temperature See J-STD-020A Specification (See Note 7)
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
OPERATING RANGE
RECOMMENDED DC OPERATING CONDITIONS (Over the Operating Range)
DC ELECTRICAL CHARACTERISTICS (Over the Operating Range; VCC = 5.0V ± 10%)
DS1742
DC ELECTRICAL CHARACTERISTICS(Over the Operating Range; VCC = 3.3V ± 10%)
READ CYCLE, AC CHARACTERISTICS
(Over the Operating Range; VCC = 5.0V ± 10%)
