DS17285S-5+ ,3V/5V Real-Time ClocksElectrical Characteristics(V = 0V, V = 3.0V, T = Over the operating range, unless otherwise noted.) ..
DS17287 ,3V/5V Real-Time Clockfeatures:X1 23 SQW2 Y2K compliantVBAUXX2 3 22 +3V or +5V operationAD0 4 21 RCLR SMI recovery sta ..
DS17287-3 ,3V/5V Real-Time ClockPIN DESCRIPTIONX1 - Crystal InputX2 - Crystal OutputRCLR - RAM Clear InputAD0–AD7 - Multiplexed Add ..
DS17287-3+ ,3V/5V Real-Time ClocksFeaturesThe DS17285, DS17485, DS17885, DS17287, DS17487, ● Incorporates Industry-Standard DS12887 P ..
DS17287-5 ,3V/5V Real-Time Clockfeatures described above. An external crystal and batteryare the only components required to mainta ..
DS17287-5+ ,3V/5V Real-Time ClocksElectrical Characteristics(V = 0V, V = 3.0V, T = Over the operating range, unless otherwise noted.) ..
DV74AC244 , Octal buffer/Line Driver with 3-state Outputs
DVIULC6-2P6 ,Ultra Low capacitance 2 lines ESD protectionApplicationsBenefits■ DVI ports up to 1.65 Gb/s■ ESD standards compliance guaranteed at ■ IEEE 1394 ..
DVIULC6-4SC6 ,Ultralow capacitance ESD protectionFeatures■ 4-line ESD protection (IEC 61000-4-2)■ Protects V when applicableBUS■ Ultralow capacitanc ..
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DS17285S-5+-DS17287-3+-DS17287-5+-DS17487-3+-DS17487-5+-DS17487-5IND+-DS17887-3-DS17887-3+-DS17887-5-DS17887-5+
3V/5V Real-Time Clocks
General DescriptionThe DS17285, DS17485, DS17885, DS17287, DS17487,
and DS17887 real-time clocks (RTCs) are designed to
be successors to the industry-standard DS12885 and
DS12887. The DS17285, DS17485, and DS17885 (here-
after referred to as the DS17x85) provide a real-time
clock/calendar, one time-of-day alarm, three maskable
interrupts with a common interrupt output, a program-
mable square wave, and 114 bytes of battery-backed
NV SRAM. The DS17x85 also incorporates a number
of enhanced functions including a silicon serial number,
power-on/off control circuitry, and 2k, 4k, or 8kbytes of
battery-backed NV SRAM. The DS17287, DS17487, and
DS17887 (hereafter referred to as the DS17x87) integrate
a quartz crystal and lithium energy source into a 24-pin
encapsulated DIP package. The DS17x85 and DS17x87
power-control circuitry allows the system to be powered
on by an external stimulus such as a keyboard or by a
time-and-date (wake-up) alarm. The PWR output pin is
triggered by one or either of these events, and is used to
turn on an external power supply. The PWR pin is under
software control, so that when a task is complete, the
system power can then be shut down.
For all devices, the date at the end of the month is auto-
matically adjusted for months with fewer than 31 days,
including correction for leap years. It also operates in
either 24-hour or 12-hour format with an AM/PM indicator. precision temperature-compensated circuit monitors
the status of VCC. If a primary power failure is detected,
the device automatically switches to a backup supply. A
lithium coin cell battery can be connected to the VBAT
input pin on the DS17x85 to maintain time and date oper-
ation when primary power is absent. The DS17x85 and
DS17x87 include a VBAUX input used to power auxiliary
functions such as PWR control. The device is accessed
through a multiplexed byte-wide interface.
Applications●Embedded Systems●Utility Meters●Security Systems●Network Hubs, Bridges, and Routers
Features●Incorporates Industry-Standard DS12887 PC
Clock Plus Enhanced Functions●RTC Counts Seconds, Minutes, Hours, Day, Date,
Month, and Year with Leap Year Compensation
Through 2099●Optional +3.0V or +5.0V Operation●SMI Recovery Stack●64-Bit Silicon Serial Number●Power-Control Circuitry Supports System Power-
On from Date/Time Alarm or Key Closure●Crystal Select Bit Allows Operation with 6pF or
12.5pF Crystal●12-Hour or 24-Hour Clock with AM and PM in
12-Hour Mode●114 Bytes of General-Purpose, Battery-Backed NV
SRAM●Extended Battery-Backed NV SRAM 2048 Bytes (DS17285/DS17287) 4096 Bytes (DS17485/DS17487) 8192 Bytes (DS17885/DS17887)●RAM Clear Function●Interrupt Output with Six Independently Maskable
Interrupt Flags●Time-of-Day Alarm Once per Second to Once per
Day●End of Clock Update Cycle Flag●Programmable Square-Wave Output●Automatic Power-Fail Detect and Switch Circuitry●Available in PDIP, SO, or TSOP Package
(DS17285, DS17485, DS17885)●Optional Encapsulated DIP (EDIP) Package with
Integrated Crystal and Battery (DS17287,
DS17487, DS17887)●Optional Industrial Temperature Range Available●Underwriters Laboratory (UL) Recognized
Ordering Information, Pin Configurations, and Typical
Operating Circuit appear at end of data sheet.
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
Voltage Range on VCC Pin Relative to Ground ...-0.3V to +6.0V
Operating Temperature Range (Noncondensing)
Commercial.........................................................0°C to +70°C
Industrial .........................................................-40°C to +85°C
Storage Temperature Range
EDIP ...............................................................-40°C to +85°C
PDIP, SO, TSOP ...........................................-55°C to +125°C
Lead Temperature (soldering, 10s) .................................+260°C
(Note: EDIP is hand or wave-soldered only.)
Soldering Temperature (reflow) .......................................+260°C
(VCC = +4.5V to +5.5V, or VCC = +2.7V to +3.7V, TA = Over the operating temperature range, unless otherwise noted. Typical
values are with TA = +25°C, VCC = 5.0V or 3.0V and VBAT = 3.0V, unless otherwise noted.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSupply Voltage (Note 3)VCC(-5)4.55.05.5V(-3)2.73.03.7
VBAT Input Voltage VBAT(Note 3)2.53.03.7V
VBAUX Input Voltage (Note 3)VBAUX(-5)2.53.05.2V(-3)3.7
Input Logic 1 (Note 3)VIH
(-5)2.2VCC +
0.3V
(-3)2.0VCC +
Input Logic 0 (Note 3)VIL(-5)-0.3+0.8V(-3)-0.3+0.6
VCC Power-Supply Current
(Note 4)ICC1(-5)2550mA(-3)1530
VCC Standby Current (Notes 4, 5)ICCS(-5)1.03.0mA(-3)0.52.0
Input LeakageIIL-1.0+1.0µA
I/O LeakageIOL(Note 6)-1.0+1.0µA
Output Logic 1 Voltage (Note 3) VOH(-5), -1.0mA2.4V(-3), -0.4mA2.4
Output Logic 0 Voltage
AD0–AD7, IRQ, SQW (Note 3)VOL(-5), +2.1mA0.4V(-3), +0.8mA0.4
Output Logic 0 Voltage
PWR (Note 3)VOL(-5), +10mA0.4V(-3), +4mA0.4
Power-Fail Voltage (Note 3)VPF(-5)4.254.374.5V(-3)2.52.62.7
VRT Trip PointVRTTRIP(Note 3)1.3V
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
DC Electrical Characteristics
(VCC = 0V, VBAT = 3.0V, TA = Over the operating range, unless otherwise noted.) (Note 1)(VCC = +4.5V to +5.5V, TA = Over the operating range, unless otherwise noted.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSVBAT or VBAUX Current
(Oscillator On); TA = +25°C,
VBAT = 3.0V
IBAT(Note 7)500700nA
VBAT or VBAUX Current
(Oscillator Off)IBATDR(Note 7)50400nA
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSCycle TimetCYC240DCns
Pulse Width, RD or WR LowPWRWL120ns
Pulse Width, RD or WR HighPWRWH80ns
Input Rise and FalltR, tF30ns
Chip-Select Setup Time Before
RD or WRtCS20ns
Chip-Select Hold TimetCH0ns
Read-Data Hold TimetDHR1050ns
Write-Data Hold TimetDHW0ns
Address Setup Time to ALE FalltASL20ns
Address Hold Time to ALE FalltAHL10ns
RD or WR High Setup to ALE
RisetASD25ns
Pulse Width ALE HighPWASH40ns
Delay Time ALE Low to RD LowtASED30ns
Output Data Delay Time from RDtDDR(Note 8)20120ns
Data Setup TimetDSW30ns
IRQ Release from RDtIRD2µs
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
DC Electrical Characteristics
AC Electrical Characteristics
(VCC = +2.7V to +3.7V, TA = Over the operating range, unless otherwise noted.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSCycle TimetCYC360DCns
Pulse Width, RD or WR LowPWRWL200ns
Pulse Width, RD or WR HighPWRWH150ns
Input Rise and FalltR, tF30ns
Chip-Select Setup Time Before
RD or WRtCS20ns
Chip-Select Hold TimetCH0ns
Read-Data Hold TimetDHR1090ns
Write-Data Hold TimetDHW0ns
Address Setup Time to ALE FalltASL40ns
Address Hold Time to ALE FalltAHL10ns
RD or WR High Setup to ALE
RisetASD30ns
Pulse Width ALE HighPWASH40ns
Delay Time ALE Low to RD LowtASED30ns
Output Data Delay Time from RDtDDR(Note 8)20200ns
Data Setup TimetDSW70ns
IRQ Release from RDtIRD2µs
PWASH
tASED
PWRWHPWRWL
tCS
tAHLtASLtDSWtDHW
tCH
tASD
tASD
tCYC
AD0–AD7
WRITE
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
AC Electrical Characteristics
Write Timing
AD0–AD7
CS, WR, RD
HIGH IMPEDANCE
DON'T CARE
VALID
RECOGNIZEDRECOGNIZED
VALID
VCC
VPF(MAX)
VPF(MIN)
tREC
tASLtDDR
PWASH
ALE
AD0–AD7
tASD
PWRWL
tCS
tDHRtAHL
tCH
tCYC
PWRWH
tASED
IRQ
tIRD
tASD
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
Power-Up/Power-Down Timing
Read Timing
Note 1: RTC modules can be successfully processed through conventional wave-soldering techniques as long as temperature
exposure to the lithium energy source contained within does not exceed +85°C. However, post-solder cleaning with water-
washing techniques is acceptable, provided that ultrasonic vibrations not used to prevent damage to the crystal.
Note 2: Limits at -40°C are guaranteed by design and not production tested.
Note 3: All voltages are referenced to ground.
Note 4: All outputs are open.
Note 5: Specified with CS = RD = WR = VCC, ALE, AD0–AD7 = 0.
Note 6: Applies to the AD0–AD7 pins, IRQ, and SQW when each is in a high-impedance state.
Note 7: Measured with a 32.768kHz crystal attached to X1 and X2.
Note 8: Measured with a 50pF capacitance load plus 1TTL gate.
Note 9: If the oscillator is disabled in software, or if the countdown chain is in reset, tREC is bypassed, and the part becomes
immediately accessible.
Note 10: Guaranteed by design. Not production tested.
(TA = -40°C to +85°C) (Note 2)
(TA = +25°C)
(TA = +25°C) (Note 10)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSRecovery at Power-UptREC(Note 9)20150ms
VCC Fall Time, VPF(MAX) to
VPF(MIN)tF300µs
VCC Fall Time, VPF(MAX) to
VPF(MIN)tR0µs
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSExpected Data RetentiontDR(Note 9)10Years
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSCapacitance on All Input Pins
Except X1CIN(Note 10)12pF
Capacitance on IRQ, SQW, and
DQ0–DQ7 PinsCIO(Note 10)12pF
PARAMETERCONDITIONSInput Pulse Levels:0 to 3.0V
Output Load Including Scope and Jig:50pF + 1TTL Gate
Input and Output Timing Measurement Reference Levels:Input/Output: VIL max and VIH min
Input Pulse Rise and Fall Times:5ns
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
Power-Up/Power-Down Characteristics
Data Retention (DS17x87 Only)
Capacitance
AC Test Conditions
WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode can cause loss of data.
(VCC = +3.3V, TA = +25°C, unless otherwise noted.)
PINNAMEFUNCTION24288PWR
Active-Low Power-On Reset. This open-drain output pin is intended for use as an on/off control
for the system power. With VCC voltage removed from the device, PWR can be automatically
activated from a kickstart input by the KS pin or from a wake-up interrupt. Once the system is
powered on, the state of PWR can be controlled by bits in the control registers. The PWR pin
can be connected through a pullup resistor to a positive supply. For 5V operation, the voltage
of the pullup supply should be no greater than 5.7V. For 3V operation, the voltage on the pullup
supply should be no greater than 3.9V.
2, 39, 10X1, X2
Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed for operation with a crystal having a speciied load capacitance (CL) of 6pF or 12.5pF. Pin X1 is
the input to the oscillator and can optionally be connected to an external 32.768kHz oscillator.
The output of the internal oscillator, pin X2, is left unconnected if an external oscillator is
connected to pin X1. These pins are missing (N.C.) on the EDIP package.
4–1112–17,
19, 20AD0–AD7
Multiplexed Bidirectional Address/Data Bus. The addresses are presented during the irst
portion of the bus cycle and latched into the device by the falling edge of ALE. Write data is
latched by the rising edge of WR. In a read cycle, the device outputs data during the latter
portion of the RD low. The read cycle is terminated and the bus returns to a high-impedance
state as RD transitions high.
12, 1621, 22, 26GNDGround
SUPPLY CURRENT
vs. TEMPERATUREDS17285/87 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (nA)5035205-10-25
VBAT = 3.0V
OSCILLATOR FREQUENCY
vs. SUPPLY VOLTAGEDS17285/87 toc03
SUPPLY VOLTAGE (V)
OSCILLATOR FREQUENCY (Hz)
SUPPLY CURRENT
vs. INPUT VOLTAGE
DS17285/87 toc01
VBAT (V)
SUPPLY CURRENT (nA)
VCC = 0V
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
Typical Operating Characteristics
Pin Description
PINNAMEFUNCTION242823CS
Active-Low Chip-Select Input. This pin must be asserted low during a bus cycle for the device
to be accessed. CS must be kept in the active state during RD and WR. Bus cycles that take
place without asserting CS latch addresses, but no access occurs.24ALEAddress Latch Enable Input, Active High. This input pin is used to demultiplex the address/data
bus. The falling edge of ALE causes the address to be latched within the device.25WRActive-Low Write Input. This pin deines the period during which data is written to the
addressed register.27RDActive-Low Read Input. This pin identiies the period when the device drives the bus with read
data. It is an enable signal for the output buffers of the device.28KS
Active-Low Kickstart Input. When VCC is removed from the device, the system can be powered
on in response to an active-low transition on the KS pin, as might be generated from a key
closure. VBAUX must be present and auxiliary-battery-enable bit (ABE) must be set to 1 if the
kickstart function is used, and the KS pin must be pulled up to the VBAUX supply. While VCC
is applied, the KS pin can be used as an interrupt input. If not used, KS must be grounded and
ABE set to 0.1IRQ
Active-Low Interrupt Request. This pin is an active-low output that can be used as an interrupt
input to a processor. The IRQ output remains low as long as the status bit causing the interrupt
is present and the corresponding interrupt-enable bit is set. To clear the IRQ pin, the application software must clear all enabled lag bits contributing to the pin’s active state. When no interrupt
conditions are present, the IRQ level is in the high-impedance state. Multiple interrupting
devices can be connected to an IRQ bus, provided that they are all open drain. The IRQ pin
requires an external pullup resistor to VCC.2VBAT
Connection for Primary Battery. This supply input is used to power the normal clock functions
when VCC is absent. Diodes placed in series between VBAT and the battery can prevent proper
operation. If VBAT is not required, the pin must be grounded. UL recognized to ensure against
reverse charging current when used with a lithium battery (www.maximintegrated.com/qa/
info/ul). This pin is missing (N.C.) on the EDIP package.DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
Pin Description (continued)
PINNAMEFUNCTION24283RCLR
Active-Low RAM Clear Input. This pin is used to clear (set to logic 1) all the 114 bytes of
general-purpose RAM but does not affect the RAM associated with the real time clock or
extended RAM. RCLR may be invoked while the part is powered from any supply. The RCLR
function is designed to be used via a human interface (shorting to ground manually or by a
switch) and not to be driven with external buffers. This pin is internally pulled up. Do not use an
external pullup resistor on this pin.4VBAUX
Auxiliary Battery Input. Required for kickstart and wake-up functions. This input also supports
clock/calendar and user RAM if VBAT is at lower voltage or is not used. A standard +3V lithium
cell or other energy source can be used. Diodes placed in series between VBAUX and the
battery may prevent proper operation. UL recognized to ensure against reverse charging
current when used with a lithium battery (www.maximintegrated.com/qa/info/ul/). For 3V
VCC operation, VBAUX must be held between +2.5V and +3.7V. For 5V VCC operation, VBAUX
must be held between +2.5V and +5.2V. If VBAUX is not used it should be grounded and the
auxiliary-battery-enable bit bank 1, register 4BH, should = 0.5SQW
Square-Wave Output. When VCC rises above VPF, bits DV1 and E32k are set to 1. This
condition enables a 32kHz square-wave output. A square wave is output if either SQWE = 1
or E32k = 1. If E32k = 1, then 32kHz is output regardless of the other control bits. If E32k =
0, then the output frequency is dependent on the control bits in Register A. The SQW pin can
output a signal from one of 13 taps provided by the 15 internal divider stages of the RTC. The
frequency of the SQW pin can be changed by programming Register A, as shown in Table 3.
The SQW signal can be turned on and off using the SQWE bit in Register B or the E32k bit
in extended register 4Bh. A 32kHz square wave is also available when VCC is less than VPF
if E32k = 1, ABE = 1, and voltage is applied to the VBAUX pin. When disabled, SQW is high
impedance when VCC is below VPF.6, 7VCC
DC Power Pin for Primary Power Supply. When VCC is applied within normal limits, the device
is fully accessible and data can be written and read. When VCC is below VPF reads and writes
are inhibited.
2, 3,
16, 20
(DS17x87
only)
11, 18N.C.No Connection
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
Pin Description (continued)
Figure 1. Functional Diagram
OSCILLATOR
POWER
CONTROL
DS17x87
ONLY
VBAT
GND
DIVIDE
BY 8
REGISTERS A, B, C, D
CLOCK/CALENDAR
UPDATE LOGIC
EXTENDED
USER RAM
2k/4k/8k
BYTES
SELECT
EXTENDED RAM ADDR/
DATA REGISTERS
EXTENDED CONTROL/
STATUS REGISTERS
64-BIT SERIAL NUMBER
CENTURY COUNTER
DATE ALARM
RTC ADDRESS-2
RTC ADDRESS-3
DIVIDE BY
64
DIVIDE BY
64
16:1 MUX
SQUARE-
WAVE
GENERATOR
SQW
IRQ
PWR
RLCR
IRQ
GENERATORVCC
VBAUX
BUS
INTERFACE
ALE
AD0–AD7
CLOCK/CALENDAR AND
ALARM REGISTERS
BUFFERED CLOCK/
CALENDAR AND ALARM
REGISTERS
USER RAM
114 BYTES
RAM
CLEAR
LOGIC
DS17x85/87DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
Detailed DescriptionThe DS17x85 is a successor to the DS1285 real-time
clock (RTC). The device provides 18 bytes of real-time
clock/calendar, alarm, and control/status registers and 114
bytes of nonvolatile battery-backed RAM. The device also
provides additional extended RAM in either 2k/4k/8kbytes
(DS17285/DS17485/DS17885). A time-of-day alarm, six
maskable interrupts with a common interrupt output, and
a programmable square-wave output are available. It also
operates in either 24-hour or 12-hour format with an AM/
PM indicator. A precision temperature-compensated cir-
cuit monitors the status of VCC. If a primary power-supply
failure is detected, the device automatically switches to
a backup supply. The backup supply input supports a
primary battery, such as a lithium coin cell. The device is
accessed by a multiplexed address/data bus.
Oscillator CircuitThe DS17x85 uses an external 32.768kHz crystal. The
oscillator circuit does not require any external resistors
or capacitors to operate. Table 1 specifies several crystal
parameters for the external crystal, and Figure 2 shows
a functional schematic of the oscillator circuit. The oscil-
lator is controlled by an enable bit in the control register.
Oscillator startup times are highly dependent upon crystal
characteristics, PC board leakage, and layout. High ESR
and excessive capacitive loads are the major contributors
to long startup times. A circuit using a crystal with the
recommended characteristics and proper layout usually
starts within one second.
An external 32.768kHz oscillator can also drive the
DS17x85. In this configuration, the X1 pin is connected
to the external oscillator signal and the X2 pin is left
unconnected.
Clock AccuracyThe accuracy of the clock is dependent upon the accu-
racy of the crystal and the accuracy of the match between
the capacitive load of the oscillator circuit and the capaci-
tive load for which the crystal was trimmed. Additional
error will be added by crystal frequency drift caused by
temperature shifts. External circuit noise coupled into
the oscillator circuit may result in the clock running fast.
Figure 3 shows a typical PC board layout for isolation of
the crystal and oscillator from noise. Refer to Application
Note 58: Crystal Considerations with Dallas Real-Time
Clocks for detailed information.
Clock Accuracy (DS17287, Figure 2. Oscillator Circuit Showing Internal Bias Network
Table 1. Crystal Specifications* (DS17x85
Only)*The crystal, traces, and crystal input pins should be isolated
from RF generating signals. Refer to Application Note 58:
Crystal Considerations for Dallas Real-Time Clocks for addi-
tional specifications.
PARAMETERSYMBOLMINTYPMAXUNITSNominal
FrequencyfO32.768kHz
Series
ResistanceESR50kΩ
Load
CapacitanceCL6 or
12.5pF
COUNTDOWN
CHAINX2
CRYSTAL
CL1CL2RTC REGISTERS
DS17285/87
DS17485/87
DS17885/87LOCAL GROUND PLANE (TOP LAYER)
CRYSTAL
GND
NOTE: AVOID ROUTING SIGNAL LINES IN THE CROSSHATCHED AREA
(UPPER LEFT QUADRANT) OF
THE PACKAGE UNLESS THERE IS
A GROUND PLANE BETWEEN THE
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
Power-Down/Power-Up
ConsiderationsThe RTC function continues to operate, and all the RAM,
time, calendar, and alarm memory locations remain non-
volatile regardless of the level of the VCC input. VBAT or
VBAUX must remain within the minimum and maximum
limits when VCC is not applied. When VCC falls below
VPF, the device inhibits all access, putting the part into
a low-power mode. When VCC is applied and exceeds
VPF (power-fail trip point), the device becomes acces-
sible after tREC, if the oscillator is running and the oscil-
lator countdown chain is not in reset (Register A). This
time period allows the system to stabilize after power
is applied. If the oscillator is not enabled, the oscilla-
tor enable bit is enabled on powerup, and the device
becomes immediately accessible.
Power ControlThe power control function is provided by a precise,
temperature-compensated voltage reference and a com-
parator circuit that monitors the VCC level. The device is
fully accessible and data can be written and read when
VCC is greater than VPF. However, when VCC falls below
VPF, the device inhibits read and write access. If VPF is
less than VBAT, the device power is switched from VCC
to the higher of VBAT or VBAUX when VCC drops below
VPF. If VPF is greater than the higher of VBAT or VBAUX,
the device power is switched from VCC to the higher of
VBAT or VBAUX when VCC drops below the higher backup
source. The registers are maintained from the VBAT or
VBAUX source until VCC is returned to nominal levels.
After VCC returns above VPF, read and write access is
allowed after tREC.
Time, Calendar, and Alarm
LocationsThe time and calendar information is obtained by read-
ing the appropriate register bytes. The time, calendar,
and alarm are set or initialized by writing the appropriate
register bytes. The contents of the 12 time, calendar, and
alarm bytes can be either binary or binary-coded deci-
mal (BCD) format. Tables 3A and 3B show the BCD and
binary formats of the 12 time, date, and alarm registers,
control registers A to D, plus the two extended registers
that reside in bank 1 only (bank 0 and bank 1 switching is
explained later in this text).
The day-of-week register increments at midnight, incre-
menting from 1 through 7. The day-of-week register is
used by the daylight saving function, and so the value 1
is defined as Sunday. The date at the end of the month
is automatically adjusted for months with fewer than 31
days, including correction for leap years.
Before writing the internal time, calendar, and alarm
registers, the SET bit in Register B should be written to
logic 1 to prevent updates from occurring while access is
being attempted. In addition to writing the 12 time, calen-
dar, and alarm registers in a selected format (binary or
BCD), the data mode bit (DM) of Register B must be set
to the appropriate logic level. All 12 time, calendar, and
alarm bytes must use the same data mode. The set bit in
Register B should be cleared after the data mode bit has
been written to allow the real time clock to update the time
and calendar bytes. Once initialized, the real time clock
makes all updates in the selected mode. The data mode
cannot be changed without reinitializing the 12 data bytes.
Tables 3A and 3B show the BCD and binary formats of the
12 time, calendar, and alarm locations.
The 24-12 bit cannot be changed without reinitializing the
hour locations. When the 12-hour format is selected, the
high order bit of the hours byte represents PM when it is
logic 1. The time, calendar, and alarm bytes are always
accessible because they are double-buffered. Once per
second, the eight bytes are advanced by one second and
checked for an alarm condition.
If a read of the time and calendar data occurs during an
update, a problem exists where seconds, minutes, hours,
etc., may not correlate. The probability of reading incor-
rect time and calendar data is low. Several methods of
avoiding any possible incorrect time and calendar reads
are covered later in this text.
Table 2. Power Control
SUPPLY CONDITIONREAD/WRITE
ACCESSPOWERED BYVCC < VPF, VCC <
(VBAT | VBAUX)NoVBAT or VBAUX
VCC < VPF, VCC >
(VBAT | VBAUX)NoVCC
VCC > VPF, VCC <
(VBAT | VBAUX)YesVCC
VCC > VPF, VCC >
(VBAT | VBAUX)YesVCC
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
The alarm bytes can be used in two ways. First, when the
alarm time is written in the appropriate hours, minutes, and
seconds alarm locations, the alarm interrupt is initiated at
the specified time each day, if the alarm enable bit is high.
In this mode, the “0” bits in the alarm registers and the cor-
responding time registers must always be written to 0 (see
Table 3A and 3B). Writing the 0 bits in the alarm and/or time
registers to 1 can result in undefined operation.
The second use condition is to insert a “don’t care” state in one or more of the alarm bytes. The don’t care code is
any hexadecimal value from C0 to FF. The two most sig-nificant bits of each byte set the don’t care condition when
at logic 1. An alarm will be generated each hour when the “don’t care” bits are set in the hours byte. Similarly, an alarm is generated every minute with don’t care codes in
the hours and minute alarm bytes. An alarm is generated every second with don’t care codes in the hours, minutes,
and seconds alarm bytes.
All 128 bytes can be directly written or read except for the
following:
1) Registers C and D are read-only.
2) Bit 7 of register A is read-only.
3) The MSB of the seconds byte is read-only.
Note: Unless otherwise specified, the state of the registers is not defined when power is first applied. Except for the seconds reg-ister, 0 bits in the time and date registers can be written to 1, but can be modified when the clock updates. 0 bits should always be
written to 0 except for alarm mask bits.
Table 3A. Time, Calendar, and Alarm Data Modes—BCD Mode (DM = 0)
ADDRESSBIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0FUNCTIONRANGE00h010 SecondsSecondsSeconds00–59
01h010 SecondsSecondsSeconds Alarm00–59
02h010 MinutesMinutesMinutes00–59
03h010 MinutesMinutesMinutes Alarm00–59
04hAM/PM0010 HourHoursHours1–12 + AM/PM
00–23010 Hour
05hAM/PM0010 HourHoursHours Alarm1–12 + AM/PM
00–23010 Hour
06h00000DayDay01–07
07h0010 DateDateDate01–31
08h00010 MonthMonthMonth01–12
09h10 YearYearYear00–99
0AhUIPDV2DV1DV0RS3RS2RS1RS0Control—
0BhSETPIEAIEUIESQWEDM24/12DSEControl—
0ChIRQFPFAFUF0000Control—
0DhVRT0000000Control—
Bank 1, 48h10 CenturyCenturyCentury00–99
Bank 1, 49h10 DateDateDate Alarm01–31
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
Control RegistersThe four control registers (A, B, C, and D) reside in both
bank 0 and bank 1. These registers are accessible at all
times, even during the update cycle.
Bit 7: Update In Progress (UIP). This bit is a status flag that can be monitored. When the UIP bit is 1, the update
transfer will soon occur. When UIP is 0, the update trans-fer does not occur for at least 244μs. The time, calendar,
and alarm information in RAM is fully available for access
when the UIP bit is 0. The UIP bit is read-only. Writing the
SET bit in Register B to 1 inhibits any update transfer and
clears the UIP status bit.
Bits 6, 5, and 4: DV2, DV1, and DV0. These bits are used to turn the oscillator on or off and to reset the count-
down chain. A pattern of 01X is the only combination of
bits that turns the oscillator on and allows the RTC to keep
time. A pattern of 11X enables the oscillator but holds
the countdown chain in reset. The next update occurs at
500ms after a pattern of 01X is written to DV0, DV1, and
DV2. DV0 is used to select bank 0 or bank 1 as defined in
Table 5. When DV0 is set to 0, bank 0 is selected. When
DV0 is set to 1, bank 1 is selected.
Note: Unless otherwise specified, the state of the registers is not defined when power is first applied. Except for the seconds reg-ister, 0 bits in the time and date registers can be written to 1, but can be modified when the clock updates. 0 bits should always be
written to 0 except for alarm mask bits.
Table 3B. Time, Calendar, and Alarm Data Modes—Binary Mode (DM = 1)
ADDRESSBIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0FUNCTIONRANGE00h00SecondsSeconds00–3B
01h00SecondsSeconds Alarm00–3B
02h00MinutesMinutes00–3B
03h00MinutesMinutes Alarm00–3B
04hAM/PM000HoursHours1–0C + AM/PM
00–170Hours
05hAM/PM000HoursHours Alarm1–0C + AM/PM
00–170Hours
06h00000DayDay01–07
07h000DateDate01–1F
08h0000MonthMonth01–0C
09h0YearYear00–63
0AhUIPDV2DV1DV0RS3RS2RS1RS0Control—
0BhSETPIEAIEUIESQWEDM24/12DSEControl—
0ChIRQFPFAFUF0000Control—
0DhVRT0000000Control—
Bank 1, 48h10 CenturyCenturyCentury00–63
Bank 1, 49h10 DateDateDate Alarm01–1F
MSBLSB
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0UIPDV2DV1DV0RS3RS2RS1RS0
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
Register A (0Ah)
Bits 3 to 0: Rate Selector Bits (RS3 to RS0). These four rate-selection bits select one of the 13 taps on the
15-stage divider or disable the divider output. The tap
selected can be used to generate an output square wave
(SQW pin) and/or a periodic interrupt. The user can do
one of the following:
1) Enable the interrupt with the PIE bit;
2) Enable the SQW output pin with the SQWE or E32k
bits;
3) Enable both at the same time and the same rate; or
4) Enable neither.
Table 4 lists the periodic interrupt rates and the square-
wave frequencies that can be chosen with the RS bits.
*RS3 to RS0 determine periodic interrupt rates as listed for E32K = 0.
Table 4. Periodic Interrupt Rate and Square-Wave Output Frequency
EXT REG BSELECT BITS REGISTER AtPI PERIODIC INTERRUPT
RATESQW OUTPUT FREQUENCYE32KRS3RS2RS1RS00000NoneNone00013.90625ms256Hz00107.8125ms128Hz0011122.070Fs8.192kHz0100244.141Fs4.096kHz0101488.281Fs2.048kHz0110976.5625Fs1.024kHz01111.953125ms512Hz10003.90625ms256Hz10017.8125ms128Hz101015.625ms64Hz101131.25ms32Hz110062.5ms16Hz1101125ms8Hz1110250ms4Hz1111500ms2HzXXXX*32.768kHz
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
Bit 7: SET. When the SET bit is 0, the update transfer functions normally by advancing the counts once per sec-
ond. When the SET bit is written to 1, any update transfer
is inhibited, and the program can initialize the time and
calendar bytes without an update occurring in the midst
of initializing. Read cycles can be executed in a similar
manner. SET is a read/write bit and is not affected by any
internal functions of the DS17x85.
Bit 6: Periodic Interrupt Enable (PIE). This bit is a read/write bit that allows the periodic interrupt flag (PF) bit in
Register C to drive the IRQ pin low. When PIE is set to 1,
periodic interrupts are generated by driving the IRQ pin low
at a rate specified by the RS3–RS0 bits of Register A. A 0
in the PIE bit blocks the IRQ output from being driven by
a periodic interrupt, but the PF bit is still set at the periodic
rate. PIE is not modified by any internal DS17x85 functions.
Bit 5: Alarm Interrupt Enable (AIE). This bit is a read/write bit that, when set to 1, permits the alarm flag (AF)
bit in Register C to assert IRQ. An alarm interrupt occurs
for each second that the three time bytes equal the three alarm bytes, including a don’t care alarm code of binary
11XXXXXX. When the AIE bit is set to 0, the AF bit does
not initiate the IRQ signal. The internal functions of the
DS17x285/87 do not affect the AIE bit.
Bit 4: Update-Ended Interrupt Enable (UIE). This bit is a read/write bit that enables the update-end flag (UF) bit
in Register C to assert IRQ. The SET bit going high clears
the UIE bit.
Bit 3: Square-Wave Enable (SQWE). When this bit is set to 1 and E32k = 0, a square-wave signal at the frequency
set by RS3–RS0 is driven out on the SQW pin. When the
SQWE bit is set to 0 and E32k = 0, the SQW pin is held
low. SQWE is a read/write bit. SQWE is set to 1 when
VCC is powered up.
Bit 2: Data Mode (DM). This bit indicates whether time and calendar information is in binary or BCD format. The
program sets the DM bit to the appropriate format and can
be read as required. This bit is not modified by internal
functions. A 1 in DM signifies binary data, while a 0 in DM
specifies binary-coded decimal (BCD) data.
Bit 1: 24/12 Control (24/12). This bit establishes the for-mat of the hours byte. A 1 indicates the 24-hour mode and
a 0 indicates the 12-hour mode. This bit is read/write and
is not affected by internal functions.
Bit 0: Daylight Saving Enable (DSE). This bit is a read/write bit that enables two daylight saving adjustments
when DSE is set to 1. On the first Sunday in April, the
time increments from 1:59:59AM to 3:00:00AM. On
the last Sunday in October when the time first reaches
1:59:59AM, it changes to 1:00:00AM. When DSE is
enabled, the internal logic tests for the first/last Sunday
condition at midnight. If the DSE bit is not set when the
test occurs, the daylight saving function does not operate
correctly. These adjustments do not occur when the DSE
bit is zero. This bit is not affected by internal functions.
MSBLSB
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0SETPIEAIEUIESQWEDM24/12DSE
DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
Register B (0Bh)
