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3.3 and 5.0 Volt MicroMonitor
FEATURESHolds microprocessor in check during power
transientsAutomatically restarts microprocessor afterpower failureMonitors pushbutton for external overrideAccurate 5%, 10% or 20% resets for 3.3V
systems and 5% or 10% resets for 5.0V
systemsEliminates the need for discrete components20% tolerance compatible with 3.0V systemsPin compatible with the MAXIM
MAX707/MAX708 in 8-pin DIP, 8-pin SOIC
packages8-pin DIP, 8-pin and μ-SOP SOIC and 8-pin
μ-SOP packages availableIndustrial temperature range -40°C to +85°C
PIN ASSIGNMENTSee Mech. Drawings Section
DS1707 and DS1708_R/S/T
PIN DESCRIPTIONPBRST- Pushbutton Reset InputVCC - Power Supply
GND - Ground
IN - Input
NMI - Non-maskable Interrupt
NC - No Connect
RST - Active Low Reset Output
RST - Active High Reset Output
DESCRIPTIONThe DS1707/DS1708 3.3- or 5.0-Volt MicroMonitor monitors three vital conditions for a microprocessor:
power supply, voltage sense, and external override. A precision temperature-compensated reference andcomparator circuit monitor the status of VCC at the device and at an upstream point for maximum
protection. When the sense input detects an out-of-tolerance condition a non-maskable interrupt is
generated. As the voltage at the device degrades an internal power fail signal is generated which forces
DS1707/DS1708
3.3 and 5.0-Volt MicroMonitor8-Pin DIP (300-mil)
PBRST
VCC
GND
RST
RST
NMI
8-Pin μ-SOP (118-mil)
RST
RST
PBRST
VCC
NMI
GND
8-Pin SOIC (150-mil)
PBRST
VCC
GND
RST
RST
NMI
DS1707/DS1708
The third function the DS1707/DS1708 performs is pushbutton reset control. The DS1707/DS1708
debounces the pushbutton input and guarantees an active reset pulse width of 130 ms minimum.
OPERATION
Power MonitorThe DS1707/DS1708 detects out-of-tolerance power supply conditions and warns a processor-basedsystem of impending power failure. When VCC falls below the minimum VCC tolerance, a comparator
outputs the RST and RST signals. RST and RST are excellent control signals for a microprocessor, as
processing is stopped at the last possible moment of valid VCC. On power-up, RST and RST are kept
active for a minimum of 130 ms to allow the power supply and processor to stabilize.
Pushbutton ResetThe DS1707/DS1708 provides an input pin for direct connection to a pushbutton reset (see Figure 2). The
pushbutton reset input requires an active low signal. Internally, this input is debounced and timed such
that RST and RST signals of at least 130 ms minimum will be generated. The 130 ms delay commences
as the pushbutton reset input is released from the low level. The pushbutton can be initiated by connecting
the NMI output to the PBRST input as shown in Figure 3.
Non-Maskable InterruptThe DS1707/DS1708 generates a non-maskable interrupt (NMI) for early warning of a power failure. A
precision comparator monitors the voltage level at the IN pin relative to an on-chip reference generated
by an internal band gap. The IN pin is a high impedance input allowing for a user-defined sense point. An
external resistor voltage divider network (Figure 5) is used to interface with high voltage signals. This
sense point may be derived from a regulated supply or from a higher DC voltage level closer to the mainsystem power input. Since the IN trip point VTP is 1.25 volts, the proper values for R1 and R2 can be
determined by the equation as shown in Figure 5. Proper operation of the DS1707/DS1708 requires that
the voltage at the IN pin be limited to VCC. Therefore, the maximum allowable voltage at the supply being
monitored (VMAX) can also be derived as shown in Figure 5. A simple approach to solving the equation is
to select a value for R2 high enough to keep power consumption low, and solve for R1. The flexibility ofthe IN input pin allows for detection of power loss at the earliest point in a power supply system,
maximizing the amount of time for system shut-down between NMI and RST/RST.
When the supply being monitored decays to the voltage sense point, the DS1707/DS1708 pulses the NMI
output to the active state for a minimum 200 μs. The NMI power-fail detection circuitry also has built-in
hysteresis of 100 μV. The supply must be below the voltage sense point for approximately 5 μs before a
low NMI will be generated. In this way, power supply noise is removed from the monitoring function,
preventing false interrupts. During a power-up, any detected IN pin levels below VTP by the comparator
are disabled from generating an interrupt until VCC rises to VCCTP. As a result, any potential NMI pulse
will not be initiated until VCC reaches VCCTP.
Connecting NMI to PBRST would allow the non-maskable interrupt to generate an automatic reset when
an out-of-tolerance condition occurred in a monitored supply. An example is shown in Figure 3.
DS1707/DS1708
MICROMONITOR BLOCK DIAGRAM Figure 1
PUSHBUTTON RESET Figure 2
PUSHBUTTON RESET CONTROLLED BY NMI Figure 3
DS1707/DS1708
TIMING DIAGRAM: PUSHBUTTON RESET Figure 4
NON-MASKABLE INTERRUPT CIRCUIT EXAMPLE Figure 5VSENSE = R2VMAX =
Example:VSENSE = 4.70V at the trip point
VCC = 3.3V
10 k� = R2
Therefore: 25.1
4.70 = R1 = 27.6 k�
DS1707/DS1708
TIMING DIAGRAM: NON-MASKABLE INTERRUPT Figure 6
TIMING DIAGRAM: POWER-DOWN Figure 7
DS1707/DS1708
TIMING DIAGRAM: POWER UP Figure 8
