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DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
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DS1705ESA-DS1705ESA/T&R-DS1706EPA-DS1706ESA-DS1706ESA/T&R-DS1706LEPA+-DS1706LESA+-DS1706REUA+-DS1706SESA-DS1706SESA+-DS1706TESA-DS1706TESA+-DS1706TEUA
3.3V and 5.0V MicroMonitor
FEATURESHalts and restarts an out-of-control
microprocessorHolds microprocessor in check during powertransientsAutomatically restarts microprocessor after
power failureMonitors pushbutton for external overrideAccurate 5%, 10% or 20% resets for 3.3Vsystems and 5% or 10% resets for 5.0V
systemsEliminates the need for discrete components3.3V 20% tolerance for use with 3.0V
systemsPin-compatible with the MAXIM
MAX705/MAX706 in 8-pin DIP, 8-pin SOIC,
and μ-SOP8-pin DIP, 8-pin SOIC and 8-pin μ-SOPpackagesIndustrial temperature range -40°C to +85°C
PIN ASSIGNMENTDS1705 and DS1706_R/S/T
(*DS1706L and DS1706P)
PIN DESCRIPTIONPBRST- Pushbutton Reset Input
VCC - Power Supply
GND - Ground
IN - Input
NMI - Non-maskable Interrupt - Strobe Input
RST - Active Low Reset Output*RST - Active High Reset Output
(DS1706P and DS1706L only)
WDS - Watchdog Status Output
DESCRIPTIONThe DS1705/DS1706 3.3- or 5.0-Volt MicroMonitor monitors three vital conditions for a microprocessor:
power supply, software execution, and external override. A precision temperature compensated reference
and comparator circuit monitor the status of VCC at the device and at an upstream point for maximum
DS1705/DS1706
3.3 and 5.0 Volt MicroMonitor8-Pin μ-SOP (118-mil)
See Mech. Drawings Section
RST(*RST)
WDS
PBRST
VCC
NMI
GND
8-Pin DIP (300 -mil)
PBRST
VCC
GND
WDS
RST
NMI
8-Pin SOIC (150-mil)
PBRST
VCC
GND
WDS
RST(*RST)
NMI
DS1705/DS1706
the reset to an active state. When VCC returns to an in-tolerance condition, the reset signal is kept in the
active state for a minimum of 130 ms to allow the power supply and processor to stabilize.
The second function the DS1705/DS1706 performs is pushbutton reset control. The DS1705/DS1706
debounces the pushbutton input and guarantees an active reset pulse width of 130 ms minimum.
The third function is a watchdog timer. The DS1705/DS1706 has an internal timer that forces the WDO
signal to the active state if the strobe input is not driven low prior to time-out.
OPERATION
Power MonitorThe DS1705/DS1706 detects out-of-tolerance power supply conditions and warns a processor-basedsystem of impending power failure. When VCC falls below the minimum VCC tolerance, a comparator
outputs the RST (or RST) signal. RST (or RST) is an excellent control signal for a microprocessor, as
processing is stopped at the last possible moment of valid VCC. On power-up, RST (or RST) are kept
active for a minimum of 130 ms to allow the power supply and processor to stabilize.
Pushbutton ResetThe DS1705/DS1706 provides an input pin for direct connection to a pushbutton reset (see Figure 2). The
pushbutton reset input requires an active low signal. Internally, this input is debounced and timed such
that a RST (or RST) signal of at least 130 ms minimum will be generated. The 130 ms delay commences
as the pushbutton reset input is released from the low level. The pushbutton can be initiated by connecting
the WDS or NMI outputs to the PBRST input as shown in Figure 3.
Non-Maskable InterruptThe DS1705/DS1706 generates a non-maskable interrupt (NMI) for early warning of a power failure. A
precision comparator monitors the voltage level at the IN pin relative to an on-chip reference generatedby an internal band gap. The IN pin is a high impedance input allowing for a user-defined sense point. An
external resistor voltage divider network (Figure 5) is used to interface with high voltage signals. This
sense point may be derived from a regulated supply or from a higher DC voltage level closer to the main
system power input. Since the IN trip point VTP is 1.25 volts, the proper values for R1 and R2 can be
determined by the equation as shown in Figure 5. Proper operation of the DS1705/DS1706 requires thatthe voltage at the IN pin be limited to VCC. Therefore, the maximum allowable voltage at the supply being
monitored (VMAX) can also be derived as shown in Figure 5. A simple approach to solving the equation is
to select a value for R2 high enough to keep power consumption low, and solve for R1. The flexibility of
the IN input pin allows for detection of power loss at the earliest point in a power supply system,
maximizing the amount of time for system shutdown between NMI and RST (or RST).
When the supply being monitored decays to the voltage sense point, the DS1705/DS1706 pulses the NMI
output to the active state for a minimum 200 μs. The NMI power-fail detection circuitry also has built-in
hysteresis of 100 μV. The supply must be below the voltage sense point for approximately 5 μs before a
low NMI will be generated. In this way, power supply noise is removed from the monitoring function,preventing false interrupts. During a power-up, any detected IN pin levels below VTP by the comparator
are disabled from generating an interrupt until VCC rises to VCCTP. As a result, any potential NMI pulse
will not be initiated until VCC reaches VCCTP.
DS1705/DS1706
Watchdog TimerThe watchdog timer function forces WDS signals active when the ST input is not clocked within the 1
second time-out period. Time-out of the watchdog starts when RST (or RST) becomes inactive. If a high-
to-low transition occurs on the ST input pin prior to time-out, the watchdog timer is reset and begins to
time out again. If the watchdog timer is allowed to time out, the WDS signal is driven active (low) for a
minimum of 130 ms. The ST input can be derived from many microprocessor outputs. The typical signalsused are the microprocessors address signals, data signals, or control signals. When the microprocessor
functions normally, these signals would, as a matter of routine, cause the watchdog to be reset prior to
time-out. To guarantee that the watchdog timer does not time out, a high-to-low transition must occur at
or less than the minimum watchdog time-out of 1 second. A typical circuit example is shown in Figure 6.
MICROMONITOR BLOCK DIAGRAM Figure 1
PUSH-BUTTON RESET Figure 2
DS1705/DS1706
PUSH-BUTTON RESET CONTROLLED BY NMI AND WDS Figure 3
TIMING DIAGRAM: PUSHBUTTON RESET Figure 4
NON-MASKABLE INTERRUPT CIRCUIT EXAMPLE Figure 5VSENSE = R2VMAX =
Example:VSENSE = 4.50V at the trip point
VCC = 3.3V
10 k� = R2
Therefore: 25.1
DS1705/DS1706
WATCHDOG TIMER Figure 6
TIMING DIAGRAM: STROBE INPUT Figure 7
TIMING DIAGRAM: NON-MASKABLE INTERRUPT Figure 8
DS1705/DS1706
TIMING DIAGRAM: POWER-DOWN Figure 9
