DS1689S ,3-Volt/5-Volt Serialized Real-Time Clock with NV RAM ControlPIN DESCRIPTION RAM clear inputX1 - Crystal Input Century registerX2 - Crystal Output 32 kHz out ..
DS1691 ,3 Volt/5 Volt serialized real time clock with NV RAM controlfeatures includinga silicon serial number, power on/off control circuitry, 114 bytes of user NV SRA ..
DS1691AJ/883 ,RS-422/RS-423 Line Drivers With TRI-STATE OutputsFeaturesn Dual RS-422 line driver with mode pin low, or quadThe DS1691A/DS3691 are low power Schott ..
DS1691AJ/883 ,RS-422/RS-423 Line Drivers With TRI-STATE OutputsFeaturesn Dual RS-422 line driver with mode pin low, or quadThe DS1691A/DS3691 are low power Schott ..
DS1692J ,TRI-STATE Differential Line DriversElectrical CharacteristicsV ≤ 0V (Notes 3, 4)EESymbol Parameter Conditions Min Typ Max UnitsV High ..
DS1693 ,3 Volt/5 Volt Serialized Real Time Clock with NV RAM ControlFeatures: Century Register +3V or +5V Operation 32kHz Output for Power Management 64-Bit Si ..
DV74AC244 , Octal buffer/Line Driver with 3-state Outputs
DVIULC6-2P6 ,Ultra Low capacitance 2 lines ESD protectionApplicationsBenefits■ DVI ports up to 1.65 Gb/s■ ESD standards compliance guaranteed at ■ IEEE 1394 ..
DVIULC6-4SC6 ,Ultralow capacitance ESD protectionFeatures■ 4-line ESD protection (IEC 61000-4-2)■ Protects V when applicableBUS■ Ultralow capacitanc ..
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DS1689S
3-Volt/5-Volt Serialized Real-Time Clock with NV RAM Control
FEATURESIncorporates industry standard DS1287 PC clock
plus enhanced features:+3- or +5V operation64-bit silicon serial number64-bit customer specific ROM or additional
serial number availablePower control circuitry supports system
power-on from date/time alarm or key closureAutomatic battery backup and writeprotection to external SRAMCrystal select bit allows RTC to operate with
6 pF or 12.5 pF crystal114 bytes user NV RAMAuxiliary battery inputRAM clear inputCentury register32 kHz output for power management32-bit VCC powered elapsed time counter32-bit VBAT powered elapsed time counter16-bit power cycle counterCompatible with existing BIOS for original
DS1287 functionsAvailable as IC (DS1689) or standalone
module with embedded battery and crystal(DS1693)IC is available in industrial temperature
versionTimekeeping algorithm includes leap year
compensation valid up to 2100
ORDERING INFORMATION
PART # DESCRIPTIONDS1689S RTC IC, 28-pin SOICDS1689SNRTC IC, 28-pin SOIC IND
DS1693 RTC Module; 28-pin DIP
PIN ASSIGNMENT
PIN DESCRIPTIONX1 - Crystal InputX2 - Crystal Output
RCLR - RAM Clear Input
AD0-AD7 - Mux’ed Address/Data Bus
PWR - Power-on Interrupt Output
(Open drain) - Kickstart Input - RTC Chip Select Input
ALE - RTC Address Strobe - RTC Write Data Strobe - RTC Read Data StrobeVCCO - RAM Power Supply Output
IRQ - Interrupt Request Output
(Open drain)
SQW - Square Wave Output
VCCI- +3- or +5V Main SupplyGND - Ground
VBAT - Battery + Supply
VBAUX - Auxiliary Battery Supply
PSEL - +3- or +5V Power Select
CEI - RAM Chip Enable In
CEO - RAM Chip Enable Out
DS1689/DS1693
3-Volt/5-Volt Serialized Real-Time Clock
with NV RAM ControlVBAUX
DS1689S 28-Pin SOIC(330-mil)X2
AD0
AD2AD3
AD4
AD5
AD6
AD7
GND
PWR
RCLR
AD1
GND
DS1693 28-Pin Encapsulated Package(740-mil)
AD0
AD2
AD3
AD4
AD5
AD6
AD7
GND
PWR
CEI
VCCO
SQWNC
IRQ
PSEL
RCLR
AD1
VBAUX
CEOVCCI
DS1689/DS1693
DESCRIPTIONThe DS1689/DS1693 is a real time clock (RTC) designed as a successor to the industry standard DS1285,
DS1385, DS1485, and DS1585 PC real time clocks. This device provides the industry standard DS1285
clock function with the new feature of either +3.0- or +5.0 volt operation and automatic backup and write
protection to an external SRAM. The DS1689 also incorporates a number of enhanced features including
a silicon serial number, power-on/off control circuitry, and 114 bytes of user NVSRAM, power-onelapsed timer, and power cycle counter.
Each DS1689/DS1693 is individually manufactured with a unique 64-bit serial number as well as an
additional 64-bit customer specific ROM or serial number. The serial number is programmed and tested
at Dallas to insure that no two devices are alike. The serial number can be used to electronically identify asystem for purposes such as establishment of a network node address or for maintenance tracking. Blocks
of available numbers from Dallas Semiconductor can be reserved by the customer.
The serialized RTCs also incorporate power control circuitry, which allows the system to be powered on
via an external stimulus, such as a keyboard or by a time and date (wake-up) alarm. The PWR output pin
can be triggered by one or either of these events, and can be used to turn on an external power supply.
The PWR pin is under software control, so that when a task is complete, the system power can then beshut down.
The DS1689/DS1693 incorporates a power-on elapsed time counter, a power-on cycle counter, and a
battery powered continuous counter. These three counters provide valuable information for maintenance
and warranty requirements.
Automatic backup and write protection for an external SRAM is provided through the VCCO and CEO
pins. The lithium energy source used to permanently power the real time clock is also used to retain RAM
data in the absence of VCC power through the VCCO pin. The chip enable output to RAM (CEO) is
controlled during power transients to prevent data corruption.
The DS1689 is a clock/calendar chip with the features described above. An external crystal and battery
are the only components required to maintain time-of-day and memory status in the absence of power.The DS1693 incorporates the DS1689 chip, a 32.768 kHz crystal, and a lithium battery in a complete,
self-contained timekeeping module. The entire unit is fully tested at Dallas Semiconductor such that a
minimum of 10 years of timekeeping and data retention in the absence of VCC is guaranteed.
OPERATIONThe block diagram in Figure 1 shows the pin connections with the major internal functions of theDS1689/DS1693. The following paragraphs describe the function of each pin.
SIGNAL DESCRIPTIONS
GND, VCCI - DC power is provided to the device on these pins. VCCI is the +3-volt or +5-volt input.Five-volt operation is selected when the PSEL pin is at a logic 1. If PSEL is floated or at a logic 0, the
device will be in auto-sense mode and will determine the correct operating voltage based on the VCCIvoltage level.
PSEL (Power Select Input) - This pin selects whether 3-volt operation or 5-volt operation will be used.
DS1689/DS1693
VCCO (External SRAM Power Supply Output) - This pin will be internally connected to VCCI when
VCCI is within nominal limits. However, during power fail, VCCO will be internally connected to the VBAT
or VBAUX (whichever is larger). For 5-volt operation, switch over from VCCI to the backup supply occurs
when VCCI drops below the larger of VBAT and VBAUX. For 3-volt operation, switch over from VCCI to thebackup supply occurs at VPF if VPF is less than VBAT and VBAUX. If VPF is greater than VBAT and VBAUX,
the switch from VCCI to the backup supply occurs when VCCI drops below the larger of VBAT and VBAUX.
DS1689/DS1693 BLOCK DIAGRAM Figure 1
SQW (Square Wave Output) - The SQW pin can output a signal from one of 13 taps provided by the 15internal divider stages of the real time clock. The frequency of the SQW pin can be changed by
programming Register A as shown in Table 2. The SQW signal can be turned on and off using the SQWE
bit in Register B. A 32 kHz SQW signal is output when SQWE=1, the Enable 32 kHz (E32K) bit inextended register 04BH is a logic 1, and VCC is above VPF. A 32 kHz square wave is also available when
DS1689/DS1693
AD0-AD7 (Multiplexed Bi-directional Address/Data Bus) - Multiplexed buses save pins because
address information and data information time-share the same signal paths. The addresses are present
during the first portion of the bus cycle and the same pins and signal paths are used for data in the second
portion of the cycle. Address/data multiplexing does not slow the access time of the DS1689 since the buschange from address to data occurs during the internal RAM access time. Addresses must be valid prior
to the latter portion of ALE, at which time the DS1689/DS1693 latches the address. Valid write data must
be present and held stable during the latter portion of the WR pulse. In a read cycle the DS1689/DS1693
outputs 8 bits of data during the latter portion of the RD pulse. The read cycle is terminated and the bus
returns to a high impedance state as RD transitions high. The address/data bus also serves as a bi-directional data path for the external extended RAM.
ALE (RTC Address Strobe Input; active high) - A pulse on the address strobe pin serves to
demultiplex the bus. The falling edge of ALE causes the RTC address to be latched within theDS1689/DS1693.
(RTC Read Input; active low) - RD identifies the time period when the DS1689/DS1693 drives the
bus with RTC read data. The RD signal is an enable signal for the output buffers of the clock.
(RTC Write Input; active low) - The WR signal is an active low signal. The WR signal defines
the time period during which data is written to the addressed register.
(RTC Chip Select Input; active low) - The Chip Select signal must be asserted low during a bus
cycle for the RTC portion of the DS1689/DS1693 to be accessed. CS must be kept in the active state
during RD and WR timing. Bus cycles, which take place with ALE asserted but without asserting, CS
will latch addresses. However, no data transfer will occur.
IRQ (Interrupt Request Output; open drain, active low) - The IRQ pin is an active low output of the
DS1689/DS1693 that can be tied to the interrupt input of a processor. The IRQ output remains low as
long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set. To
clear the IRQ pin, the application software must clear all enabled flag bits contributing to IRQ’s active
state.
When no interrupt conditions are present, the IRQ level is in the high impedance state. Multiple
interrupting devices can be connected to an IRQ bus. The IRQ pin is an open drain output and requires an
external pull-up resistor.
CEI (RAM Chip Enable Input; active low) - CEI should be driven low to enable the external RAM.
CEO (RAM Chip Enable Output; active low) - When power is valid, CEO will equal CEI. When
power is not valid, CEO will be driven high regardless of CEI.
PWR (Power-on Output; open drain, active low) - The PWR pin is intended for use as an on/off
control for the system power. With VCC voltage removed from the DS1689/DS1693, PWR may be
DS1689/DS1693
(Kickstart Input; active low) - When VCC is removed from the DS1689/DS1693, the system can bepowered on in response to an active low transition on the KS pin, as might be generated from a keyclosure. VBAUX must be present and Auxiliary Battery Enable bit (ABE) must be set to 1 if the kickstart
function is used, and the KS pin must be pulled up to the VBAUX supply. While VCC is applied, the KS pin
can be used as an interrupt input.
RCLR (RAM Clear Input; active low) - If enabled by software, taking RCLR low will result in the
clearing of the 114 bytes of user RAM. When enabled, RCLR can be activated whether or not VCC is
present.
VBAUX - Auxiliary battery input required for kickstart and wake-up features. This input also supports
clock/calendar and External NVRAM if VBAT is at lower voltage or is not present. A standard +3-volt
lithium cell or other energy source can be used. Battery voltage must be held between +2.5 and +3.7 volts
for proper operation. If VBAUX is not going to be used it should be grounded and auxiliary battery enable
bit bank 1, register 4BH, should=0.
DS1689 ONLY
X1, X2 - Connections for a standard 32.768 kHz quartz crystal. For greatest accuracy, the DS1689 mustbe used with a crystal that has a specified load capacitance of either 6 pF or 12.5 pF. The Crystal Select
(CS) bit in Extended Control Register 4B is used to select operation with a 6 pF or 12.5 pF crystal. The
crystal is attached directly to the X1 and X2 pins. There is no need for external capacitors or resistors.Note: X1 and X2 are very high impedance nodes. It is recommended that they and the crystal by guard-
ringed with ground and that high frequency signals be kept away from the crystal area.
For more information on crystal selection and crystal layout considerations, please consult Application
Note 58, “Crystal Considerations with Dallas Real Time Clocks.” The DS1689 can also be driven by anexternal 32.768 kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator
signal and the X2 pin is floated.
VBAT - Battery input for any standard 3-Volt lithium cell or other energy source. Battery voltage must beheld between 2.5 and 3.7 volts for proper operation.
POWER-DOWN/POWER-UP CONSIDERATIONSThe real-time clock function will continue to operate and all of the RAM, time, calendar, and alarm
memory locations remain nonvolatile regardless of the level of the VCCI input. When VCCI is applied to
the DS1689/DS1693 and reaches a level of greater than VPF (power fail trip point), the device becomes
accessible after tREC, provided that the oscillator is running and the oscillator countdown chain is not inreset (see Register A). This time period allows the system to stabilize after power is applied.
When PSEL is floating or logic 0, the DS1689 is in autosense mode and 3-volt or 5-volt operation is
determined based on the voltage on VCCI. Selection of 5-volt operation is automatically invoked when
VCCI rises above 4.5 volts for a minimum of tREC. However, 3-volt operation is automatically selected ifVCCI does not rise above the level of 4.25 volts. Selection of the power supply input levels requires
150 ms of input stability before operation can commence.
DS1689/DS1693
When 5-volt operation is selected, the device is fully accessible and data can be written and read only
when VCCI is greater than 4.5 volts. When VCCI is below 4.5 volts, read and writes are inhibited. However,
the timekeeping function continues unaffected by the lower input voltage. As VCC falls below the greater
of VBAT and VBAUX, the RAM and timekeeper are switched over to a lithium battery connected either tothe VBAT pin or VBAUX pin.
When 3-volt operation is selected and applied within normal limits, the device is fully accessible and data
can be written or read. When VCCI falls below VPF, access to the device is inhibited. If VPF is less than
VBAT and VBAUX, the power supply is switched from VCCI to the backup supply (the greater of VBAT andVBAUX) when VCCI drops below VPF. If VPF is greater than VBAT and VBAUX, the power supply is switched
from VCCI to the backup supply when VCCI drops below the larger of VBAT and VBAUX.
When VCC falls below VPF, the chip is write-protected. With the possible exception of the KS, PWR, and
SQW pins, all inputs are ignored and all outputs are in a high impedance state.
RTC ADDRESS MAPThe address map for the RTC registers of the DS1689/DS1693 is shown in Figure 2. The address mapconsists of the 14-clock/calendar registers. Ten registers contain the time, calendar, and alarm data, and
four bytes are used for control and status. All registers can be directly written or read except for the
following:
1. Registers C and D are read-only.2. Bit 7 of Register A is read-only.
3. The high order bit of the seconds byte is read-only.
DS1689 REAL TIME CLOCK ADDRESS MAP Figure 2
DS1689/DS1693
TIME, CALENDAR AND ALARM LOCATIONSThe time and calendar information is obtained by reading the appropriate register bytes shown in Table 1.
The time, calendar, and alarm are set or initialized by writing the appropriate register bytes. The contents
of the time, calendar, and alarm registers can be either Binary or Binary-Coded Decimal (BCD) format.
Table 1 shows the binary and BCD formats of the twelve time, calendar, and alarm locations that reside in
both bank 0 and in bank 1, plus the two extended registers that reside in bank 1 only (bank 0 and bank 1switching will be explained later in this text).
Before writing the internal time, calendar, and alarm registers, the SET bit in Register B should be written
to a logic 1 to prevent updates from occurring while access is being attempted. Also at this time, the data
format (binary or BCD) should be set via the data mode bit (DM) of Register B. All time, calendar, andalarm registers must use the same data mode. The set bit in Register B should be cleared after the data
mode bit has been written to allow the real-time clock to update the time and calendar bytes.
Once initialized, the real-time clock makes all updates in the selected mode. The data mode cannot be
changed without reinitializing the 10 data bytes. The 24/12 bit cannot be changed without reinitializingthe hour locations. When the 12-hour format is selected, the high order bit of the hours byte represents
PM when it is a logic 1. The time, calendar, and alarm bytes are always accessible because they are
double-buffered. Once per second the 10 bytes are advanced by one second and checked for an alarm
condition. If a read of the time and calendar data occurs during an update, a problem exists where
seconds, minutes, hours, etc. may not correlate. The probability of reading incorrect time and calendardata is low. Several methods of avoiding any possible incorrect time and calendar reads are covered later
in this text.
The 4 alarm bytes can be used in two ways. First, when the alarm time is written in the appropriate hours,
minutes, and seconds alarm locations, the alarm interrupt is initiated at the specified time each day if thealarm enable bit is high. The second use condition is to insert a “don’t care” state in one or more of the 4
alarm bytes. The “don’t care” code is any hexadecimal value from C0 to FF. The 2 most significant bits
of each byte set the “don’t care” condition when at logic 1. An alarm will be generated each hour when
the “don’t care” bits are set in the hours byte. Similarly, an alarm is generated every minute with “don’t
care” codes in the hours and minute alarm bytes. The “don’t care” codes in all 3-alarm bytes create aninterrupt every second. The 3 alarm bytes may be used in conjunction with the date alarm as described in
the Wakeup/Kickstart section. The century counter will be discussed later in this text.
DS1689/DS1693
TIME, CALENDAR AND ALARM DATA MODES Table 1
CONTROL REGISTERSThe four control registers; A, B, C, and D reside in both bank 0 and bank 1. These registers are accessible
at all times, even during the update cycle.
NONVOLATILE RAM - RTCThe 114 general-purpose nonvolatile RAM bytes are not dedicated to any special function within theDS1689/DS1693. They can be used by the application program as nonvolatile memory and are fully
available during the update cycle. This memory is directly accessible when bank 0 is selected.
INTERRUPT CONTROLThe DS1689/DS1693 includes six separate, fully automatic sources of interrupt for a processor:
1. Alarm interrupt
2. Periodic interrupt3. Update-ended interrupt
4. Wake-up interrupt
5. Kickstart interrupt
6. RAM clear interrupt
The conditions, which generate each of these independent interrupt conditions, are described in greater
detail elsewhere in this data sheet. This section describes the overall control of the interrupts.
DS1689/DS1693
The application software can select which interrupts, if any are to be used. There are a total of 6 bits
including 3 bits in Register B and 3 bits in Extended Register B which enable the interrupts. The extended
register locations are described later. Writing a logic 1 to an interrupt enable bit permits that interrupt to
be initiated when the event occurs. A logic 0 in the interrupt enable bit prohibits the IRQ. pin from being
asserted from that interrupt condition. If an interrupt flag is already set when an interrupt is enabled, IRQ
will immediately be set at an active level, even though the event initiating the interrupt condition mayhave occurred much earlier. As a result, there are cases where the software should clear these earlier
generated interrupts before first enabling new interrupts.
When an interrupt event occurs, the relating flag bit is set to a logic 1 in Register C or in Extended
Register A. These flag bits are set regardless of the setting of the corresponding enable bit located eitherin Register B or in Extended Register B. The flag bits can be used in a polling mode without enabling the
corresponding enable bits.
However, care should be taken when using the flag bits of Register C as they are automatically cleared to
0 immediately after they are read. Double latching is implemented on these bits so that bits which are setremain stable throughout the read cycle. All bits which were set are cleared when read and new interrupts
which are pending during the read cycle are held until after the cycle is completed. One, 2, or 3 bits can
be set when reading Register C. Each utilized flag bit should be examined when read to ensure that no
interrupts are lost.
The flag bits in Extended Register A are not automatically cleared following a read. Instead, each flag bit
can be cleared to 0 only by writing 0 to that bit.
When using the flag bits with fully enabled interrupts, the IRQ line will be driven low when an interrupt
flag bit is set and its corresponding enable bit is also set. IRQ will be held low as long as at least one of
the six possible interrupt sources has it s flag and enable bits both set. The IRQF bit in Register C is a 1
whenever the IRQ pin is being driven low as a result of one of the six possible active sources. Therefore,
determination that the DS1689/DS1693 initiated an interrupt is accomplished by reading Register C andfinding IRQF=1. IRQF will remain set until all enabled interrupt flag bits are cleared to 0.
SQUARE WAVE OUTPUT SELECTIONThe SQW pin can be programmed to output a variety of frequencies divided down from the 32.768 kHz
crystal tied to X1 and X2. The square wave output is enabled and disabled via the SQWE bit in Register
B. If the square wave is enabled (SQWE=1), then the output frequency will be determined by the settings
of the E32K bit in Extended Register B and by the RS3-0 bits in Register A. If the E32K = 1, then a32.768 kHz square wave will be output on the SQW pin regardless of the settings of RS3-0.
If E32K = 0, then the square wave output frequency is determined by the RS3-0 bits. These bits control a
1-of-15 decoder, which selects one of 13 taps that divide the 32.768 kHz frequency. The RS3-0 bits
establish the SQW output frequency as shown in Table 2. In addition, RS3-0 bits control the periodicinterrupt selection as described below.
If SQWE1, E32K=1, and the Auxiliary Battery Enable bit (ABE, bank 1; register 04BH) is enabled, and
voltage is applied to VBAUX then the 32 kHz square wave output signal will be output on the SQW pin in
the absence of VCC. This facility is provided to clock external power management circuitry. If any of the
DS1689/DS1693
A pattern of 01X in the DV2, DV1, and DV0, bits respectively, will turn the oscillator on and enable the
countdown chain. Note that this is different than the DS1287, which required a pattern of 010 in these
bits. DV0 is now a “don’t care” because it is used for selection between register banks 0 and 1. A pattern
of 11X will turn the oscillator on, but the oscillator’s countdown chain will be held in reset, as it was inthe DS1287. Any other bit combination for DV2 and DV1 will keep the oscillator off.
PERIODIC INTERRUPT SELECTIONThe periodic interrupt will cause the IRQ pin to go to an active state from once every 500 ms to once
every 122 �s. This function is separate from the alarm interrupt which can be output from once per
second to once per day. The periodic interrupt rate is selected using the same RS3-0 bits in Register A
which select the square wave frequency (see Table 2). Changing the bits affects both the square wavefrequency and the periodic interrupt output. However, each function has a separate enable bit in Register
B. The SQWE bit controls the square wave output. Similarly, the periodic interrupt is enabled by the PIE
bit in Register B. The periodic interrupt can be used with software counters to measure inputs, create
output intervals, or await the next needed software function.
UPDATE CYCLEThe Serialized RTC executes an update cycle once per second regardless of the SET bit in Register B.When the SET bit in Register B is set to 1, the user copy of the double-buffered time, calendar, alarm and
elapsed time byte is frozen and will not update as the time increments. However, the time countdown
chain continues to update the internal copy of the buffer. This feature allows the time to maintain
accuracy independent of reading or writing the time, calendar, and alarm buffers and also guarantees that
time and calendar information is consistent. The update cycle also compares each alarm byte with thecorresponding time byte and issues an alarm if a match or if a “don’t care” code is present in all three
positions.
There are three methods that can handle access of the real-time clock that avoid any possibility of
accessing inconsistent time and calendar data. The first method uses the update-ended interrupt. Ifenabled, an interrupt occurs after every up date cycle that indicates that over 999 ms are available to read
valid time and date information. If this interrupt is used, the IRQF bit in Register C should be cleared
before leaving the interrupt routine.
A second method uses the update-in-progress bit (UIP) in Register A to determine if the update cycle is inprogress. The UIP bit will pulse once per second. After the UIP bit goes high, the update transfer occurs
244 �s later. If a low is read on the UIP bit, the user has at least 244 �s before the time/calendar data will
be changed. Therefore, the user should avoid interrupt service routines that would cause the time needed
to read valid time/calendar data to exceed 244 �s.
DS1689/DS1693
PERIODIC INTERRUPT RATE AND
SQUARE WAVE OUTPUT FREQUENCY Table 2*RS3-RS0 determine periodic interrupt rates as listed for E32K=0.
The third method uses a periodic interrupt to determine if an update cycle is in progress. The UIP bit in
Register A is set high between the setting of the PF bit in Register C (see Figure 3). Periodic interruptsthat occur at a rate of greater than tBUC allow valid time and date information to be reached at each
occurrence of the periodic interrupt. The reads should be complete within (tPI / 2+tBUC) to ensure that data
is not read during the update cycle.
UPDATE-ENDED AND PERIODIC INTERRUPT RELATIONSHIP Figure 3
DS1689/DS1693
REGISTER A
MSB LSB
UIP - The Update In Progress (UIP) bit is a status flag that can be monitored. When the UIP bit is a 1, theupdate transfer will soon occur. When UIP is a 0, the update transfer will not occur for at least 244 ms.
The time, calendar, and alarm information in RAM is fully available for access when the UIP bit is 0. TheUIP bit is read-only. Writing the SET bit in Register B to a one inhibits any update transfer and clears the
UIP status bit.
DV0, DV1, DV2 - These bits are defined as follows:DV2 = Countdown Chain
1 - resets countdown chain only if DV1=1
0 - countdown chain enabled
DV1 = Oscillator Enable
0 - oscillator off
1 - oscillator on
DV0 = Bank Select
0 - original bank
1 - extended registers
A pattern of 01X is the only combination of bits that will turn the oscillator on and allow the RTC to keep
time. A pattern of 11X will enable the oscillator but holds the countdown chain in reset. The next update
will occur at 500 ms after a pattern of 01X is written to DV2, DV1, and DV0.
RS3, RS2, RS1, RS0 - These four rate-selection bits select one of the 13 taps on the 15-stage divider ordisable the divider output. The tap selected can be used to generate an output square wave (SQW pin)
and/or a periodic interrupt. The user can do one of the following:
Enable the interrupt with the PIE bit;
Enable the SQW output pin with the SQWE bit;
Enable both at the same time and the same rate; or
Enable neither.
Table 2 lists the periodic interrupt rates and the square wave frequencies that can be chosen with the RSbits.
DS1689/DS1693
REGISTER B
MSB LSB
SET - When the SET bit is a 0, the update transfer functions normally by advancing the counts once persecond. When the SET bit is written to a 1, any update transfer is inhibited and the program can initialize
the time and calendar bytes without an update occurring in the midst of initializing. Read cycles can beexecuted in a similar manner. SET is a read/write bit that is not modified by internal functions of the
DS1689/DS1693.
PIE - The Periodic Interrupt Enable bit is a read/write bit which allows the Periodic Interrupt Flag (PF)bit in Register C to drive the IRQ pin low. When the PIE bit is set to 1, periodic interrupts are generated
by driving the IRQ pin low at a rate specified by the RS3-RS0 bits of Register A. A 0 in the PIE bit
blocks the IRQ output from being driven by a periodic interrupt, but the Periodic Flag (PF) bit is still set
at the periodic rate. PIE is not modified by any internal DS1689/DS1693 functions.
AIE - The Alarm Interrupt Enable (AIE) bit is a read/write bit which, when set to a 1, permits the AlarmFlag (AF) bit in register C to assert IRQ. An alarm interrupt occurs for each second that the 3 time bytes
equal the 3 alarm bytes including a don’t care alarm code of binary 11XXXXXX. When the AIE bit is set
to 0, the AF bit does not initiate the IRQ signal. The internal functions of the DS1689/DS1693 do not
affect the AIE bit.
UIE - The Update Ended Interrupt Enable (UIE) bit is a read/write that enables the Update End Flag (UF)bit in Register C to assert IRQ. The SET bit going high clears the UIE bit.
SQWE - When the Square Wave Enable (SQWE) bit is set to a 1, a square wave signal at the frequencyset by the rate-selection bits RS3 through RS0 and the E32K bit is driven out on the SQW pin. When the
SQWE bit is set to 0, the SQW pin is held low. SQWE is a read/write bit.
DM - The Data Mode (DM) bit indicates whether time and calendar information is in binary or BCD
format. The DM bit is set by the program to the appropriate format and can be read as required. This bit is
not modified by internal functions. A 1 in DM signifies binary data while a 0 in DM specifies Binary
Coded Decimal (BCD) data.
24/12 - The 24/12 control bit establishes the format of the hours byte. A 1 indicates the 24-hour mode anda 0 indicates the 12-hour mode. This bit is read/write.
DSE - The Daylight Savings Enable (DSE) bit is a read/write bit which enables two special updates whenDSE is set to 1. On the first Sunday in April the time increments from 1:59:59 am to 3:00:00 AM. On the
last Sunday in October when the time first reaches 1:59:59 AM it changes to 1:00:00 AM. These special
updates do not occur when the DSE bit is a 0. This bit is not affected by internal functions.
DS1689/DS1693
REGISTER C
MSB LSB
IRQF - The Interrupt Request Flag (IRQF) bit is set to a 1 when one or more of the following are true:PF = PIE = 1 WF = WIE = 1AF = AIE = 1 KF = KSE = 1
UF = UIE = 1 RF = RIE = 1
i.e., IRQF = (PF � PIE) + (AF � AIE) + (UF � UIE) + (WF � WIE) + (KF � KSE) + (RF � RIE)
Any time the IRQF bit is a one, the IRQ pin is driven low. Flag bits PF, AF, and UF are cleared after
Register C is read by the program.
PF - The Periodic Interrupt Flag (PF) is a read-only bit which is set to a 1 when an edge is detected on theselected tap of the divider chain. The RS3 through RS0 bits establish the periodic rate. PF is set to a 1
independent of the state of the PIE bit. When both PF and PIE are 1s, the IRQ signal is active and will set
the IRQF bit. The PF bit is cleared by a software read of Register C.
AF - A one in the Alarm Interrupt Flag (AF) bit indicates that the current time has matched the alarm
time. If the AIE bit is also a 1, the IRQ pin will go low and a one will appear in the IRQF bit. A read of
Register C will clear AF.
UF - The Update Ended Interrupt Flag (UF) bit is set after each update cycle. When the UIE bit is set to1, the one in UF causes the IRQF bit to be a 1, which will assert the IRQ pin. UF is cleared by reading
Register C.
BIT 0 THROUGH BIT 3 - These are unused bits of the status Register C. These bits always read 0 andcannot be written.
REGISTER D
MSB LSB
VRT - The Valid RAM and Time (VRT) bit indicates the condition of the battery connected to the VBATpin or the battery connected to VBAUX, whichever is at a higher voltage. This bit is not writable and should
always be a 1 when read. If a 0 is ever present, an exhausted lithium energy source is indicated and both
the contents of the RTC data and RAM data are questionable.
BIT 6 THROUGH BIT 0 - The remaining bits of Register D are not usable. They cannot be written and,when read, they will always read 0.
DS1689/DS1693
EXTENDED FUNCTIONSThe extended functions provided by the DS1689/DS1693 that are new to the RAMified RTC family are
accessed via a software controlled bank switching scheme, as illustrated in Figure 4. In bank 0, the
clock/calendar registers and 50 bytes of user RAM are in the same locations as for the DS1287. As aresult, existing routines implemented within BIOS, DOS, or application software packages can gain
access to the DS1689/DS1693 clock registers with no changes. Also in bank 0, an extra 64 bytes of RAM
are provided at addresses just above the original locations for a total of 114 directly addressable bytes of
user RAM.
When bank 1 is selected, the clock/calendar registers and the original 50 bytes of user RAM still appear
as bank 0. However, the Dallas registers which provide control and status for the extended functions willbe accessed in place of the additional 64 bytes of user RAM. The major extended functions controlled by
the Dallas registers are listed below:
1. Silicon Revision byte
2. Serial Number
3. 8-Byte Customer Specific ROM or Serial Number
4. Century counter5. Auxiliary Battery Control/Status
6. Wake-Up
7. Kickstart
8. RAM Clear Control/Status
9. VCC Powered Elapsed Time Counter10. VBAT Powered Elapsed Time Counter
11. Power-on Cycle Counter
The bank selection is controlled by the state of the DV0 bit in register A. To access bank 0 the DV0 bit
should be written to a 0. To access bank 1, DV0 should be written to a 1. Register locations designated asreserved in the bank 1 map are reserved for future use by Dallas Semiconductor. Bits in these locations
cannot be written and will return a 0 if read.
DS1689/DS1693
DS1689/DS1693 EXTENDED REGISTER BANK DEFINITION Figure 4
