DS1687-5+ ,3V/5V Real-Time Clockfeatures including a silicon serial number, power-on/off control circuitry, 242 bytes of user NVSRA ..
DS1689S ,3-Volt/5-Volt Serialized Real-Time Clock with NV RAM ControlPIN DESCRIPTION RAM clear inputX1 - Crystal Input Century registerX2 - Crystal Output 32 kHz out ..
DS1691 ,3 Volt/5 Volt serialized real time clock with NV RAM controlfeatures includinga silicon serial number, power on/off control circuitry, 114 bytes of user NV SRA ..
DS1691AJ/883 ,RS-422/RS-423 Line Drivers With TRI-STATE OutputsFeaturesn Dual RS-422 line driver with mode pin low, or quadThe DS1691A/DS3691 are low power Schott ..
DS1691AJ/883 ,RS-422/RS-423 Line Drivers With TRI-STATE OutputsFeaturesn Dual RS-422 line driver with mode pin low, or quadThe DS1691A/DS3691 are low power Schott ..
DS1692J ,TRI-STATE Differential Line DriversElectrical CharacteristicsV ≤ 0V (Notes 3, 4)EESymbol Parameter Conditions Min Typ Max UnitsV High ..
DV74AC244 , Octal buffer/Line Driver with 3-state Outputs
DVIULC6-2P6 ,Ultra Low capacitance 2 lines ESD protectionApplicationsBenefits■ DVI ports up to 1.65 Gb/s■ ESD standards compliance guaranteed at ■ IEEE 1394 ..
DVIULC6-4SC6 ,Ultralow capacitance ESD protectionFeatures■ 4-line ESD protection (IEC 61000-4-2)■ Protects V when applicableBUS■ Ultralow capacitanc ..
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DS1685E-3+-DS1685S-5+-DS1685SN-5+-DS1685SN-5+T&R-DS1687-3+-DS1687-3IND+-DS1687-5+
3V/5V Real-Time Clock
FEATURESIncorporates industry-standard DS1287 PC clock
plus enhanced features:Y2K-compliant+3 or +5V operation64-bit silicon serial numberPower-control circuitry supports system
power-on from date/time alarm or keyclosure32kHz output for power managementCrystal-select bit allows RTC to operate with
6pF or 12.5pF crystalSMI Recovery Stack242 bytes user NV RAMAuxiliary battery inputRAM clear inputCentury registerDate alarm registerCompatible with existing BIOS for original
DS1287 functionsAvailable as chip (DS1685) or standalone
module with embedded battery and crystal
(DS1687)
PIN ASSIGNMENT (Top View)Timekeeping algorithm includes leap-year
compensation valid up to 2100Underwriters Laboratory (UL) recognized
Package Dimension Informationhttp:///TechSupport/DallasPackInfo.htm
VCC
SQW
VBAUX
RCLR
N.C.
IRQ
PWR
N.C.
N.C.
AD0
AD1
AD2
AD3
AD4
AD5
AD6
DS1687 24-Pin Module PDIP (740mil)
AD7
GND
VCC
SQW
VBAUX
VBAT
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
DS1685 24-Pin DIP
DS1685S 24-Pin SO (300mil)
DS1685E 24-Pin TSSOP
AD7
GND
ALEX1PW
AD0
AD1AD2
AD3
AD4
AD5RD
GNDN.C.
GND
4 3 2 1 28 27 26
12 13 14 15 16 17 18AUX
DS1685/DS1687
3V/5V Real-Time Clock
DS1685/DS1687
ORDERING INFORMATION*An “N” located in the right-hand corner of the top of the package denotes an industrial device.
DS1685/DS1687
TYPICAL OPERATING CIRCUIT
DESCRIPTIONThe DS1685/DS1687 is a real-time clock (RTC) designed as a successor to the industry-standard
DS1285, DS1385, DS1485, and DS1585 PC RTCs. This device provides the industry-standard DS1285
clock function with either +3.0V or +5.0V operation. The DS1685 also incorporates a number of
enhanced features including a silicon serial number, power-on/off control circuitry, 242 bytes of user NV
SRAM, and 32.768kHz output for sustaining power management activities.
The DS1685/DS1687 power-control circuitry allows the system to be powered on by an external stimulus
such as a keyboard or by a time and date (wake-up) alarm. The PWR output pin can be triggered by one
or either of these events, and can be used to turn on an external power supply. The PWR pin is under
software control, so that when a task is complete, the system power can then be shut down.
The DS1685 is a clock/calendar chip with the features described above. An external crystal and battery
are the only components required to maintain time-of-day and memory status in the absence of power.
The DS1687 incorporates the DS1685 chip, a 32.768kHz crystal, and a lithium battery in a complete,
self-contained timekeeping module. The entire unit is fully tested at Dallas Semiconductor such that a
minimum of 10 years of timekeeping and data retention in the absence of VCC is guaranteed.
OPERATIONThe block diagram in Figure 1 shows the pin connections with the major internal functions of the
DS1685/DS1687. The following paragraphs describe the function of each pin.
DS1685/DS1687
SIGNAL DESCRIPTIONS
GND, VCC – DC power is provided to the device on these pins. VCC is the +3V or +5V input.
SQW (Square-Wave Output) - The SQW pin provides a 32kHz square-wave output, tREC, after a power-up condition has been detected. This condition sets the following bits, enabling the 32kHz output;
DV1 = 1, and E32K = 1. A square wave is output on this pin if either SQWE = 1 or E32K = 1. If E32K =
1, then 32kHz is output regardless of the other control bits. If E32K = 0, then the output frequency is
dependent on the control bits in register A. The SQW pin can output a signal from one of 13 taps
provided by the 15 internal divider stages of the RTC. The frequency of the SQW pin can be changed by
programming Register A as shown in Table 2. The SQW signal can be turned on and off using the SQWE
bit in register B or the E32K bit in extended register 4Bh. A 32kHz SQW signal is output when the
enable-32kHz (E32K) bit in extended register 4Bh is a logic 1 and VCC is above VPF. A 32kHz square
wave is also available when VCC is less than VPF if E32K = 1, ABE = 1, and voltage is applied to the
VBAUX pin.
AD0–AD7 (Multiplexed Bidirectional Address/Data Bus) – Multiplexed buses save pins because
address information and data information time-share the same signal paths. The addresses are present
during the first portion of the bus cycle and the same pins and signal paths are used for data in the second
portion of the cycle. Address/data multiplexing does not slow the access time of the DS1685 since the bus
change from address to data occurs during the internal RAM access time. Addresses must be valid prior
to the latter portion of ALE, at which time the DS1685/DS1687 latches the address. Valid write data must
be present and held stable during the latter portion of the WR pulse. In a read cycle, the DS1685/DS1687
outputs 8 bits of data during the latter portion of the RD pulse. The read cycle is terminated and the bus
returns to a high-impedance state as RD transitions high. The address/data bus also serves as a
bidirectional data path for the external extended RAM.
ALE (RTC Address-Strobe Input; Active High) – A pulse on the address strobe pin serves to
demultiplex the bus. The falling edge of ALE causes the RTC address to be latched within the
DS1685/DS1687.
(RTC Read Input; Active Low) - RD identifies the time period when the DS1685/DS1687 drives
the bus with RTC read data. The RD signal is an enable signal for the output buffers of the clock.
(RTC Write Input; Active Low) -The WR signal is an active-low signal. The WR signal defines
the time period during which data is written to the addressed register.
(RTC Chip-Select Input; Active Low) – The chip-select signal must be asserted low during a buscycle for the RTC portion of the DS1685/DS1687 to be accessed. CS must be kept in the active state
during RD and WR timing. Bus cycles that take place with ALE asserted but without asserting CS latch
addresses. However, no data transfer occurs.
IRQ (Interrupt-Request Output; Open Drain, Active Low) – The IRQ pin is an active-low output of
the DS1685/DS1687 that can be connected to the interrupt input of a processor. The IRQ output remains
DS1685/DS1687
set. To clear the IRQ pin, the application software must clear all enabled flag bits contributing to IRQ’s
active state.
When no interrupt conditions are present, the IRQ level is in the high-impedance state. Multiple
interrupting devices can be connected to an IRQ bus. The IRQ pin is an open-drain output and requires an
external pullup resistor. The voltage on the pullup supply should be no greater than VCC + 0.2V.
PWR (Power-On Output; Open Drain, Active Low) – The PWR pin is intended for use as an on/off
control for the system power. With VCC voltage removed from the DS1685/DS1687, PWR can be
automatically activated from a kickstart input by the KS pin or from a wake-up interrupt. Once the
system is powered on, the state of PWR can be controlled by bits in the Dallas registers. The PWR pin
can be connected through a pullup resistor to a positive supply. For 5V operation, the voltage of the
pullup supply should be no greater than 5.7V. For 3V operation, the voltage of the pullup supply should
be no greater than 3.9V.
(Kickstart Input; Active Low) – When VCC is removed from the DS1685/DS1687, the system canbe powered on in response to an active-low transition on the KS pin, as might be generated from a key
closure. VBAUX must be present and the auxiliary-battery enable bit (ABE) must be set to 1 if the kickstart
function is used, and the KS pin must be pulled up to the VBAUX supply. While VCC is applied, the KS pin
can be used as an interrupt input.
RCLR (RAM Clear Input; Active Low) – If enabled by software, taking RCLR low clears the 242
bytes of user RAM. When enabled, RCLR can be activated whether or not VCC is present. The RCLR
function is designed to be used by a human interface (shorting to ground manually or by a switch) and not
to be driven with external buffers. This pin is internally pulled up. Do not use an external pullup resistor
on this pin.
VBAUX – Auxiliary battery input required for kickstart and wake-up features. This input also supports
clock/ calendar and user RAM if VBAT is at lower voltage or is not present. A standard +3V lithium cell or
other energy source can be used. Battery voltage must be held between +2.5V and +3.7V for proper
operation. If VBAUX is not going to be used it should be grounded, and auxiliary-battery enable bit bank 1,
register 4BH, should equal 0.
See “Conditions of Acceptability” at http:///TechSupport/QA/ntrl.htm.
DS1685 ONLY
X1, X2 – Connections for a standard 32.768kHz quartz crystal. For greatest accuracy, the DS1685 mustbe used with a crystal that has a specified load capacitance of either 6pF or 12.5pF. The crystal-select
(CS) bit in Extended Control Register 4B is used to select operation with a 6pF or 12.5pF crystal. The
crystal is attached directly to the X1 and X2 pins. There is no need for external capacitors or resistors.Note: X1 and X2 are very high-impedance nodes. It is recommended that they and the crystal be guard-
ringed with ground and that high-frequency signals be kept away from the crystal area.
DS1685/DS1687
VBAT – Battery input for any standard 3V lithium cell or other energy source. Battery voltage must beheld between 2.5V and 3.7V for proper operation. VBAT must be grounded if not used. Diodes should not
be placed between VBAT and the battery.
N.C. – No Connection.See “Conditions of Acceptability” at http:///TechSupport/QA/ntrl.htm
DS1685/DS1687
Figure 1. BLOCK DIAGRAM
DS1685/DS1687
OSCILLATOR STARTUP TIMEOscillator startup times are highly dependent upon crystal characteristics and layout. High ESR and
excessive capacitive loads are the major contributors to long startup times. A circuit using a crystal with
the recommended characteristics and following the recommended layout usually starts within one second.
CLOCK ACCURACYThe accuracy of the clock is dependent on the accuracy of the crystal and the accuracy of the matchbetween the capacitive load of the oscillator circuit and the capacitive load for which the crystal was
trimmed. Additional error is added by crystal frequency drift caused by temperature shifts. External
circuit noise coupled into the oscillator circuit can result in the clock running fast.
The DS1685 can also be driven by an external 32.768 kHz oscillator. In this configuration, the X1 pin isconnected to the external oscillator signal and the X2 pin is floated. Refer to Application Note 58 “Crystal
Considerations with Dallas Real-Time Clocks” for detailed information about crystal selection and crystal
layout.
DS1685/DS1687
POWER-DOWN/POWER-UP CONSIDERATIONSThe RTC function continues to operate, and all of the RAM, time, calendar, and alarm memory locations
remain nonvolatile regardless of the level of the VCC input. When VCC is applied to the DS1685/DS1687
and reaches a level of greater than VPF (power-fail trip point), the device becomes accessible after tREC,
provided that the oscillator is running and the oscillator countdown chain is not in reset (Register A). This
time period allows the system to stabilize after power is applied.
The DS1685/DS1687 is available in either a 3V or a 5V device.
The 5V device is fully accessible and data can be written and read only when VCC is greater than 4.5V.
When VCC is below 4.5V, read and writes are inhibited. However, the timekeeping function continuesunaffected by the lower input voltage. As VCC falls below the greater of VBAT and VBAUX, the RAM and
timekeeper are switched over to a lithium battery connected either to the VBAT pin or VBAUX pin.
The 3V device is fully accessible and data can be written or read only when VCC is greater than 2.7V.
When VCC falls below VPF, access to the device is inhibited. If VPF is less than VBAT and VBAUX, thepower supply is switched from VCC to the backup supply (the greater of VBAT and VBAUX) when VCC
drops below VPF. If VPF is greater than VBAT and VBAUX, the power supply is switched from VCC to the
backup supply when VCC drops below the larger of VBAT and VBAUX.
When VCC falls below VPF, the chip is write-protected. With the possible exception of the KS, PWR, and
SQW pins, all inputs are ignored and all outputs are in a high-impedance state.
RTC ADDRESS MAPThe address map for the RTC registers of the DS1685/DS1687 is shown in Figure 2. The address mapconsists of the 14 clock/calendar registers. Ten registers contain the time, calendar, and alarm data, and
four bytes are used for control and status. All registers can be directly written or read except for the
following:
1) Registers C and D are read-only.2) Bit 7 of Register A is read-only.
3) The high order bit of the seconds byte is read-only.
DS1685/DS1687
Figure 2. DS1685 RTC ADDRESS MAPBINARY OR BCD INPUTS
TIME, CALENDAR, AND ALARM LOCATIONSThe time and calendar information is obtained by reading the appropriate register bytes shown in Table 1.
The time, calendar, and alarm are set or initialized by writing the appropriate register bytes. The contentsof the time, calendar, and alarm registers can be either binary or binary coded decimal (BCD) format.
Table 1 shows the binary and BCD formats of the 10 time, calendar, and alarm locations that reside in
both bank 0 and in bank 1, plus the two extended registers that reside in bank 1 only (bank 0 and bank 1
switching are explained later in this text).
Before writing the internal time, calendar, and alarm registers, the SET bit in Register B should be written
to a logic 1 to prevent updates from occurring while access is being attempted. Also at this time, the data
format (binary or BCD) should be set by the data mode bit (DM) of Register B. All time, calendar, and
alarm registers must use the same data mode. The set bit in Register B should be cleared after the data
mode bit has been written to allow the RTC to update the time and calendar bytes.
Once initialized, the RTC makes all updates in the selected mode. The data mode cannot be changed
without reinitializing the 10 data bytes. The 24/12 bit cannot be changed without reinitializing the hour
locations. When the 12-hour format is selected, the high order bit of the hours byte represents PM when itis a logic 1. The time, calendar, and alarm bytes are always accessible because they are double buffered.
Once per second the 10 bytes are advanced by one second and checked for an alarm condition. If a read
of the time and calendar data occurs during an update, a problem exists where seconds, minutes, hours,
etc., might not correlate. The probability of reading incorrect time and calendar data is low. Several
methods of avoiding any possible incorrect time and calendar reads are covered later.
The three time alarm bytes can be used in two ways. First, when the alarm time is written in the
appropriate hours, minutes, and seconds alarm locations, the alarm interrupt is initiated at the specified
time each day if the alarm enable bit is high. The second use condition is to insert a “don’t care” state in
DS1685/DS1687
generated each hour when the “don’t care” bits are set in the hours byte. Similarly, an alarm is generatedevery minute with “don’t care” codes in the hours and minute alarm bytes. The “don’t care” codes in all
three time alarm bytes create an interrupt every second. The three time-alarm bytes can be used with the
date alarm as described in the Wake-Up/Kickstart section. The century counter is discussed later in this
text.
Table 1. TIME, CALENDAR, AND ALARM DATA MODES
DS1685/DS1687
CONTROL REGISTERSThe four control registers A, B, C, and D reside in both bank 0 and bank 1. These registers are accessible
at all times, even during the update cycle.
REGISTER AMSBLSB
UIP – The update-in-progress (UIP) bit is a status flag that can be monitored. When the UIP bit is a 1, theupdate transfer occurs soon. When UIP is a 0, the update transfer does not occur for at least 244�s. The
time, calendar, and alarm information in RAM is fully available for access when the UIP bit is 0. The UIP
bit is read-only. Writing the SET bit in Register B to a 1 inhibits any update transfer and clears the UIPstatus bit.
DV2, DV1, DV0 – These bits are defined as follows:DV2 = Countdown Chain1 – resets countdown chain only if DV1 = 1
0 – countdown chain enabled
DV1 = Oscillator Enable
0 – oscillator off1 – oscillator on
DV0 = Bank Select
0 – original bank
A pattern of 01X is the only combination of bits that turns the oscillator on and allows the RTC to keep
time. A pattern of 11X enables the oscillator but holds the countdown chain in reset. The next update
occurs at 500ms after a pattern of 01X is written to DV2, DV1, and DV0.
RS3, RS2, RS1, RS0 – These four rate-selection bits select one of the 13 taps on the 15-stage divider ordisable the divider output. The tap selected can be used to generate an output square wave (SQW pin)
and/or a periodic interrupt. The user can do one of the following:
1) Enable the interrupt with the PIE bit;
2) Enable the SQW output pin with the SQWE or E32K bits;3) Enable both at the same time and the same rate; or
4) Enable neither.
Table 2 lists the periodic interrupt rates and the square-wave frequencies that can be chosen with the RS
bits.
DS1685/DS1687
REGISTER BMSBLSB
SET – When the SET bit is a 0, the update transfer functions normally by advancing the counts once persecond. When the SET bit is written to a 1, any update transfer is inhibited and the program can initialize
the time and calendar bytes without an update occurring in the midst of initializing. Read cycles can beexecuted in a similar manner. SET is a read/write bit that is not modified by internal functions of the
DS1685/DS1687.
PIE – The periodic-interrupt enable bit is a read/write bit that allows the periodic-interrupt flag (PF) bit inRegister C to drive the IRQ pin low. When the PIE bit is set to 1, periodic interrupts are generated by
driving the IRQ pin low at a rate specified by the RS3–RS0 bits of Register A. A 0 in the PIE bit blocks
the IRQ output from being driven by a periodic interrupt, but the periodic flag (PF) bit is still set at the
periodic rate. PIE is not modified by any internal DS1685/DS1687 functions.
AIE – The alarm-interrupt enable (AIE) bit is a read/write bit which, when set to a 1, permits the alarmflag (AF) bit in Register C to assert IRQ. An alarm interrupt occurs for each second that the three time
bytes equal the three alarm bytes, including a “don’t care” alarm code of binary 11XXXXXX. When the
AIE bit is set to 0, the AF bit does not initiate the IRQ signal. The internal functions of the
DS1685/DS1687 do not affect the AIE bit.
UIE – The update-ended interrupt-enable (UIE) bit is a read/write bit that enables the update-end flag(UF) bit in Register C to assert IRQ. The SET bit going high clears the UIE bit.
SQWE – When the square-wave enable (SQWE) bit is set to a 1 and E32K = 0, a square-wave signal atthe frequency set by the rate-selection bits RS3–RS0 is driven out on the SQW pin. When the SQWE bitis set to 0 and E32K = 0, the SQW pin is held low. SQWE is a read/write bit.
DM – The data mode (DM) bit indicates whether time and calendar information is in binary or BCD
format. The DM bit is set by the program to the appropriate format and can be read as required. This bit is
not modified by internal functions. A 1 in DM signifies binary data while a 0 in DM specifies BCD data.
24/12 – The 24/12 control bit establishes the format of the hours byte. A 1 indicates the 24-hour mode
and a 0 indicates the 12-hour mode. This bit is read/write.
DSE – The Daylight Savings Enable (DSE) bit is a read/write bit that enables two special updates whenDSE is set to 1. On the first Sunday in April, the time increments from 1:59:59 AM to 3:00:00 AM. On
the last Sunday in October, when the time first reaches 1:59:59 AM, it changes to 1:00:00 AM. These
special updates do not occur when the DSE bit is a 0. This bit is not affected by internal functions.
DS1685/DS1687
REGISTER CMSBLSB
IRQF – The interrupt-request flag (IRQF) bit is set to a 1 when one or more of the following are true:PF = PIE = 1 WF = WIE= 1
AF = AIE = 1 KF = KSE= 1
UF = UIE = 1 RF = RIE = 1
i.e., IRQF = (PF x PIE) + (AF x AIE) + (UF x UIE) + (WF x WIE) + (KF x KSE) + (RF x RIE)
Any time the IRQF bit is a 1, the IRQ pin is driven low. Flag bits PF, AF, and UF are cleared after
Register C is read by the program.
PF – The periodic-interrupt flag (PF) is a read-only bit that is set to a 1 when an edge is detected on theselected tap of the divider chain. The RS3–RS0 bits establish the periodic rate. PF is set to a 1
independently of the state of the PIE bit. When both PF and PIE are 1’s, the IRQ signal is active and sets
the IRQF bit. The PF bit is cleared by a software read of Register C.
AF – A 1 in the alarm-interrupt flag (AF) bit indicates that the current time has matched the alarm time. Ifthe AIE bit is also a 1, the IRQ pin goes low and a 1 appears in the IRQF bit. A read of Register C clears
AF.
UF – The update-ended interrupt flag (UF) bit is set after each update cycle. When the UIE bit is set to 1,the one in UF causes the IRQF bit to be a 1, which asserts the IRQ pin. UF is cleared by reading Register
BIT 3, BIT2, BIT 1, BIT 0 - These are unused bits of the status Register C. These bits always read 0 andcannot be written.
REGISTER DMSBLSB
VRT – The valid RAM and time (VRT) bit indicates the condition of the battery connected to the VBATpin or the battery connected to VBAUX, whichever is at a higher voltage. This bit is not writable and should
always be a 1 when read. If a 0 is ever present, an exhausted lithium energy source is indicated and both
the contents of the RTC data and RAM data are questionable.
BIT 6, BIT 5, BIT 4, BIT 3, BIT 2, BIT 1, BIT 0 – The remaining bits of Register D are not usable.They cannot be written and when read will always read 0.
DS1685/DS1687
NV RAM—RTCThe 242 general-purpose NV RAM bytes are not dedicated to any special function within the
DS1685/DS1687. They can be used by the application program as nonvolatile memory and are fully
available during the update cycle.
The user RAM is divided into two separate memory banks. When the bank 0 is selected, the 14 RTCregisters and 114 bytes of user RAM are accessible. When bank 1 is selected, an additional 128 bytes of
user RAM are accessible through the extended RAM address and data registers.
INTERRUPT CONTROLThe DS1685/DS1687 includes six separate, fully automatic sources of interrupt for a processor:
1) Alarm Interrupt
2) Periodic Interrupt
3) Update-Ended Interrupt
4) Wake-Up Interrupt
5) Kickstart Interrupt
6) RAM Clear Interrupt
The conditions that generate each of these independent interrupt conditions are described in greater detail
elsewhere in this data sheet. This section describes the overall control of the interrupts.
The application software can select which interrupts, if any, are to be used. There are a total of 6 bits,
including 3 bits in Register B and 3 bits in Extended Register B, that enable the interrupts. The extended
register locations are described later. Writing a logic 1 to an interrupt-enable bit permits that interrupt to
be initiated when the event occurs. A logic 0 in the interrupt enable bit prohibits the IRQ pin from being
asserted from that interrupt condition. If an interrupt flag is already set when an interrupt is enabled, IRQ
is immediately set at an active level, even though the event initiating the interrupt condition might have
occurred much earlier. As a result, there are cases where the software should clear these earlier generated
interrupts before first enabling new interrupts.
When an interrupt event occurs, the relating flag bit is set to a logic 1 in Register C or in Extended
Register A. These flag bits are set regardless of the setting of the corresponding enable bit located either
in Register B or in Extended Register B. The flag bits can be used in a polling mode without enabling the
corresponding enable bits.
However, care should be taken when using the flag bits of Register C as they are automatically cleared to
0 immediately after they are read. Double latching is implemented on these bits so that set bits remain
stable throughout the read cycle. All bits that were set are cleared when read and new interrupts that are
pending during the read cycle are held until after the cycle is completed. One, two, or three bits can be set
when reading Register C. Each used flag bit should be examined when read to ensure that no interrupts
are lost.
The flag bits in Extended Register A are not automatically cleared following a read. Instead, each flag bit
DS1685/DS1687
When using the flag bits with fully enabled interrupts, the IRQ line is driven low when an interrupt flag
bit is set and its corresponding enable bit is also set. IRQ is held low as long as at least one of the six
possible interrupt sources has its flag and enable bits both set. The IRQF bit in Register C is a 1 whenever
the IRQ pin is being driven low as a result of one of the six possible active sources. Therefore,
determination that the DS1685/DS1687 initiated an interrupt is accomplished by reading Register C and
finding IRQF = 1. IRQF remains set until all enabled interrupt flag bits are cleared to 0.
SQUARE-WAVE OUTPUT SELECTIONThe SQW pin can be programmed to output a variety of frequencies divided down from the 32.768kHz
crystal tied to X1 and X2. The square-wave output is enabled and disabled by the SQWE bit in Register Bor the E32K bit in extended register 4Bh. If the square wave is enabled (SQWE = 1 or E32K = 1), then
the output frequency is determined by the settings of the E32K bit in Extended Register 4Bh and by the
RS3–0 bits in Register A. If E32K = 1, then a 32.768kHz square wave is output on the SQW pin
regardless of the settings of RS3–0 and SQWE.
If E32K = 0, then the square-wave output frequency is determined by the RS3–0 bits. These bits control a
1-of-15 decoder, which selects one of 13 taps that divide the 32.768kHz frequency. The RS3–0 bits
establish the SQW output frequency as shown in Table 2. In addition, RS3–0 bits control the periodic
interrupt selection as described below.
If E32K = 1 and the auxiliary-battery enable bit (ABE, bank 1; register 04BH) is enabled, and voltage is
applied to VBAUX, then the 32kHz square-wave output signal is output on the SQW pin in the absence of
VCC. This facility is provided to clock external power management circuitry. If any of the above
requirements are not met, no square-wave output signal is generated on the SQW pin in the absence of
VCC.
A pattern of 01X in the DV2, DV1, and DV0 bits respectively turns the oscillator on and enables the
countdown chain. Note that this is different than the DS1287, which required a pattern of 010 in these
bits. DV0 is now a “don’t care” because it is used for selection between register banks 0 and 1.
A pattern of 11X turns the oscillator on, but the oscillator’s countdown chain is held in reset, as it was in
the DS1287. Any other bit combination for DV2 and DV1 keeps the oscillator off.
Oscillator Control BitsWhen the DS1687 is shipped from the factory, the internal oscillator is turned off. This feature prevents
the lithium energy cell from being used until it is installed in a system. A pattern of 01X in bits 4 through6 of Register A turns the oscillator on and enables the countdown chain. A pattern of 11X turns the
oscillator on, but holds the countdown chain of the oscillator in reset. All other combinations of bits 4
through 6 keep the oscillator off.
PERIODIC INTERRUPT SELECTIONThe periodic interrupt causes the IRQ pin to go to an active state from once every 500ms to once every
122�s. This function is separate from the alarm interrupt, which can be output from once per second to
once per day. The periodic interrupt rate is selected using the same RS3–0 bits in Register A, which selectthe square-wave frequency (Table 2). Changing the bits affects both the square-wave frequency and the
periodic-interrupt output. However, each function has a separate enable bit in Register B. The SQWE and
DS1685/DS1687
Register B. The periodic interrupt can be used with software counters to measure inputs, create outputintervals, or await the next needed software function.
Table 2. PERIODIC INTERRUPT RATE AND SQUARE-WAVE OUTPUT
FREQUENCY*RS3–RS0 determine periodic interrupt rates as listed for E32K=0.
DS1685/DS1687
UPDATE CYCLEThe serialized RTC executes an update cycle once per second regardless of the SET bit in Register B.
When the SET bit in Register B is set to 1, the user copy of the double-buffered time, calendar, alarm,
and elapsed time byte is frozen and does not update as the time increments. However, the time countdown
chain continues to update the internal copy of the buffer. This feature allows the time to maintain
accuracy independent of reading or writing the time, calendar, and alarm buffers and also guarantees thattime and calendar information is consistent. The update cycle also compares each alarm byte with the
corresponding time byte and issues an alarm if a match or if a “don’t care” code is present in all alarm
locations.
There are three methods that can handle access of the RTC that avoid any possibility of accessinginconsistent time and calendar data. The first method uses the update-ended interrupt. If enabled, an
interrupt occurs after every update cycle that indicates that over 999ms are available to read valid time
and date information. If this interrupt is used, the IRQF bit in Register C should be cleared before leaving
the interrupt routine.
A second method uses the UIP bit in Register A to determine if the update cycle is in progress. The UIP
bit pulses once per second. After the UIP bit goes high, the update transfer occurs 244µs later. If a low is
read on the UIP bit, the user has at least 244µs before the time/calendar data is changed. Therefore, the
user should avoid interrupt service routines that would cause the time needed to read valid time/calendar
data to exceed 244µs.
The third method uses a periodic interrupt to determine if an update cycle is in progress. The UIP bit in
Register A is set high between the setting of the PF bit in Register C (Figure 3). Periodic interrupts that
occur at a rate of greater than tBUC allow valid time and date information to be reached at each occurrence
of the periodic interrupt. The reads should be complete within (tPI / 2 + tBUC) to ensure that data is notread during the update cycle.
Figure 3. UPDATE-ENDED AND PERIODIC-INTERRUPT RELATIONSHIPUIP BIT IN
REGISTER A
UF BIT IN
REGISTER C
PF BIT IN
REGISTER C
tPI = PERIODIC INTERRUPT TIME INTERNAL PER TABLE 1
tBUC = DELAY TIME BEFORE UPDATE CYCLE = 244µs
DS1685/DS1687
EXTENDED FUNCTIONSThe extended functions provided by the DS1685/DS1687 that are new to the RAMified RTC family are
accessed by a software-controlled bank-switching scheme, as illustrated in Figure 4. In bank 0, the
clock/calendar registers and 50 bytes of user RAM are in the same locations as for the DS1287. As a
result, existing routines implemented within BIOS, DOS, or application software packages can gain
access to the DS1685/DS1687 clock registers with no changes. Also in bank 0, an extra 64 bytes of RAMare provided at addresses just above the original locations for a total of 114 directly addressable bytes of
user RAM.
When bank 1 is selected, the clock/calendar registers and the original 50 bytes of user RAM still appear
as bank 0. However, the Dallas registers that provide control and status for the extended functions areaccessed in place of the additional 64 bytes of user RAM. The major extended functions controlled by the
Dallas registers are listed below:
1) 64-bit Silicon Serial Number
2) Century counter3) Date Alarm
4) Auxiliary Battery Control/Status
5) Wake-Up
6) Kickstart
7) RAM Clear Control/Status8) 128-bytes Extended RAM Access
The bank selection is controlled by the state of the DV0 bit in register A. To access bank 0, the DV0 bit
should be written to a 0. To access bank 1, DV0 should be written to a 1. Register locations designated as
reserved in the bank 1 map are reserved for future use by Dallas Semiconductor. Bits in these locationscannot be written and return a 0 if read.
SILICON SERIAL NUMBERA unique 64-bit lasered serial number is located in bank 1, registers 40h to 47h. This serial number is
divided into three parts. The first byte in register 40h contains a model number, 47h, to identify the device
type. Registers 41h to 46h contain a unique binary number. Register 47h contains a CRC byte used tovalidate the data in registers 40h to 46h. All 8 bytes of the serial number are read-only registers.
The DS1685/DS1687 is manufactured such that no two devices contain an identical number in locations
41h to 47h.
CENTURY COUNTERA register has been added in bank 1, location 48H, to keep track of centuries. The value is read in eitherbinary or BCD according to the setting of the DM bit.
