DS1685S-5 ,3V/5V Real-Time Clocksfeatures described above. An external crystal and battery are the only components required to maint ..
DS1685S-5+ ,3V/5V Real-Time ClockFEATURES PIN ASSIGNMENT (Top View)Incorporates industry-standard DS1287 PC clockplus enhanced
DS1685SN-5 ,3V/5V Real-Time ClocksFEATURES Incorporates Industry-Standard DS1287 PC Clock plus Enhanced
DS1685SN-5+ ,3V/5V Real-Time Clockfeatures:PWR 1 24 VCC Y2K-compliant2X1 23 SQW +3 or +5V operationX23 22 VBAUX 64-bit silicon ser ..
DS1685SN-5+T&R ,3V/5V Real-Time Clockfeatures:PWR 1 24 VCC Y2K-compliant2X1 23 SQW +3 or +5V operationX23 22 VBAUX 64-bit silicon ser ..
DS1687+3 ,3V/5V Real-Time Clocksfeatures described above. An external crystal and battery are the only components required to maint ..
DV74AC244 , Octal buffer/Line Driver with 3-state Outputs
DVIULC6-2P6 ,Ultra Low capacitance 2 lines ESD protectionApplicationsBenefits■ DVI ports up to 1.65 Gb/s■ ESD standards compliance guaranteed at ■ IEEE 1394 ..
DVIULC6-4SC6 ,Ultralow capacitance ESD protectionFeatures■ 4-line ESD protection (IEC 61000-4-2)■ Protects V when applicableBUS■ Ultralow capacitanc ..
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DW01 , One Cell Lithium-ion/Polymer Battery Protection IC
DS1685-3-DS1685-5-DS1685E-3-DS1685E-5-DS1685E-5/T&R-DS1685EN-3-DS1685EN-5-DS1685Q-5-DS1685S-3-DS1685S-5-DS1685SN-5-DS1687+3-DS1687-3-DS1687-5-DS1687-5.
3V/5V Real-Time Clocks
FEATURES Incorporates Industry-Standard DS1287 PC Clock
plus Enhanced Features Such as:Y2K Compliant +3V or +5V Operation 64-Bit Silicon Serial Number Power-Control Circuitry Supports System Power-On from Date/Time Alarm or Key Closure 32kHz Output for Power Management Crystal-Select Bit Allows RTC to Operate with
6pF or 12.5pF Crystal SMI Recovery Stack 242 Bytes Battery-Backed NV RAM Auxiliary Battery Input RAM Clear Input Century Register Date Alarm Register Compatible with Existing BIOS for Original DS1287 Functions Available as Chip (DS1685) or Stand-Alone Encapsulated DIP (EDIP) with Embedded
Battery and Crystal (DS1687) Timekeeping Algorithm Includes Leap-Year
Compensation Valid Through 2099 Underwriters Laboratory (UL) Recognized
APPLICATIONS Embedded Systems
Utility Meters
Security Systems
Network Hubs, Bridges, and Routers
PIN CONFIGURATIONS PACKAGE DIMENSION
INFORMATION /DallasPackInfo
DS1685/DS1687
3V/5V Real-Time Clocks
DS1685/DS1687 3V/5V Real-Time Clocks
ORDERING INFORMATION *An “N” located in the right-hand corner of the top of the package denotes an industrial device.
DS1685/DS1687 3V/5V Real-Time Clocks
TYPICAL OPERATING CIRCUIT
DETAILED DESCRIPTION The DS1685/DS1687 are real-time clocks (RTC) designed as successors to the industry-standard DS1285, DS1385, DS1485, and DS1585 PC RTCs. These devices provide the industry-standard DS1285 clock function with
either +3.0V or +5.0V operation. The DS1685 also incorporates a number of enhanced features including a silicon serial number, power-on/off control circuitry, 242 bytes of user NV SRAM, and 32.768kHz output for sustaining
power management activities.
The DS1685/DS1687 power-control circuitry allows the system to be powered on by an external stimulus such as a keyboard or by a time and date (wake-up) alarm. The PWR output pin can be triggered by one or either of these
events, and can be used to turn on an external power supply. The PWR pin is under software control, so that when a task is complete, the system power can then be shut down. The DS1685 is a clock/calendar chip with the features described above. An external crystal and battery are the
only components required to maintain time-of-day and memory status in the absence of power. The DS1687 incorporates the DS1685 chip, a 32.768kHz crystal, and a lithium battery in a complete, self-contained timekeeping
EDIP. The entire unit is fully tested at Dallas Semiconductor such that a minimum of 10 years of timekeeping and data retention in the absence of VCC is guaranteed.
OPERATION The block diagram in Figure 1 shows the pin connections with the major internal functions of the DS1685/DS1687.
The following paragraphs describe the function of each pin.
DS1685/DS1687 3V/5V Real-Time Clocks
PIN DESCRIPTIONS
DS1685/DS1687 3V/5V Real-Time Clocks
PIN DESCRIPTIONS (continued)
DS1685/DS1687 3V/5V Real-Time Clocks
Figure 1. Block Diagram
OSCILLATOR CIRCUIT The DS1685 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or
capacitors to operate. Table 1 specifies several crystal parameters for the external crystal, and Figure 2 shows a functional schematic of the oscillator circuit. The oscillator is controlled by an enable bit in the control register.
Oscillator startup times are highly dependent upon crystal characteristics, PC board leakage, and layout. High ESR and excessive capacitive loads are the major contributors to long startup times. A circuit using a crystal with the
recommended characteristics and proper layout usually starts within one second.
DS1685/DS1687 3V/5V Real-Time Clocks
Table 1. Crystal Specifications* *The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations
for Dallas Real-Time Clocks for additional specifications.
CLOCK ACCURACY The accuracy of the clock is dependent on the accuracy of the crystal and the accuracy of the match between the
capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error is added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator
circuit can result in the clock running fast. Figure 3 shows a typical PC board layout for isolation of the crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks for
detailed information.
The DS1685 can also be driven by an external 32.768 kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated. Refer to Application Note 58: Crystal Considerations with
Dallas Real-Time Clocks for detailed information about crystal selection and crystal layout.
Figure 2. Oscillator Circuit Showing Internal Bias Network
Figure 3. Typical Crystal Layout
DS1685/DS1687 3V/5V Real-Time Clocks
POWER-DOWN/POWER-UP CONSIDERATIONS The RTC function continues to operate, and all of the RAM, time, calendar, and alarm memory locations remain
nonvolatile regardless of the level of the VCC input. . At least one back up supply must remain within the minimum and maximum limits whenever VCC is not at a valid level. When VCC is applied and exceeds VPF (power-fail trip
point), the device becomes accessible after tREC, provided that the oscillator is running and the oscillator countdown chain is not in reset (Register A). This time period allows the system to stabilize after power is applied. If the
oscillator is not enabled, the oscillator enable bit will be enabled on power up, and the device becomes immediately accessible. The DS1685/DS1687 is available in either a 3V or a 5V device. The 5V device is fully accessible and data can be written and read only when VCC is greater than 4.5V. When VCC
falls below VPF, read and writes are inhibited. However, the timekeeping function continues unaffected by the lower input voltage. As VCC falls below the greater of VBAT and VBAUX, the RAM and timekeeper are switched over to a
lithium battery connected either to the VBAT pin or VBAUX pin.
The 3V device is fully accessible and data can be written or read only when VCC is greater than 2.7V. When VCC falls below VPF, reads and writes are inhibited. If VPF is less than VBAT and VBAUX, the power supply is switched from
VCC to the backup supply (the greater of VBAT and VBAUX) when VCC drops below VPF. If VPF is greater than VBAT and VBAUX, the power supply is switched from VCC to the backup supply when VCC drops below the larger of VBAT and
VBAUX.
When VCC falls below VPF, the device inhibits access by internally disabling the CS input. With the possible
exception of the KS, PWR, and SQW pins, all inputs are ignored and all outputs are in a high-impedance state.
TIME, CALENDAR, AND ALARM LOCATIONS The time and calendar information is obtained by reading the appropriate register bytes shown in Table 2. The time, calendar, and alarm are set or initialized by writing the appropriate register bytes. The contents of the time,
calendar, and alarm registers can be either binary or binary coded decimal (BCD) format. Table 2 shows the binary and BCD formats of the 10 time, calendar, and alarm locations that reside in both bank 0 and in bank 1, plus the
two extended registers that reside in bank 1 only (bank 0 and bank 1 switching are explained later in this text).
Before writing the internal time, calendar, and alarm registers, the SET bit in Register B should be written to a logic 1 to prevent updates from occurring while access is being attempted. Also at this time, the data format (binary or
BCD) should be set by the data mode bit (DM) of Register B. All time, calendar, and alarm registers must use the same data mode. Invalid time and date entries will result in undefined operation. The set bit in Register B should
be cleared after the data mode bit has been written to allow the RTC to update the time and calendar bytes. If the oscillator is running, the time and date registers will update 500ms after the countdown chain is enabled. Once initialized, the RTC makes all updates in the selected mode. The data mode cannot be changed without
reinitializing the 10 data bytes. The 24/12 bit cannot be changed without reinitializing the hour locations. When the 12-hour format is selected, the high order bit of the hours byte represents PM when it is a logic 1. The time,
calendar, and alarm bytes are always accessible because they are double buffered. Once per second the 10 bytes are advanced by one second and checked for an alarm condition If a read of the time and calendar data occurs during an update, a problem exists where seconds, minutes, hours,
etc., might not correlate. The probability of reading incorrect time and calendar data is low. Several methods of avoiding any possible incorrect time and calendar reads are covered later. The three time alarm bytes can be used in two ways. First, when the alarm time is written in the appropriate hours,
minutes, and seconds alarm locations, the alarm interrupt is initiated at the specified time each day if the alarm enable bit is high. The second use condition is to insert a “don’t care” state in one or more of the three time-alarm bytes. The “don’t
care” code is any hexadecimal value from C0 to FF. The two most significant bits of each byte set the “don’t care” condition when at logic 1. An alarm is generated each hour when the “don’t care” bits are set in the hours byte.
DS1685/DS1687 3V/5V Real-Time Clocks
“don’t care” codes in all three time alarm bytes create an interrupt every second. The three time-alarm bytes can be
used with the date alarm as described in the Wake-Up/Kickstart section. The century counter is discussed later in this text. All registers can be directly written or read except for the following: 1) Registers C and D are read-only. 2) Bit 7 of Register A is read-only.
3) Bit 7 of the seconds byte is read-only.
Table 2A. Time, Calendar, and Alarm Data Modes—BCD Mode (DM = 0) X = Read/Write Bit.
Note 1: Unless otherwise specified, the state of the registers is not defined when power is first applied.
Note 2: Except for the seconds register, 0 bits in the time and date registers can be written to a 1, but may be modified when the clock updates. 0 bits should always be written to 0 except for alarm mask bits.
DS1685/DS1687 3V/5V Real-Time Clocks
Table 2. Time, Calendar, and Alarm Data Modes—Binary Mode (DM = 1) DS1685/DS1687 3V/5V Real-Time Clocks
CONTROL REGISTERS The four control registers A, B, C, and D reside in both bank 0 and bank 1. These registers are accessible at all
times, even during the update cycle.
Register A (0Ah) MSB LSB
UIP – The update-in-progress (UIP) bit is a status flag that can be monitored. When the UIP bit is a 1, the update transfer occurs soon. When UIP is a 0, the update transfer does not occur for at least 244�s. The time, calendar, and alarm information in RAM is fully available for access when the UIP bit is 0. The UIP bit is read-only. Writing
the SET bit in Register B to a 1 inhibits any update transfer and clears the UIP status bit.
DV2, DV1, DV0 - These three bits are used to turn the oscillator on or off and to reset the countdown chain. A pattern of 01X is the only combination of bits that will turn the oscillator on and allow the RTC to keep time. A
pattern of 11X will enable the oscillator but holds the countdown chain in reset. The next update will occur at 500ms after a pattern of 01X is written to DV0, DV1, and DV2. The oscillator enable bit, DV1, will be set to a 1
when VCC is applied.
DV2 = Countdown Chain 1 – resets countdown chain only if DV1=1 0 – countdown chain enabled
DV1 = Oscillator Enable 1 – oscillator on 0 – oscillator off DV0 = Bank Select 1 – extended registers 0 – original bank
RS3, RS2, RS1, RS0 – These four rate-selection bits select one of the 13 taps on the 15-stage divider or disable the divider output. The tap selected can be used to generate an output square wave (SQW pin) and/or a periodic interrupt. The user can do one of the following: 1) Enable the interrupt with the PIE bit; 2) Enable the SQW output pin with the SQWE or E32K bits;
3) Enable both at the same time and the same rate; or 4) Enable neither. Table 3 lists the periodic interrupt rates and the square-wave frequencies that can be chosen with the RS bits.
DS1685/DS1687 3V/5V Real-Time Clocks
Register B (0Bh) MSB LSB
SET – When the SET bit is a 0, the update transfer functions normally by advancing the counts once per second. When the SET bit is written to a 1, any update transfer is inhibited and the program can initialize the time and
calendar bytes without an update occurring in the midst of initializing. Read cycles can be executed in a similar manner. SET is a read/write bit that is not modified by internal functions of the DS1685/DS1687.
PIE – The periodic-interrupt enable bit is a read/write bit that allows the periodic-interrupt flag (PF) bit in Register C to drive the IRQ pin low. When the PIE bit is set to 1, periodic interrupts are generated by driving the IRQ pin low at
a rate specified by the RS3–RS0 bits of Register A. A 0 in the PIE bit blocks the IRQ output from being driven by a
periodic interrupt, but the periodic flag (PF) bit is still set at the periodic rate. PIE is not modified by any internal DS1685/DS1687 functions.
AIE – The alarm-interrupt enable (AIE) bit is a read/write bit which, when set to a 1, permits the alarm flag (AF) bit in Register C to assert IRQ. An alarm interrupt occurs for each second that the three time bytes equal the three
alarm bytes, including a “don’t care” alarm code of binary 11XXXXXX. When the AIE bit is set to 0, the AF bit does
not initiate the IRQ signal. The internal functions of the DS1685/DS1687 do not affect the AIE bit.
UIE – The update-ended interrupt-enable (UIE) bit is a read/write bit that enables the update-end flag (UF) bit in Register C to assert IRQ. The SET bit going high clears the UIE bit.
SQWE – When the square-wave enable (SQWE) bit is set to a 1 and E32K = 0, a square-wave signal at the
frequency set by the rate-selection bits RS3–RS0 is driven out on the SQW pin. When the SQWE bit is set to 0 and E32K = 0, the SQW pin is held low. SQWE is a read/write bit.
DM – The data mode (DM) bit indicates whether time and calendar information is in binary or BCD format. The DM bit is set by the program to the appropriate format and can be read as required. This bit is not modified by internal functions. A 1 in DM signifies binary data while a 0 in DM specifies BCD data.
24/12 – The 24/12 control bit establishes the format of the hours byte. A 1 indicates the 24-hour mode and a 0
indicates the 12-hour mode. This bit is read/write.
DSE - The Daylight Savings Enable (DSE) bit is a read/write bit that enables two daylight savings adjustments when DSE is set to 1. On the first Sunday in April the time increments from 1:59:59 AM to 3:00:00 AM. On the last
Sunday in October when the time first reaches 1:59:59 AM it changes to 1:00:00 AM. When DSE is enabled, the internal logic tests for the first/last Sunday condition at 1:59:59 AM. If the DSE bit is not set when the test occurs,
the daylight savings function will not operate correctly. These adjustments do not occur when the DSE bit is a zero. This bit is not affected by internal functions.
DS1685/DS1687 3V/5V Real-Time Clocks
Register C (0Ch) MSB LSB
IRQF – The interrupt-request flag (IRQF) bit is set to a 1 when one or more of the following are true: PF = PIE = 1 WF = WIE = 1
AF = AIE = 1 KF = KSE = 1 UF = UIE = 1 RF = RIE = 1
Any time the IRQF bit is a 1, the IRQ pin is driven low. Flag bits PF, AF, and UF are cleared after Register C is read by the program.
PF – The periodic-interrupt flag (PF) is a read-only bit that is set to a 1 when an edge is detected on the selected tap of the divider chain. The RS3–RS0 bits establish the periodic rate. PF is set to a 1 independently of the state of
the PIE bit. When both PF and PIE are 1’s, the IRQ signal is active and sets the IRQF bit. This bit may be cleared by reading Register C.
AF – A 1 in the alarm-interrupt flag (AF) bit indicates that the current time has matched the alarm time. If the AIE bit is also a 1, the IRQ pin goes low and a 1 appears in the IRQF bit. This bit may be cleared by reading Register C.
UF – The update-ended interrupt flag (UF) bit is set after each update cycle. When the UIE bit is set to 1, the one in UF causes the IRQF bit to be a 1, which asserts the IRQ pin. This bit may be cleared by reading Register C.
BIT 3, BIT2, BIT 1, BIT 0 - These are unused bits of the status Register C. These bits always read 0 and cannot be written.
Register D (0Dh) MSB LSB
VRT – The valid RAM and time (VRT) bit indicates the condition of the battery connected to the VBAT pin or the battery connected to VBAUX, whichever is at a higher voltage. This bit is not writable and should always be a 1 when
read. If a 0 is ever present, an exhausted lithium energy source is indicated and both the contents of the RTC data and RAM data are questionable.
BIT 6, BIT 5, BIT 4, BIT 3, BIT 2, BIT 1, BIT 0 – The remaining bits of Register D are not usable. They cannot be written and when read will always read 0.
DS1685/DS1687 3V/5V Real-Time Clocks
NV RAM—RTC The 242 general-purpose NV RAM bytes are not dedicated to any special function within the DS1685/DS1687.
They can be used by the application program as nonvolatile memory and are fully available during the update cycle. The user RAM is divided into two separate memory banks. When the bank 0 is selected, the 14 RTC registers and
114 bytes of user RAM are accessible. When bank 1 is selected, an additional 128 bytes of user RAM are accessible through the extended RAM address and data registers.
INTERRUPT CONTROL The DS1685/DS1687 includes six separate, fully automatic sources of interrupt for a processor:
1) Alarm Interrupt 2) Periodic Interrupt
3) Update-Ended Interrupt 4) Wake-Up Interrupt
5) Kickstart Interrupt 6) RAM Clear Interrupt The conditions that generate each of these independent interrupt conditions are described in detail in other
sections of this text. This section describes the overall control of the interrupts.
The application software can select which interrupts, if any, are to be used. There are a total of 6 bits, including 3 bits in Register B and 3 bits in Extended Register 4B, that enable the interrupts. The extended register locations
are described later. Writing a logic 1 to an interrupt-enable bit permits that interrupt to be initiated when the event occurs. A logic 0 in the interrupt enable bit prohibits the IRQ pin from being asserted from that interrupt condition. If
an interrupt flag is already set when an interrupt is enabled, IRQ is immediately set at an active level, even though the event initiating the interrupt condition might have occurred much earlier. As a result, there are cases where the
software should clear these earlier generated interrupts before first enabling new interrupts.
When an interrupt event occurs, the relating flag bit is set to a logic 1 in Register C or in Extended Register 4A. These flag bits are set regardless of the setting of the corresponding enable bit located either in Register B or in
Extended Register 4B. The flag bits can be used in a polling mode without enabling the corresponding enable bits.
However, care should be taken when using the flag bits of Register C as they are automatically cleared to 0 immediately after they are read. Double latching is implemented on these bits so that set bits remain stable
throughout the read cycle. All bits that were set are cleared when read and new interrupts that are pending during the read cycle are held until after the cycle is completed. One, two, or three bits can be set when reading Register
C. Each used flag bit should be examined when read to ensure that no interrupts are lost.
The flag bits in Extended Register 4A are not automatically cleared following a read. Instead, each flag bit can be cleared to 0 only by writing 0 to that bit. When using the flag bits with fully enabled interrupts, the IRQ line is driven low when an interrupt flag bit is set and
its corresponding enable bit is also set. IRQ is held low as long as at least one of the six possible interrupt sources has its flag and enable bits both set. The IRQF bit in Register C is a 1 whenever the IRQ pin is being driven low as
a result of one of the six possible active sources. Therefore, determination that the DS1685/DS1687 initiated an interrupt is accomplished by reading Register C and finding IRQF = 1. IRQF remains set until all enabled interrupt
flag bits are cleared to 0.
DS1685/DS1687 3V/5V Real-Time Clocks
SQUARE-WAVE OUTPUT SELECTION The SQW pin can be programmed to output a variety of frequencies divided down from the 32.768kHz crystal tied
to X1 and X2. The square-wave output is enabled and disabled by the SQWE bit in Register B or the E32K bit in extended register 4Bh. If the square wave is enabled (SQWE = 1 or E32K = 1), then the output frequency is
determined by the settings of the E32K bit in Extended Register 4Bh and by the RS3–0 bits in Register A. If E32K = 1, then a 32.768kHz square wave is output on the SQW pin regardless of the settings of RS3–0 and SQWE. If E32K = 0, then the square-wave output frequency is determined by the RS3–0 bits. These bits control a 1-of-16
decoder, which selects one of 13 taps that divide the 32.768kHz frequency. The RS3–0 bits establish the SQW output frequency as shown in Table 3. In addition, RS3–0 bits control the periodic interrupt selection as described
below.
If E32K = 1 and the auxiliary-battery enable bit (ABE, bank 1; register 04BH) is enabled, and voltage is applied to VBAUX, then the 32kHz square-wave output signal is output on the SQW pin in the absence of VCC. This facility is
provided to clock external power management circuitry. If any of the above requirements are not met, no square-wave output signal is generated on the SQW pin in the absence of VCC. A pattern of 01X in the DV2, DV1, and DV0 bits respectively turns the oscillator on and enables the countdown
chain. Note that this is different than the DS1287, which required a pattern of 010 in these bits. DV0 is now a “don’t care” because it is used for selection between register banks 0 and 1. A pattern of 11X turns the oscillator on, but the oscillator’s countdown chain is held in reset, as it was in the
DS1287. Any other bit combination for DV2 and DV1 keeps the oscillator off.
OSCILLATOR CONTROL BITS When the DS1687 is shipped from the factory, the internal oscillator is turned off. This feature prevents the lithium energy cell from being used until it is installed in a system. A pattern of 01X in bits 4 through 6 of Register A turns
the oscillator on and enables the countdown chain. A pattern of 11X turns the oscillator on, but holds the countdown chain of the oscillator in reset. All other combinations of bits 4 through 6 keep the oscillator off.
PERIODIC INTERRUPT SELECTION The periodic interrupt causes the IRQ pin to go to an active state from once every 500ms to once every 122�s. This function is separate from the alarm interrupt, which can be output from once per second to once per day. The
periodic interrupt rate is selected using the same RS3–0 bits in Register A, which select the square-wave frequency (Table 3). Changing the bits affects both the square-wave frequency and the periodic-interrupt output.
However, each function has a separate enable bit in Register B. The SQWE and E32K bits control the square-wave output. Similarly, the periodic interrupt is enabled by the PIE bit in Register B. The periodic interrupt can be
used with software counters to measure inputs, create output intervals, or await the next needed software function.
DS1685/DS1687 3V/5V Real-Time Clocks
Table 3. Periodic Interrupt Rate and Square-Wave Output Frequency *RS3–RS0 determine periodic interrupt rates as listed for E32K = 0.
UPDATE CYCLE The RTC executes an update cycle once per second regardless of the SET bit in Register B. When the SET bit in
Register B is set to 1, the user copy of the double-buffered time, calendar, alarm, and elapsed time byte is frozen and does not update as the time increments. However, the time countdown chain continues to update the internal
copy of the buffer. This feature allows the time to maintain accuracy independent of reading or writing the time, calendar, and alarm buffers and also guarantees that time and calendar information is consistent. The update cycle
also compares each alarm byte with the corresponding time byte and issues an alarm if a match or if a “don’t care” code is present in all alarm locations. There are three methods that can handle access of the RTC that avoid any possibility of accessing inconsistent
time and calendar data. The first method uses the update-ended interrupt. If enabled, an interrupt occurs after every update cycle that indicates that over 999ms is available to read valid time and date information. If this
interrupt is used, the IRQF bit in Register C should be cleared before leaving the interrupt routine.
A second method uses the UIP bit in Register A to determine if the update cycle is in progress. The UIP bit pulses
once per second. After the UIP bit goes high, the update transfer occurs 244�s later. If a low is read on the UIP bit,
the user has at least 244�s before the time/calendar data is changed. Therefore, the user should avoid interrupt
service routines that would cause the time needed to read valid time/calendar data to exceed 244�s.
The third method uses a periodic interrupt to determine if an update cycle is in progress. The UIP bit in Register A is set high between the setting of the PF bit in Register C (Figure 4). Periodic interrupts that occur at a rate of
greater than tBUC allow valid time and date information to be reached at each occurrence of the periodic interrupt. The reads should be complete within (tPI / 2 + tBUC) to ensure that data is not read during the update cycle.
DS1685/DS1687 3V/5V Real-Time Clocks
Figure 4. Update-Ended And Periodic-Interrupt Relationship
EXTENDED FUNCTIONS The extended functions provided by the DS1685/DS1687 that are new to the RAMified RTC family are accessed by a software-controlled bank-switching scheme, as illustrated in Figure 5. In bank 0, the clock/calendar registers and
50 bytes of user RAM are in the same locations as for the DS1287. As a result, existing routines implemented within BIOS, DOS, or application software packages can gain access to the DS1685/DS1687 clock registers with
no changes. Also in bank 0, an extra 64 bytes of RAM are provided at addresses just above the original locations for a total of 114 directly addressable bytes of user RAM.
