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DS1678S+
Real-Time Event Recorder
GENERAL DESCRIPTION The DS1678 real-time clock (RTC) event recorder
records the time and date of a nonperiodic,
asynchronous event each time the INT pin is
activated. The device records the seconds, minutes,
hours, date, day of the week, month, year, and
century when the first event occurs, and starts the 16-
bit elapsed time counter (ETC). Subsequent events
trigger the recording of the ETC into the event-log
memory. This allows for up to 1025 events to be
logged. Events can be logged while the device is
operating from either VCC or VBAT.
PIN CONFIGURATION
FEATURES
Real-Time Clock/Calendar in Binary-Coded Decimal (BCD) Format Counts Seconds, Minutes, Hours, Date, Month, Day of the Week, and Year with Leap Year Compensation and is Year 2000 Compliant
Logs Up to 1025 Consecutive Events in Read-Only Battery-Backed Memory
User-Programmable Event Trigger can be Triggered by the Falling Edge, Rising Edge, or Rising and Falling Edges of the INT Pin
Event Counter Register Provides Data on the Number of Events that Have Been Logged in the Current Event-Logging Mission
Programmable RTC Alarm
32-Byte, Battery-Backed, General-Purpose NV RAM
I2C* Serial Interface
Three Resolution Options for Trade-Off Accuracy vs. Maximum Time Between Events
-40C to +85C Industrial Temperature Range
Underwriters Laboratory (UL) Recognized
ORDERING INFORMATION
PART†
PIN-PACKAGE TOP MARK††
DS1678 8 Plastic DIP DS1678
DS1678+ 8 Plastic DIP DS1678
DS1678S 8 SO DS1678S
DS1678S+ 8 SO DS1678S
DS1678S/T&R 8 SO (Tape and
Reel) DS1678S
DS1678S+T&R8 SO (Tape and
Reel) DS1678S All devices are specified over the -40°C to +85°C operating range. †† A “‘+” anywhere on the top mark denotes a lead(Pb)-free device.
+ Denotes a lead(Pb)-free/RoHS-compliant device.
* I2CI2Cs fd AI2C
DS1678
Real-Time Event Recorder
TOP VIEW
4 5
VBAT
VCC
GND
INT
SCL
SDA
X2
X1
DS1678
PDIP (300 mils)
TYPICAL OPERATING CIRCUIT
DS1678 Real-Time Event Recorder
ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………………..-0.3V to +6.0V
Operating Temperature Range (noncondensing)…………………………………………...-40°C to +85°C
Storage Temperature Range…………………………………………………………….…-55°C to +125°C
Soldering Temperature………………………………………….See IPC/JEDEC J-STD-020 Specification
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device
reliability.
RECOMMENDED DC OPERATING CONDITIONS (VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at nominal
supply voltage and TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Power-Supply Voltage VCC (Note 2) 4.5 5.0 5.5 V
Input Logic 1 VIH (Note 2) 2.2 VCC +
0.3 V
Input Logic 0 VIL (Note 2) -0.3 +0.8 V
Pullup Resistor Value VPU VCC = 0V (Note 2) 5.5 V
Battery Voltage VBAT (Note 2) 2.6 3.5 V
DC ELECTRICAL CHARACTERISTICS (VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSSDA, SCL SDA output off -1 +1 Input Leakage
INT
ILI
INT output off 10 A
Logic 0 Output
IOL = 4mA (SDA, INT) VOL 0.4 V
Active Supply Current ICCA 1 2 mA
Power-Fail Voltage (Note 2) VPF VBAT = 3.0V 1.216
x VBAT
1.25 x
VBAT
1.284
x VBAT V
LOBAT Trip Point LOBATTRP 1.35
DC ELECTRICAL CHARACTERISTICS (VCC = 0V, TA = -40°C to +85°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSVBAT Current
(Oscillator On) IOSC 300 500 nA
VBAT Current
(Oscillator Off) IBAT 50 150 nA
DS1678 Real-Time Event Recorder
AC ELECTRICAL CHARACTERISTICS (VCC= 2.6V to 5.5V or VBAT = 2.6V to 3.5V, TA = -40°C to +85°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Capacitance CI INT 10 pF
Minimum Signal Width tGLITCH 0.122 0.245 ms
Minimum Event Rate tEVENT 0.854 1.22 ms
AC ELECTRICAL CHARACTERISTICS (VCC = 4.5V to 5.5V, TA = -40C to +85C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAXUNITS Fast mode 100 400 SCL Clock Frequency fSCL Standard mode 100 kHz
Fast mode 1.3 Bus Free Time Between a STOP and
START Condition tBUF Standard mode 4.7 s
Fast mode 0.6 Hold Time (Repeated) START
Condition (Note 3) tHD:STA Standard mode 4.0 s
Fast mode 1.3 LOW Period of SCL tLOW Standard mode 4.7 s
Fast mode 0.6 HIGH Period of SCL tHIGH Standard mode 4.0 s
Fast mode 0.6 Setup Time for a Repeated START tSU:STA Standard mode 4.7 s
Fast mode 0 0.9 Data Hold Time (Note 4) tHD:DAT Standard mode 0 s
Fast mode 100 Data Setup Time (Note 5) tSU:DAT Standard mode 250 ns
Fast mode 20 + 0.1CB 300 Rise Time of Both SDA and SCL
Signals (Note 6) tR Standard mode 20 + 0.1CB 1000 ns
Fast mode 20 + 0.1CB 300 Fall Time of Both SDA and SCL
Signals (Note 6) tF Standard mode 20 + 0.1CB 300 ns
Fast mode 0.6 Setup Time for STOP tSU:STO Standard mode 4.0 s
Capacitive Load for Each Bus Line
(Note 6) CB 400 pF
Input Capacitance (SCL, SDA) CI 5 pF
WARNING: Under no circumstances are negative undershoots of any amplitude allowed
when the device is in write protect.
DS1678 Real-Time Event Recorder
Note 1: Limits at -40C are guaranteed by design and not production tested.
Note 2: All voltages referenced to ground.
Note 3: After this period, the first clock pulse is generated.
Note 4: A device must initially provide a hold time of at least 300ns for the SDA signal to bridge the undefined region of the falling edge
of SCL. The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 5: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met. This is
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL
line is released.
Note 6: CB—Total capacitance of one bus line in pF.
Note 7: tR and tF are measured with a 1.7kΩ pullup resistor, 200pF pullup capacitor, 1.7kΩ pulldown resistor, and 5pF
pulldown capacitor.
2C COMMUNICATION TIMING DIAGRAM SU:STOt
HD:STAt
tSU:STASU:DATttHIGHttLOW
tHD:STA
SCL
START
SDA
STOP
tBUF
REPEATED
START
tHD:DAT
DS1678 Real-Time Event Recorder
BLOCK DIAGRAM
DATALOG
NV SRAM
1Hz
POWER
CONTROL CC BAT 2C SERIAL
INTERFACE
SCL
SDA
REAL-TIME
CLOCK
7FFh
USER RAM CONTROL
LOGIC INT ADDRESS
REGISTER
000h
DATA LOG RAM
PORT
GND
OSCILLATOR
X1 X2
DIVIDER L C L
Dallas Semiconductor
DS1678
DS1678 Real-Time Event Recorder
PIN DESCRIPTION PIN NAME FUNCTION
1, 2 X1, X2
Connections for Standard 32.768kHz Quartz Crystal. For greatest accuracy,
the DS1678 must be used with a crystal that has a specified load capacitance
of 12.5pF. There is no need for external capacitors or resistors. Note: X1 and
X2 are very high-impedance nodes. It is recommended that they and the
crystal be isolated from high-frequency signals. For more information on
crystal selection and crystal layout considerations, refer to Application Note
58: Crystal Considerations with Dallas Real-Time Clocks.
3 VBAT
Battery Input for Standard Lithium Cell or Other Energy Source. All
functions of the DS1678 with the exception of the serial interface circuitry
are powered by VBAT when VCC < VBAT. All functions are powered by VCC
when VCC > VBAT. The serial interface is enabled when VCC is above VPF. If
a battery or other energy source is not used, VBAT should be connected
directly to ground. Diodes must not be placed between the battery and the
VBAT input or improper operation results. UL recognized to ensure against
reverse charging current when used with a lithium battery. See “Conditions
of Acceptability” at /qa/info/ul/.
4 GND Ground
5 SDA
Serial Data Input/Output. SDA is the data input/output (I/O) signal for the 2C serial interface. The SDA pin is an open-drain I/O and requires an
external pullup resistor.
6 SCL Serial Clock Input. SCL is used to synchronize data movement on the serial
interface. It requires an external pullup resistor. INT
Active-Low Interrupt Input/Output. The INT pin is an I/O that is activated by
an external device to signify an event has occurred and should be logged.
Once the pin is activated, the event is recorded in the event-log memory and
the Event Counter Register is incremented. The TRx bits determine which
input edge(s) trigger an event: An event can be triggered by a falling edge on
the INT pin, a rising edge, or by both the rising and falling edges.
The INT pin can also be used as an output when the DS1678 is not in an
event-logging mission. The INT pin becomes an output and generates an
alarm interrupt if the DISx bits are set to zero and the RTC reaches the preset
value in the alarm register. The INT output remains low as long as the status
bit causing the interrupt is present and the DISx bits are set to zero.
The INT pin is an open-drain input/output with a weak internal pulldown
resistor to prevent the pin from floating when the pin is tri-stated.
8 VCC DC Power for Primary Power Supply
DS1678 Real-Time Event Recorder
DETAILED DESCRIPTION
The Event Counter Register contains the total number of events that have been logged in the current
event-logging mission. The Event Counter Register also allows the user to determine if the data in the
event-log memory has rolled over.
The 16-bit ETC can be incremented once per second, once per minute, or once per hour. Each event
transfers the current ETC value into the event-log memory, then clears and restarts the ETC. The three
increment periods allow users to maximize the resolution while providing an adequate maximum time
between events. The seconds resolution provides the time of an event down to the second, while allowing
up to 65,535 seconds (18.2 hours) between events without using additional event-log memory. The
minutes resolution provides the time of an event down to the minute, while allowing up to 45.5 days
between events without using extra memory locations. The hours resolution provides the time of an event
down to the hour in which it occurred, while allowing up to 7.5 years between events without using
additional event-log memory. Based on the expected frequency of events, an increment period can be
selected to maximize the resolution while minimizing use of the event-log memory.
The event can be triggered in three different ways depending on how the user programs the trigger select
(TRx) bits in the Control Register. The event can be triggered by a falling edge on the INT pin only, a
rising edge only, or it can be triggered by rising and falling edges. Triggering with both the rising and
falling edges allows for monitoring when something is turned on/off and how long it is in either state.
The RTC provides seconds, minutes, hours, day, date, month, and year information with leap-year
compensation, and year 2000 compliance. The RTC also provides an alarm interrupt. The I2C interface
allows the RTC to function as a stand-alone RTC in the system.
The programmable alarm trip points in the RTC allow a flag to be set in the Control Register when the
specified time in the Alarm Trip Point Register is reached. The flag is readable via the I2C interface
during an event-logging mission or, when the DS1678 is not in a mission, INT becomes an output and
generates an alarm interrupt if the value in the RTC equals the value in the RTC Alarm Register and the
duration interval select (DISx) bits are both set to zeros.
The DS1678 operates as a slave device on the I2C serial bus. Access is obtained by generating a START
condition and providing a device identification code. All data is transferred to and from the DS1678 most
significant bit (MSB) first. The address counter automatically increments so that subsequent registers can
be accessed sequentially until a STOP condition is executed. When VCC falls below 1.25 x VBAT, the
device automatically write protects itself by disabling the I2C interface, terminates any access in progress,
and resets the device address counter. Inputs to the device via the I2C bus are not recognized at this time
in order to prevent erroneous data from being written to the device from an out-of-tolerance system.
When VCC falls below VBAT, the device switches into a low-current battery-backup mode. Upon power-
up, the device switches from battery power to VCC when VCC is greater than VBAT + 0.2V, and recognizes
inputs from the system when VCC is greater than 1.25 x VBAT by releasing control of the write protection
on the I2C bus.
The Block Diagram shows the main elements of the RTC event recorder. The device has four major
components: a 64-bit RTC and control block, 32-byte user NV RAM, 2048 bytes of event-log memory
(1024 events), and an I2C serial interface.
DS1678 Real-Time Event Recorder
POWER CONTROL
The device is fully accessible and data can be written and read when VCC is greater than VPF. However,
when VCC falls below VPF, the internal registers are blocked from any access. The device power is
switched from VCC to VBAT when VCC drops below VBAT. Operation, except for the I2C interface, is
maintained from the VBAT source until VCC is returned to nominal levels (Table 1). After VCC returns
above VPF, read and write access is allowed.
Table 1. Power Control
SUPPLY CONDITION READ/WRITE ACCESS POWERED BY
VCC < VPF, VCC < VBAT No VBAT
VCC < VPF, VCC > VBAT No VCC
VCC > VPF, VCC > VBAT Yes VCC
OSCILLATOR CIRCUIT
The DS1678 uses an external 32.768kHz crystal. The oscillator circuit does not require any external
resistors or capacitors (CL) to operate. Table 2 specifies several crystal parameters for the external crystal,
and the oscillator block in the Block Diagram shows a functional schematic of the oscillator circuit. Using
a crystal with the specified characteristics, the startup time is usually less than one second.
Table 2. Crystal Specifications*
PARAMETER SYMBOL MIN TYP MAX UNITS
Nominal Frequency fO 32.768 kHz
Series Resistance ESR 45 k
Load Capacitance CL 12.5 pF
*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to
Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications.
CLOCK ACCURACY
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match
between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was
trimmed. Additional error is added by crystal frequency drift caused by temperature shifts. External
circuit noise coupled into the oscillator circuit can result in the clock running fast. Figure 1 shows a
typical PC board layout for crystal and oscillator isolation from noise. Refer to Application Note 58:
Crystal Considerations with Dallas Real-Time Clocks for detailed information.
Figure 1. Typical Crystal Layout
LOCAL GROUND PLANE (LAYER 2)
CRYSTAL
X1
X2
GND
DS1678 Real-Time Event Recorder
MEMORY
The memory map in Figure 2 shows the general organization of the DS1678. As can be seen in the figure,
the device memory is in one contiguous segment with a data port to access the event-log memory.
Because the I2C bus is limited to a maximum of 256 addresses (one byte), the DS1678 uses the data port
to access the 2048 bytes of event-log memory. The address that the next data would have been written to
before logging was stopped is stored in the Address Pointer Register LSB (3Fh) and MSB (40h). These
data bytes are used to recover all the data after a rollover occurs. The data log address pointer points to
the oldest event in the memory after a rollover. This is the memory location in event-log memory that
would be overwritten by the next event. Read the data from this point to the end of the memory and the
start time stamp, including the two-byte ETC from the last event. Working backward from the value in
the start time stamp, subtract the value in the ETC from the last event to get the time the last event in the
memory occurred. Then subtract the values in each of the two-byte memory locations for elapsed time
between events to recover the time the previous event occurred.
The value in the ETC register LSB (3Dh) and MSB (3Eh) is the value in the actual ETC. This is the time
from the last event recorded until logging was stopped. Since a new event has not occurred, this data has
not been stored in the event memory yet.
The data port is made up of three bytes. The first byte (41h) is the event-log memory address LSB, the
second byte (42h) is the event-log memory address MSB, and the third byte (43h) is the event-log
memory data byte. To access data via the data port, an I2C write to the LSB of the event log LSB (41h) is
performed, writing the appropriate LSB address information. The I2C register pointer automatically
increments to the event-log memory address MSB (42h), where a second I2C write is performed, writing
the MSB address information. The I2C register pointer automatically increments to the event-log data
byte address (43h). A repeated start, followed by the I2C slave address with a read command (1) in the
R/W bit of the I2C address byte is performed. Subsequent read cycles reads the event-log information in
the event-log memory.
For each read, the event-log memory address pointer in main memory locations 41h and 42h is
autoincremented to the next higher event-log memory address, while the pointer for the main memory
remains at location 43h. This allows the event-log memory to be read continuously without having to
write the next desired event-log memory location prior to each data read. The even address locations in
the event-log memory correspond to the LSB of the elapsed time between events, and the odd memory
locations correspond to the MSB of the elapsed time between events. See Table 3 for more information
about how the data is stored in the event-log memory.
When the event-log memory address pointer gets to the last address location (07FFh), the automatic
incrementing stops. A new starting address must then be written into the event-log memory pointer bytes
(41h and 42h) to begin reading additional data. The event-log memory addresses that can be put into the
pointer (41h and 42h) are 0000h to 07FFh. The five MSBs of the address are ignored. Entering a value
greater than 07FFh results in the address location associated with the value of the lowest 11 bits of the
address.
The RTC and control registers (see Figure 2 for more details) are located in the main memory between
addresses 00h and 0Fh. The user NV RAM resides in locations 10h through 2Fh. The event-logging
memory data port is located at locations 41h, 42h, and 43h. Memory locations 44h and up are reserved for
DS1678 Real-Time Event Recorder
The user can write only to the RTC, control registers, and user NV RAM. The rest of the memory map is
read-only from the user’s perspective. During an event-log mission, all the memory is read-only. A write
terminates the mission. If there is an event being recorded when the mission is terminated, the event
finishes being recorded before the mission is stopped, and the values in the MIP and ME bits do not
change to zeros until the mission is complete.
During an event-log mission, memory locations 30h and above are not accessible to the user to avoid data
collisions from a user read and an event being logged at the same time. If the user tries to read a location
with an address greater than 2Fh during a mission, the value returned is 00h.
Table 3. DS1678 Event Elapsed Time Duration
ADDRESS REGISTER
0000 Event 1 Elapsed Time from Last Event Counter LSB
0001 Event 1 Elapsed Time from Last Event Counter MSB
0002 Event 2 Elapsed Time from Last Event Counter LSB
0003 Event 2 Elapsed Time from Last Event Counter MSB
0004
07FB
07FC Event 1023 Elapsed Time from Last Event Counter LSB
07FD Event 1023 Elapsed Time from Last Event Counter MSB
07FE Event 1024 Elapsed Time from Last Event Counter LSB
07FF Event 1024 Elapsed Time from Last Event Counter MSB
DS1678 Real-Time Event Recorder
Figure 2. DS1678 RTC and Control Page
MSB LSB ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION
00 0 10 Seconds Seconds
01 0 10 Minutes Minutes
AM/PM 02 0 12/24 10 Hr 10 Hr Hour
03 0 0 0 0 0 Day of Week
04 0 0 10 Date Date
05 0 0 0 10 Mo Month
06 10 Year Year
07 10 Century Century
RTC
08 MS 10 Seconds Alarm Seconds Alarm
09 MM 10 Minutes Alarm Minutes Alarm
AM/PM 0A MH 12/24 10 Hr 10 Hr Hour Alarm
0B MD 0 0 0 0 Day-of-Week Alarm
RTC Alarm
0C
0D (Reads 00h) Reserved
0E ME CLR DIS1 DIS0 RO TR1 TR0 EOSC Control
0F 0 MEM
CLR MIP CM LOBAT ROF 0 ALMF Status
10
11
12 ↓
2F
Byte 1
Byte 2
Byte 3 ↓
Byte 32
User-
Programmable
NV Memory
Higher addresses read back as 00h while a mission is in progress.
30 0 10 Seconds Seconds
31 0 10 Minutes Minutes
AM/PM 32 0 12/24 10 Hr 10 Hr Hours
33 0 0 0 0 0 Day-of-Week
34 0 0 10 Date Date
35 0 0 0 10 Mo Month
36 10 Year Year
37 10 Century Century
Time Stamp
38 Event 0 Elapsed Time from Last Event Counter LSB
39 Event 0 Elapsed Time from Last Event Counter MSB
Event 0 Rollover
Stamp
3A Low Byte
3B Medium Byte
3C High Byte
Event Counter
3D Low Byte
3E High Byte
Elapsed Time
Counter (ETC)
3F Low Address Byte
40 High Address Byte Address Pointer
41 Low Address Byte
42 High Address Byte
43 Data Byte
Data Log RAM
Port
44
DS1678 Real-Time Event Recorder
EVENT LOGGING
When the DS1678 event-logging function is enabled, the device is said to be on an “event-log mission”
until the event logging is stopped.
An event can be triggered one of three ways depending on the settings of the TRx bits in the Control
Register. With the TR0 bit set to one and the TR1 bit set to zero, INT is activated on the falling edge of
the input signal. With the TR0 bit set to zero and the TR1 bit set to one, INT is activated on the rising
edge of the input signal. With both TR0 and TR1 bits set to one, INT is activated on both the falling and
rising edges to allow for the measurement and duration of on/off type events. If TR0 and TR1 are both set
to zero, nothing happens when INT is toggled, and a mission does not start. This is an illegal state and the
mission does not start without a valid value in the TRx bits prior to attempting to start the mission.
During an event-log mission, every time INT is activated, the elapsed time from the last event is written
to the event-log memory pages. These memory pages are accessible through the data port in the main
memory. To access data via the data port, the LSB of the address location in the event-log memory is
written into 41h, the main memory address pointer automatically increments to 42h where the event-log
memory address MSB data is written. The data from the event-log memory location corresponding to the
address written into main memory locations 41h and 42h is available in location 43h to be read. The
event-log data is located at addresses 0000h–07FFh in the event-log memory. The LSB of the first event
duration is written to address location 0000h. The MSB of the first event duration is written to address
location 0001h. The LSB of the second event is written to address location 0002h. The MSB of the
second event duration is written to address location 0003h (see Table 3 for more details). Likewise, the
address is incremented with each additional event duration. A total of 2048 registers have been reserved
for event-log data, which allow 1024 events to be logged.
An event-log mission can be initiated by two methods (Figure 3). The first method to start a mission is
with a delayed start. This is accomplished by writing a one to the ME bit. The mission starts when the
first event occurs by activating INT. When INT is activated, the MIP bit in the Status Register is set to
one, the current time/date is written to the Start Time Stamp Register, and the Event 0 Rollover Stamp is
written to zero. The Event Counter Register is incremented and the ETC starts. Subsequent events are
logged as the duration of time from the previous event by writing the contents of the ETC into the event-
log memory when that subsequent event is triggered by the activated INT pin. Note: The ME bit can only
be written to one and a mission started if the MEM CLR bit is set to one.
The second way to start a mission is write a one to the MIP bit of the Status Register over the I2C
interface. When MIP is written to one, the ME bit in the Control Register is automatically set to one.
When the MIP bit is written to one, the mission is started by loading the current time/date into the start
time stamp, and the Event 0 Rollover Stamp is written to zero. The Event Counter Register is
incremented and the ETC starts incrementing. The first event is then logged as the duration of time since
the start time. All subsequent events are then logged as the duration of time since the previous event.
Note: The MIP bit can only be written to one and a mission started if the MEM CLR bit is set to one.
The MEM CLR bit of the Status Register must be a one to start an event-log mission. This means that the
Event-Log Memory, Event Count, ETC, Address Pointer, and Start Time Stamp registers are cleared of
data (all zeros) so that an end user cannot turn the logger on and off to avoid recording events. Once the
mission is stopped, the memory must be cleared to start a new mission.
DS1678 Real-Time Event Recorder
Figure 3. Start Mission Flow Chart
yes
Start via
Computer
Start via
External Event
Mem Clr =1noClear
Memory
Write a 1 to
the MIP bit
The ME bit is
Automatically
Written to a 1
Time/Date Stamp
is Written
ETC Starts
Incrementing
EC is
Incremented
yes
INT Input
ActivatedContinue to
Monitor Input
Record Event in
Event Memory
yes
Mem Clr =1noClear
Memory
Write a 1 to
the ME bit.
MIP = 0
yes
INT Input
ActivatedContinue to
Monitor Input
MIP Automatically
Written to a 1
Time/Date Stamp is
Written
ETC Starts
Incrementing.
EC is
Incremented
yes
INT Input
ActivatedContinue to
Monitor Input
Record Event in
Event Memory
ETC is
ETC is
Cleared
