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DS1673E-3-DS1673S-5
Portable System Controller
FEATURESProvides Real Time Clock:Counts seconds, minutes, hours, date of
the month, month, day of the week, and
year with leap year compensation valid up
to 2100– Power control circuitry supports system
power on from day/time alarmMicroprocessor monitor:Halts microprocessor during power-failAutomatically restarts microprocessorafter power failureMonitors pushbutton for external overrideHalts and resets an out of control
microprocessorNV RAM control:– Automatic battery backup and write
protection to external SRAM3-channel, 8-bit analog-to-digital converterSimple 3-wire interface+3.0 or +5.0V operation
PIN ASSIGNMENT
ORDERING INFORMATIONDS1673E - X 20-Pin TSSOP
DS1673S - X 20-Pin SOIC
3 +3V operation
5 +5V operation
DESCRIPTIONThe Portable System Controller is a circuit which incorporates many of the functions necessary for low
power portable products integrated into one chip. The DS1673 provides a Real Time Clock, NV RAM
controller, microprocessor monitor, and a 3-channel, 8-bit analog-to-digital converter. Communication
with the DS1673 is established through a simple 3-wire interface.
The Real Time Clock (RTC) provides seconds, minutes, hours, day, date, month, and year information
with leap year compensation. The RTC also provides an alarm interrupt. This interrupt works when the
DS1673 is powered by the system power supply or when in battery backup operation so the alarm can be
used to wake up a system that is powered down.
DS1673VBAT
VCCO
SCLK
I/O
CEI
CEOL
CEOH
INT
GND
VCC
RST
BLE
BHE
DS1673
Automatic backup and write protection of external SRAM is provided through the VCCO, CEOL, and
CEOH pins. The backup energy source used to power the RTC is also used to retain RAM data in the
absence of VCC through the VCCO pin. The chip enable outputs to RAM (CEOL and CEOH) are controlled
during power transients to prevent data corruption.
The microprocessor monitor circuitry of the DS1673 provides three basic functions. First, a precision
temperature-compensated reference and comparator circuit monitors the status of VCC. When an out-of-tolerance condition occurs, an internal power-fail signal is generated which forces the reset to the active
state. When VCC returns to an in-tolerance condition, the reset signals are kept in the active state for
250 ms to allow the power supply and processor to stabilize. The second microprocessor monitor
function is pushbutton reset control. The DS1673 debounces a pushbutton input and guarantees an active
reset pulse width of 250 ms. The third function is a watchdog timer. The DS1673 has an internal timerthat forces the reset signals to the active state if the strobe input is not driven low prior to watchdog
time-out.
The DS1673 also provides a 3-channel, 8-bit successive approximation analog-to-digital converter. The
converter has an internal 2.55 volt (typical) reference voltage generated by an on-board band-gap circuit.The A/D converter is monotonic (no missing codes) and has an internal analog filter to reduce high
frequency noise.
OPERATIONThe block diagram in Figure 1 shows the main elements of the DS1673. The following paragraphs
describe the function of each pin.
DS1673 BLOCK DIAGRAM Figure 1
DS1673
SIGNAL DESCRIPTIONS
VCC, GND - DC power is provided to the device on these pins. VCC is the +3.0 volt or +5.0 volt input.
VBAT (Backup Power Supply) - Battery input for standard 3-volt lithium cell or other energy source.
SCLK (Serial Clock Input) - SCLK is used to synchronize data movement on the serial interface.
I/O (Data Input/Output) - The I/O pin is the bi-directional data pin for the 3-wire interface.
CS (Chip Select) - The Chip Select signal must be asserted high during a read or a write for
communication over the 3-wire serial interface.
VCCO (External SRAM Power Supply Output) - This pin is internally connected to VCC when VCC is
within nominal limits. However, during power-fail VCCO is internally connected to the VBAT pin.
Switchover occurs when VCC drops below VCCSW.
INT (Interrupt Output) - The INT pin is an active high output of the DS1673 that can be used as aninterrupt input to a microprocessor. The INT output remains high as long as the status bit causing the
interrupt is present and the corresponding interrupt-enable bit is set. The INT pin operates when the
DS1673 is powered by VCC or VBAT.
CEI (RAM Chip Enable In) - CEI must be driven low to enable the external RAM.
BLE (Byte Low Enable Input) - This pin when driven low activates the CEOL output if CEI is also
driven low.
BHE (Byte High Enable Input) - This pin when driven low activates the CEOH output if CEI is also
driven low.
CEOL (RAM Chip Enable Out Low) – Chip enable output for low order SRAM byte.
CEOH (RAM Chip Enable Out High) – Chip enable output for high order SRAM byte. (Strobe Input) - The Strobe input pin is used in conjunction with the watchdog timer. If the ST pin
is not driven low within the watchdog time period, the RST pin is driven low.
RST (Reset) - The RST pin functions as a microprocessor reset signal. This pin is driven low 1) when
VCC is outside of nominal limits; 2) when the watchdog timer has “timed out”; 3) during the power-up
reset period; and 4) in response to a pushbutton reset. The RST pin also functions as a pushbutton reset
input. When the RST pin is driven low, the signal is debounced and timed such that a RST signal of at
least 250 ms is generated. This pin has an internal 47 kΩ pullup resistor.
AIN0, AIN1, AIN2 (Analog Inputs) - These pins are the three analog inputs for the 3-channel analog-to-digital converter.
DS1673
X1, X2 - Connections for a standard 32.768 kHz quartz crystal. For greatest accuracy, the DS1673 mustbe used with a crystal that has a specified load capacitance of 6 pF. There is no need for external
capacitors or resistors. Note: X1 and X2 are very high impedance nodes. It is recommended that they
and the crystal be guard-ringed with ground and that high frequency signals be kept away from the crystalarea. For more information on crystal selection and crystal layout considerations, please consult
Application Note 58, “Crystal Considerations with Dallas Real Time Clocks.”
The DS1673 will not function without a crystal.
POWER-UP/POWER-DOWN CONSIDERATIONSWhen VCC is applied to the DS1673 and reaches a level greater than VCCTP (power-fail trip point), thedevice becomes fully accessible after tRPU (250 ms typical). Before tRPU elapses, all inputs are disabled.
When VCC drops below VCCSW, the device is switched over to the VBAT supply.
During power-up, when VCC returns to an in-tolerance condition, the RST
pin is kept in the active statefor 250 ms (typical) to allow the power supply and microprocessor to stabilize.
ADDRESS/COMMAND BYTEThe command byte for the DS1673 is shown in Figure 2. Each data transfer is initiated by a command
byte. Bits 0 through 6 specify the address of the registers to be accessed. The MSB (bit 7) is the
Read/Write bit. This bit specifies whether the accessed byte will be read or written. A read operation is
selected if bit 7 is a 0 and a write operation is selected if bit 7 is a one. The address map for the DS1673
is shown in Figure 3.
ADDRESS/COMMAND BYTE Figure 2
DS1673
DS1673 ADDRESS MAP Figure 3
CLOCK, CALENDAR AND ALARMThe time and calendar information is accessed by reading/writing the appropriate register bytes. Notethat some bits are set to 0. These bits will always read 0 regardless of how they are written. Also note
that registers 0Fh to 7Fh are reserved. These registers will always read 0 regardless of how they are
written. The contents of the time, calendar, and alarm registers are in the Binary-Coded Decimal (BCD)
format. The DS1673 can run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as
the 12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5is the AM/PM bit with logic 1 being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20-23
hours).
The DS1673 also contains a time of day alarm. The alarm registers are located in registers 07h to 0Ah.
Bit 7 of each of the alarm registers are mask bits (see Table 1). When all of the mask bits are logic 0, analarm will occur once per week when the values stored in timekeeping registers 00h to 03h match the
values stored in the time of day alarm registers. An alarm will be generated every day when mask bit of
the day alarm register is set to 1. An alarm will be generated every hour when the day and hour alarm
mask bits are set to 1. Similarly, an alarm will be generated every minute when the day, hour, and minute
alarm mask bits are set to 1. When day, hour, minute, and seconds alarm mask bits are set to 1, an alarmwill occur every second.
DS1673
TIME OF DAY ALARM BITS Table 1
SPECIAL PURPOSE REGISTERSThe DS1673 has two additional registers (control register and status register) that control the Real Time
Clock and interrupts.
CONTROL REGISTER
EOSC (Enable Oscillator) - This bit, when set to logic 0 will start the oscillator. When this bit is set to alogic 1, the oscillator is stopped and the DS1673 is placed into a low-power standby mode with a current
drain of less than 200 nanoamps when in battery back-up mode. When the DS1673 is powered by VCC,
the oscillator is always on regardless of the status of the EOSC bit; however, the Real Time Clock is
incremented only when EOSC is a logic 0.
WP (Write Protect) - Before any write operation to the Real Time Clock or any other registers, this bitmust be logic 0. When high, the write protect bit prevents a write operation to any register.
AIS0-AIS1 (Analog Input Select) - These 2 bits are used to determine the analog input for the analog-to-digital conversion. Table 2 lists the specific analog input that is selected by these 2 bits.
AIE (Alarm Interrupt Enable) - When set to a logic 1, this bit permits the Interrupt Request Flag
(IRQF) bit in the status register to assert INT. When the AIE bit is set to logic 0, the IRQF bit does not
initiate the INT signal.
ANALOG INPUT SELECTION Table 2
DS1673
STATUS REGISTER
CU (Conversion Update In Progress) - When this bit is a 1, an update to the ADC Register (register0Eh) will occur within 488 μs. When this bit is a 0, an update to the ADC Register will not occur for at
least 244 μs.
LOBAT (Low Battery Flag) - This bit reflects the status of the backup power source connected to theVBAT pin. When VBAT is greater than 2.5 volts, LOBAT is set to a logic 0. When VBAT is less than
2.3 volts, LOBAT is set to a logic 1.
IRQF (Interrupt Request Flag) - A logic 1 in the Interrupt Request Flag bit indicates that the current
time has matched the time of day Alarm registers. If the AIE bit is also a logic 1, the INT pin will gohigh. IRQF is cleared by reading or writing to any of the alarm registers.
NONVOLATILE SRAM CONTROLLERThe DS1673 provides automatic backup and write protection for external SRAM. This function is
provided by gating the chip enable signals and by providing a constant power supply through the VCCO
pin. The DS1673 was specifically designed with the Intel 80186 and 386EX microprocessors in mind.As such, the DS1673 has the capability to provide access to the external SRAM in either byte-wide or
word-wide format. This capability is provided by the chip enable scheme. Three input signals and two
output signals are used for enabling the external SRAM(s) (see Figure 4). CEI (chip enable in), BHE
(byte high enable), and BLE (byte low enable) are used for enabling either one or two external SRAMs
through the CEOL (chip enable low) and the CEOH (chip enable high) outputs. Table 3 illustrates the
function of these pins.
The DS1673 nonvolatilizes the external SRAM(s) by write-protecting the SRAM(s) and by providing a
back-up power supply in the absence of VCC. When VCC falls below VPF, access to the external SRAM(s)
are prohibited by forcing CEOL and CEOH high regardless of the level of CEI, BLE, and BHE. Upon
power-up, access is prohibited until the end of tRPU.
EXTERNAL SRAM CHIP ENABLE Table 3
DS1673
EXTERNAL SRAM INTERFACE (WORD-WIDE) TO THE DS1673 Figure 4
MICROPROCESSOR MONITORThe DS1673 monitors three vital conditions for a microprocessor: power supply, software execution, and
external override.
First, a precision temperature-compensated reference and comparator circuit monitors the status of VCC.
When an out-of-tolerance condition occurs, an internal power-fail signal is generated which forces the
RST
pin to the active state, thus warning a processor-based system of impending power failure. WhenVCC returns to an in-tolerance condition upon power-up, the reset signal is kept in the active state for
250 ms (typical) to allow the power supply and microprocessor to stabilize. Note, however, that if the
EOSC bit is set to a logic 1 (to disable the oscillator during battery back-up mode), the reset signal will be
kept in an active state for 250 ms plus the start-up time of the oscillator.
The second monitoring function is push-button reset control. The DS1673 provides for a pushbutton
switch to be connected to the RST output pin. When the DS1673 is not in a reset cycle, it continuously
monitors the RST signal for a low going edge. If an edge is detected, the DS1673 will debounce the
switch by pulling the RST line low. After the internal 250 ms timer has expired, the DS1673 will
continue to monitor the RST
line. If the line is still low, the DS1673 will continue to monitor the linelooking for a rising edge. Upon detecting release, the DS1673 will force the RST line low and hold itlow for 250 ms.
The third microprocessor monitoring function provided by the DS1673 is a watchdog timer. The
watchdog timer function forces RST to the active state when the ST input is not stimulated within the
predetermined time period. The time period is set by the Time Delay (TD) bits in the Watchdog Register.
The time delay can be set to 250 ms, 500 ms, or 1000 ms (see Figure 5). If TD0 and TD1 are both set tozero, the watchdog timer is disabled. When enabled, the watchdog timer starts timing out from the set
time period as soon as RST is inactive. The default setting is for the watchdog timer to be enabled with
1000 ms time delay. If a high-to-low transition occurs on the ST input pin prior to time-out, the
watchdog timer is reset and begins to time-out again. If the watchdog timer is allowed to time-out, then
the RST signal is driven to the active state for 250 ms (typical). The ST input can be derived from
DS1673
WATCHDOG TIME-OUT CONTROL Figure 5
WATCHDOG REGISTER
WATCHDOG REGISTER
ANALOG-TO-DIGITAL CONVERTERThe DS1673 provides a 3-channel, 8-bit analog-to-digital converter. The A/D reference voltage (2.55Vtypical) is derived from an on-chip band-gap circuit. Three multiplexed analog inputs are provided
through the AIN0, AIN1, and AIN2 pins. The A/D converter is monotonic (no missing codes) and uses a
successive approximation technique to convert the analog signal into a digital code.
An A/D conversion is the process of assigning a digital code to an analog input voltage. This coderepresents the input value as a fraction of the full-scale voltage (FSV) range. Thus the FSV range is then
divided by the A/D converter into 256 codes (8 bits). The FSV range is bounded by an upper limit equal
to the reference voltage and the lower limit which is ground. The DS1673 has a FSV of 2.55V (typical)
which provides a resolution of 10 mV. An input voltage equal to the reference voltage converts to FFh
while an input voltage equal to ground converts to 00h. The relative linearity of the A/D converter is
±0.5 LSB.
The A/D converter selects from one of three different analog inputs (AIN0 - AIN2). The input that is
selected is determined by the Analog Input Select (AIS) bits in the Control Register. Table 2 lists thespecific analog input that is selected by these 2 bits. Note also that the converter can be turned off by
these bits to reduce power. When the A/D is turned on by setting AIS0 and AIS1 to any value other than
0,0 the analog input voltage is converted and written to the ADC Register within 488 μs. An internal
analog filter at the input reduces high frequency noise. Subsequent updates occur approximately every
10 ms. If AIS0 and/or AIS1 are changed, updates will occur at the next 10 ms conversion time.
The Conversion Update In Progress (CU) bit in the Status Register indicates when the ADC Register can
be read. When this bit is a 1, an update to the ADC Register will occur within 488 μs maximum.
However, when this bit is 0 an update will not occur for at least 244 μs. The CU bit should be polledbefore reading the ADC Register to insure that the contents are stable during a read cycle. Once a read
cycle to the ADC Register has been started, the DS1673 will not update that register until the read cycle
has been completed. It should also be mentioned that taking CS low will abort the read cycle and will
allow the ADC Register to be updated.
Figure 6 illustrates the timing of the CU bit relative to an instruction to begin conversion and the
completion of that conversion.
DS1673
CU BIT TIMING Figure 6
3-WIRE SERIAL INTERFACECommunication with the DS1673 is accomplished through a simple 3-wire interface consisting of the
Chip Select (CS), Serial Clock (SCLK) and Input/Output (I/O) pins.
All data transfers are initiated by driving the CS input high. The CS input serves two functions. First, CSturns on the control logic which allows access to the shift register for the address/command sequence.
Second, the CS signal provides a method of terminating either single byte or multiple byte (burst) data
transfer. A clock cycle is a sequence of a rising edge followed by a falling edge. For data input, data
must be valid during the rising edge of the clock and data bits are output on the falling edge of the clock.
If the CS input goes low, all data transfer terminates and the I/O pin goes to a high impedance state.
Address and data bytes are always shifted LSB first into the I/O pin. Any transaction requires the
address/command byte to specify a read or write to a specific register followed by 1 or more bytes of
data. The address byte is always the first byte entered after CS is driven high. The most significant bitRD/WR) of this byte determines if a read or write will take place. If this bit is 0, one or more read
cycles will occur. If this bit is 1, one or more write cycles will occur.
Data transfers can occur 1 byte at a time or in multiple byte burst mode. After CS is driven high an
address is written to the DS1673. After the address, 1 or more data bytes can be read or written. For asingle-byte transfer 1 byte is read or written and then CS is driven low. For a multiple-byte transfer,
multiple bytes can be read or written to the DS1673 after the address has been written. Each read or write
cycle causes the register address to automatically increment. Incrementing continues until the device is
disabled. After accessing register 0Eh, the address wraps to 00h.
Data transfer for single-byte transfer and multiple-byte burst transfer is illustrated in Figures 7 and 8.
