DS1672S/3-DS1672S-3-DS1672U-33 Fast Delivery |IC PHOENIX CO.,LIMITED

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DS1672S/3-DS1672S-3-DS1672U-33
Low Voltage Serial Timekeeping Chip
FEATURES32-bit counter2-wire serial interfaceAutomatic power-fail detect and switch
circuitryPower-fail reset outputLow-voltage oscillator operation (1.3V min.)Trickle charge capability
ORDERING INFORMATION
DS1672X-X2.0V operation3 3.0V operation
33 3.3V operation
blank8-pin DIP
S8-pin SOIC8-pin µSOP
PIN ASSIGNMENT
PIN DESCRIPTION
VCC, VBACKUP- Power Supply InputsGND- Ground
X1, X2- 32.768 kHz crystal pins
SCL- Serial clock
SDA- Serial data
RST- Reset output
DESCRIPTION
The DS1672 incorporates a 32-bit counter and power monitoring functions. The 32-bit counter isdesigned to count seconds and can be used to derive time of day, week, month, month, and year by usingsoftware algorithm. A precision temperature-compensated reference and comparator circuit monitors
the status of VCC. When an out-of-tolerance condition occurs, an internal power-fail signal is generated
which forces the reset to the active state. When VCC returns to an in-tolerance condition, the reset signal
is kept in the active state for 250 ms to allow the power supply and processor to stabilize.
OPERATION
The block diagram in Figure 1 shows the main elements of the DS1672. As shown, communications to
and from the DS1672 occur serially over a 2-wire bi-directional bus. The DS1672 operates as a slave
device on the serial bus. Access is obtained by implementing a START condition and providing a device
identification code followed by a register address. Subsequent registers can be accessed sequentially untila STOP condition is executed.
DS1672
Low Voltage Serial Timekeeping Chip
VCC
RST
SCL
VBACKUP
GND
DS1672
DS1672 BLOCK DIAGRAM Figure 1
ADDRESS MAP
The counter is accessed by reading or writing the first 4 bytes of the DS1672 (00h - 03h). The control
register and trickle charger are accessed by reading or writing the appropriate register bytes as illustrated
in Figure 2. If the master continues to send or request more data after the address pointer has reached05h, the address pointer will wrap around to location 00h.
DS1672 REGISTERS Figure 2
DATA RETENTION MODE
The device is fully accessible and data can be written and ready only when VCC is greater than VPF.However, when VCC falls below VPF, (point at which write protection occurs) the internal clock registers
are blocked from any access. If VPF is less than VBACKUP, the device power is switched from VCC to
VBACKUP when VCC drops below VPF. If VPF is greater than VBACKUP, the device power is switched from
VCC
VBACKUP
GND
SDA
RST
DS1672
OSCILLATOR CONTROL
The EOSC bit (bit 7 of the control register) controls the oscillator when in back-up mode. This bit whenset to logic 0 will start the oscillator. When this bit is set to a logic 1, the oscillator is stopped and the
DS1672 is placed into a low-power standby mode with a current drain of less than 200 nanoamps when in
back-up mode. When the DS1672 is powered by VCC, the oscillator is always on regardless of the status
of the EOSC bit; however, the counter is incremented only when EOSC is a logic 0.
CRYSTAL SELECTION
A standard 32.768 kHz quartz crystal should be directly connected to the X1 and X2 oscillator pins. The
crystal selected for use should have a specified load capacitance (CL) of 6 pF. For more information oncrystal selection and crystal layout considerations, please consult Application Note 58, “Crystal
Considerations with Dallas Real Time Clocks.”
MICROPROCESSOR MONITOR
A temperature-compensated comparator circuit monitors the level of VCC. When VCC falls to the power-
fail trip point, the RST signal (open drain) is pulled active. When VCC returns to nominal levels, the RST
signal is kept in the active state for 250 ms (typically) to allow the power supply and microprocessor to
stabilize. Note, however, that if the EOSC bit is set to a logic 1 (to disable the oscillator during writeprotection), the reset signal will be kept in an active state for 250 ms plus the start-up time of the
oscillator.
TRICKLE CHARGER
The trickle charger is controlled by the trickle charge register. The simplified schematic of Figure 3
shows the basic components of the trickle charger. The trickle charge select (TCS) bit (bits 4-7) controlsthe selection of the trickle charger. In order to prevent accidental enabling, only a pattern on 1010 will
enable the trickle charger. All other patterns will disable the trickle charger. The DS1672 powers up
with the trickle charger disabled. The diode select (DS) bits (bits 2-3) select whether or not a diode is
connected between VCC and VBACKUP. If DS is 01, no diode is selected or if DS is 10, a diode is selected.
The RS bits (bits 0-1) select whether a resistor is connected between VCC and VBACKUP and what the valueof the resistor is. The resistor selected by the resistor select (RS) bits and the diode selected by the diode
select (DS) bits are as follows:
DS1672
Diode and resistor selection is determined by the user according to the maximum current desired for
battery or super cap charging. The maximum charging current can be calculated as illustrated in the
following example. Assume that a system power supply of 3 volt is applied to VCC and a super cap is
connected to VBACKUP. Also assume that the trickle charger has been enabled with a diode and resistor R2between VCC and VBACKUP. The maximum current Imax would therefore be calculated as follows:
Imax = (3.0V – diode drop) / R2
~ (3.0V – 0.7V) / 2 kΩ
~ 1.2 mA
Obviously, as the super cap changes, the voltage drop between VCC and VBACKUP will decrease and
therefore the charge current will decrease.
DS1672 PROGRAMMABLE TRICKLE CHARGER Figure 3
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
100Ω
TRICKLE CHARGE REGISTER
TCS =TRICKLE CHARGER SELECTDS =DIODE SELECT
RS =RESISTOR SELECT
VCCΩΩ
DS1672
2-WIRE SERIAL DATA BUS
The DS1672 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends
data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that
controls the message is called a “master." The devices that are controlled by the master are “slaves.” The
bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access,
and generates the START and STOP conditions. The DS1672 operates as a slave on the 2-wire bus.Connections to the bus are made via the open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (see Figure 4).
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in thedata line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line from high to low, while the clock line is high,
defines a START condition.
Stop data transfer: A change in the state of the data line from low to high, while the clock line is high,defines a STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the high period of the clock signal. The data on the line must be changed
during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between the START and the STOP conditions is not limited, and is
determined by the master device. The information is transferred byte-wise and each receiver
acknowledges with a ninth bit.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an extra clock pulse which is associated with
this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end of data to the slave
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the master to generate the STOP condition.
DS1672
DATA TRANSFER ON 2-WIRE SERIAL BUS Figure 4
slave address
SDA
SCL
START
CONDITION
acknowledgement
signal from receiver
ACK
repeated if more bytes
are transferred
Figures 5 and 6 detail how data transfer is accomplished on the 2-wire bus. Depending upon the state of
the R/W bit, two types of data transfer are possible:
1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the
master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge
bit after each received byte.
2. Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) istransmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last received byte, a ‘not acknowledge’ is returned.
The master device generates all of the serial clock pulses and the START and STOP conditions. Atransfer is ended with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the bus will not be released.
The DS1672 may operate in the following two modes:
1. Slave receiver mode (DS1672 write mode): Serial data and clock are received through SDA and
SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions
are recognized as the beginning and end of a serial transfer. Address recognition is performed by
hardware after reception of the slave address and direction bit. The address byte is the first byte
received after the START condition is generated by the master. The address byte contains the 7-bit
DS1672 address, which is 1101000, followed by the direction bit (R/W), which for a write is a 0.After receiving and decoding the address byte the DS1672 outputs an acknowledge on the SDA line.
After the DS1672 acknowledges the slave address + write bit, the master transmits a register address
to the DS1672. This will set the register pointer on the DS1672. The master will then begin
transmitting each byte of data with the DS1672 acknowledging each byte received. The master willgenerate a STOP condition to terminate the data write.
2. Slave transmitter mode (DS1672 read mode): The first byte is received and handled as in the slave
receiver mode. However, in this mode, the direction bit will indicate that the transfer direction is
reversed. Serial data is transmitted on SDA by the DS1672 while the serial clock is input on SCL.START and STOP conditions are recognized as the beginning and end of a serial transfer. Address
DS1672
(R/W), which for a read is a 1. After receiving and decoding the address byte the DS1672 inputs an
Acknowledge on the SDA line. The DS1672 then begins to transmit data starting with the register
address pointed to by the register pointer. If the register pointer is not written to before the initiation
of a read mode the first address that is read is the last one stored in the register pointer. The DS1672
must receive a not acknowledge to end a read.
DATA WRITE – SLAVE RECEIVER MODE Figure 5
DATA READ – SLAVE TRANSMITTER MODE Figure 6

Partno	Mfg	Dc	Qty	Available	Descript
DS1672S/3 \|DS1672S3	MAX	N/a	7	avai	Low Voltage Serial Time Keeping Chip
DS1672S-3 \|DS1672S3	MAXIM	N/a	461	avai	Low Voltage Serial Time Keeping Chip
DS1672U-33 \|DS1672U33	DALLAS	N/a	450	avai	Low Voltage Serial Timekeeping Chip
DS1672U-33 \|DS1672U33	MAXIN	N/a	2942	avai	Low Voltage Serial Timekeeping Chip