DS1646/120+ ,Nonvolatile Timekeeping RAMFEATURES PIN CONFIGURATIONS Integrates NV SRAM, Real-Time Clock, N.C. 1 32 V CC Crystal, Power-F ..
DS1646-120+ ,Nonvolatile Timekeeping RAMFEATURES PIN CONFIGURATIONS Integrates NV SRAM, Real-Time Clock, N.C. 1 32 V CC Crystal, Power-F ..
DS1647 ,Nonvolatile Timekeeping RAMFEATURES PIN CONFIGURATIONS Integrates NV SRAM, Real-Time Clock, TOP VIEW Crystal, Power-Fail Co ..
DS1647-120+ ,Nonvolatile Timekeeping RAM19-5596; Rev 10/10 DS1647/DS1647P Nonvolatile Timekeeping RAM
DS1647P-120 ,Nonvolatile Timekeeping RAMFEATURES PIN CONFIGURATIONS Integrates NV SRAM, Real-Time Clock, TOP VIEW Crystal, Power-Fail Co ..
DS1647P-120 ,Nonvolatile Timekeeping RAMFEATURES PIN CONFIGURATIONS Integrates NV SRAM, Real-Time Clock, TOP VIEW Crystal, Power-Fail Co ..
DTTI5516AUA ,DTTI5516 SINGLE MODULE DEMODULATOR AND DECODER IC FOR DIGITAL VIDEO SET-TOP BOXES Data Briefing®DTTi5516Single module demodulator and decoder ICfor digital video set-top boxesDATA BRIEFDescripti ..
DTV110 ,CRT HORIZONTAL DEFLECTION HIGH VOLTAGE DAMPER DIODEFEATURES AND BENEFITSHIGH BREAKDOWN VOLTAGE CAPABILITYISOWATT220ACTO-220ACVERY FAST RECOVERY DIODED ..
DTV110F ,CRT HORIZONTAL DEFLECTION HIGH VOLTAGE DAMPER DIODEFEATURES AND BENEFITSHIGH BREAKDOWN VOLTAGE CAPABILITYISOWATT220ACTO-220ACVERY FAST RECOVERY DIODED ..
DTV1500 ,CRT HORIZONTAL DEFLECTION HIGH VOLTAGE DAMPER DIODEABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Repetitive peak reverse voltage 1500 VRRMI RMS ..
DTV1500H ,HIGH VOLTAGE DAMPER DIODE (CRT HORIZONTAL DEFLECTION)ABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Repetitive peak reverse voltage 1500 VRRMI RMS ..
DTV1500HD ,HIGH VOLTAGE DAMPER DIODE (CRT HORIZONTAL DEFLECTION)ABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Repetitive peak reverse voltage 1500 VRRMI RMS ..
DS1646/120+-DS1646-120+
Nonvolatile Timekeeping RAM
FEATURES Integrates NV SRAM, Real-Time Clock, Crystal, Power-Fail Control Circuit and Lithium Energy Source Clock Registers are Accessed Identically to the Static RAM. These Registers are Resident in the Eight Top RAM Locations Totally Nonvolatile with Over 10 Years of Operation in the Absence of Power BCD-Coded Year, Month, Date, Day, Hours, Minutes, and Seconds with Leap Year Compensation Valid Up to 2100 Power-Fail Write Protection Allows for ±10% VCC Power Supply Tolerance DS1646 only (DIP Module) Standard JEDEC Bytewide 128k x 8 RAM Pinout DS1646P Only (PowerCap Module Board)
Surface Mountable Package for Direct Connection to PowerCap Containing Battery and Crystal Replaceable Battery (PowerCap) Power-Fail Output Pin-for-Pin Compatible with Other Densities of DS164xP Timekeeping RAM Underwriters Laboratories (UL) Recognized
PIN CONFIGURATIONS
ORDERING INFORMATION
PART VOLTAGE RANGE (V) TEMP RANGE PIN-PACKAGE TOP MARK
DS1646-120+ 5.0 0°C to +70°C 32 EDIP (0.740a) DS1646+120
DS1646P-120+ 5.0 0°C to +70°C 34 PowerCap* DS1646P+120 +Denotes a lead(Pb)-free/RoHS-compliant package. *DS9034-PCX+ or DS9034I-PCX+ required (must be ordered separately).
A “+" indicates a lead(Pb)-free product. The top mark will include a “+" symbol on lead(Pb)-free devices. N.C. 2 3 A15 A16
PFO VCC
WE
OE CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND 5 6 7 8 9 10 11 12 13 14 15 16 17
N.C. A14 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18
A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
34 N.C.
X1 GND VBAT X2
34-Pin PowerCap Module Board (Uses DS9034PCX+ or DS9034I-PCX+ PowerCap)
13 4 8 10
11 12
14
31
32-Pin Encapsulated Package A14 A7 A5
A4
A3
A2
A1
A0
DQ1
DQ0
VCC A15
N.C.
WE
A13
A8 A9
A11
OE
A10
CE
DQ7
DQ5
DQ6
32
30 29
28
27
26 25
24 23
22 21
19
20 A16
A12
A6
N.C.
DQ2
GND
15
16
18
17
DQ4
DQ3
DS1646/DS1646P Nonvolatile Timekeeping RAM
19-5595; Rev 10/10
DS1646/DS1646P
PIN DESCRIPTION PIN NAME FUNCTION PDIP PowerCap 1, 30 1, 33, 34 N.C. No Connection 2 3 A16
Address Input 32 A14 4 30 A12 5 25 A7 6 24 A6 7 23 A5 8 22 A4 9 21 A3 10 20 A2 11 19 A1 12 18 A0 25 29 A11 26 27 A9 27 26 A8 28 31 A13 13 16 DQ0
Data Input/Output
14 15 DQ1 15 14 DQ2 17 13 DQ3 18 12 DQ4 19 11 DQ5 20 10 DQ6 21 9 DQ7 16 17 GND Ground 22 8 CE Active-Low Chip Enable 23 28 A10 Address Input 24 7 OE Active-Low Output Enable 29 6 WE Active-Low Write Enable 31 2 A15 Address Input 32 5 VCC Power-Supply Input 4 PFO Active-Low Power-Fail Output, Open Drain. Requires a pullup resistor for proper operation. X1, X2, VBAT Crystal Connection, VBAT Battery Connection
DS1646/DS1646P
DESCRIPTION The DS1646 is a 128k x 8 nonvolatile static RAM with a full-function real time clock, which are both accessible in a byte-wide format. The nonvolatile timekeeping RAM is functionally equivalent to any JEDEC standard 128k x 8 SRAM. The device can also be easily substituted for ROM, EPROM and EEPROM, providing read/write nonvolatility and the addition of the real time clock function. The real time clock information resides in the eight uppermost RAM locations. The RTC registers contain year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day of the month and leap year are made automatically. The RTC clock registers are double-buffered to avoid access of incorrect data that can occur during clock update cycles. The double-buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The DS1646 also contains its own power-fail circuitry, which deselects the device when the VCC supply is in an out-of-tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by low VCC as errant access and update cycles are avoided.
PACKAGES The DS1646 is available in two packages: 32-pin DIP and 34-pin PowerCap module. The 32-pin DIP style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX) that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the DS1646P after the completion of the surface mount process. Mounting the PowerCap after the surface mount process prevents damage to the crystal and battery due to the high temperatures required for solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap are ordered separately and shipped in separate containers. The part number for the PowerCap is DS9034PCX.
CLOCK OPERATIONS—READING THE CLOCK While the double-buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1646 clock registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock register updating process does not affect clock accuracy. Updating is halted when a 1 is written into the read bit, the 7th most significant bit in the control register. As long as 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count, that is day, date, and time that was present at the moment the halt command was issued. However, the internal clock registers of the double-buffered system continue to update so that clock accuracy is not affected by the access of data. All of the DS1646 registers are updated simultaneously after the clock status is reset. Updating is within a second after the read bit is written to 0.
DS1646/DS1646P
BLOCK DIAGRAM DS1646 Figure 1 TRUTH TABLE DS1646 Table 1
VCC CE OE WE MODE DQ POWER 5V ± 10%
VIH X X DESELECT HIGH-Z STANDBY X X X DESELECT HIGH-Z STANDBY VIL X VIL WRITE DATA IN ACTIVE VIL VIL VIH READ DATA OUT ACTIVE VIL VIH VIH READ HIGH-Z ACTIVE <4.5V >VBAT X X X DESELECT HIGH-Z CMOS STANDBY
SETTING THE CLOCK The MSB Bit, B7, of the control register is the write bit. Setting the write bit to a 1, like the read bit halts updates to the DS1646 registers. The user can then load them with the correct day, date and time data in 24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock counters and allows normal operation to resume. STOPPING AND STARTING THE CLOCK OSCILLATOR The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The OSC bit is the MSB for the second’s registers. Setting it to a 1 stops the oscillator. FREQUENCY TEST BIT Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the oscillator is running, the LSB of the second’s register will toggle at 512 Hz. When the seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for access
remain valid (i.e., CE low, OE low, and address for seconds register remain valid and stable).
DS1646/DS1646P
CLOCK ACCURACY (DIP MODULE) The DS1646 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The RTC is calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require additional calibration. For this reason, methods of field clock calibration are not available and not necessary. Clock accuracy is also affected by the electrical environment and caution should be taken to place the RTC in the lowest level EMI section of the PCB layout. For additional information refer to Application Note 58. CLOCK ACCURACY (POWERCAP MODULE) The DS1646 and DS9034PCX are each individually tested for accuracy. Once mounted together, the module will typically keep time accuracy to within ±1.53 minutes per month (35 ppm) at 25°C. Clock accuracy is also affected by the electrical environment and caution should be taken to place the RTC in the lowest level EMI section of the PCB layout. For additional information refer to Application Note 58. 1646 REGISTER MAP—BANK1 Table 2
ADDRESS DATA FUNCTION B7 B6 B5 B4 B3 B2 B1 B0 1FFFF — — — — — — — — Year 00–99 1FFFE X X X — — — — — Month 01–12 1FFFD X X - — — — — — Date 01–31 1FFFC X FT X X X — — — Day 01–07 1FFFB X X — — — — — — Hour 00–23 1FFFA X — — — — — — — Minutes 00–59
1FFF9 OSC — — — — — — — Seconds 00–59
1FFF8 W R X X X X X X Control A
OSC = Stop Bit R = Read Bit FT = Frequency Test
W = Write Bit X = Unused Note: All indicated “X” bits are unused but must be set to “0” during write cycles to ensure proper clock operation. RETRIEVING DATA FROM RAM OR CLOCK
The DS1646 is in the read mode whenever WE (write enable) is high; CE (chip enable) is low. The device architecture allows ripple-through access to any of the address locations in the NVSRAM. Valid
data will be available at the DQ pins within tAA after the last address input is stable, providing that the CE
and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be available at the latter of chip-enable access (tCEA) or at output enable access time (tOEA). The state of the
data input/output pins (DQ) is controlled by CE and OE. If the outputs are activated before tAA, the data
lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate until the next address access.
DS1646/DS1646P
WRITING DATA TO RAM OR CLOCK
The DS1646 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring high to low transition of WE and CE. The addresses must be held valid
throughout the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH
afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be
active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the outputs tWEZ after WE goes active. DATA RETENTION MODE When VCC is within nominal limits (VCC > 4.5 volts) the DS1646 can be accessed as described above with read or write cycles. However, when VCC is below the power-fail point VPF (point at which write protection occurs) the internal clock registers and RAM are blocked from access. This is accomplished
internally by inhibiting access via the CE signal. At this time the power-fail output signal (PFO) will be driven active low and will remain active until VCC returns to nominal levels. When VCC falls below the level of the internal battery supply, power input is switched from the VCC pin to the internal battery and clock activity, RAM, and clock data are maintained from the battery until VCC is returned to nominal level.
