DS1644-120 ,32K x 8 nonvolatile timekeeping static RAM, 120ns accessPIN DESCRIPTIONcalibratedA0–A14 – Address InputCE – Chip Enable• BCD coded year, month, date, day, ..
DS1644-120 ,32K x 8 nonvolatile timekeeping static RAM, 120ns accessDS1644LPMDS1644LPMNonvolatile Timekeeping RAM
DS1644-120 ,32K x 8 nonvolatile timekeeping static RAM, 120ns access DS1644/DS1644P Nonvolatile Timekeeping RAM
DS1644-120 ,32K x 8 nonvolatile timekeeping static RAM, 120ns accessBLOCK DIAGRAM Figure 1CLOCKOSCILLATOR AND REGISTERS32.768 KHzCLOCK COUNTDOWNCHAINCEWE32K X 8NV SRAM ..
DS1644-120+ ,Nonvolatile Timekeeping RAMPIN DESCRIPTION PIN NAME FUNCTION PDIP PowerCap 1 32 A14 2 30 A12 3 25 A7 4 24 A6 5 23 A5 Address I ..
DS1644L-120 ,Nonvolatile Timekeeping RAM BLOCK DIAGRAM Figure 1CLOCKOSCILLATOR AND REGISTERS32.768 KHzCLOCK COUNTDOWNCHAINCEWE32K X 8NV SRAM ..
DTTI5516AUA ,DTTI5516 SINGLE MODULE DEMODULATOR AND DECODER IC FOR DIGITAL VIDEO SET-TOP BOXES Data Briefing®DTTi5516Single module demodulator and decoder ICfor digital video set-top boxesDATA BRIEFDescripti ..
DTV110 ,CRT HORIZONTAL DEFLECTION HIGH VOLTAGE DAMPER DIODEFEATURES AND BENEFITSHIGH BREAKDOWN VOLTAGE CAPABILITYISOWATT220ACTO-220ACVERY FAST RECOVERY DIODED ..
DTV110F ,CRT HORIZONTAL DEFLECTION HIGH VOLTAGE DAMPER DIODEFEATURES AND BENEFITSHIGH BREAKDOWN VOLTAGE CAPABILITYISOWATT220ACTO-220ACVERY FAST RECOVERY DIODED ..
DTV1500 ,CRT HORIZONTAL DEFLECTION HIGH VOLTAGE DAMPER DIODEABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Repetitive peak reverse voltage 1500 VRRMI RMS ..
DTV1500H ,HIGH VOLTAGE DAMPER DIODE (CRT HORIZONTAL DEFLECTION)ABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Repetitive peak reverse voltage 1500 VRRMI RMS ..
DTV1500HD ,HIGH VOLTAGE DAMPER DIODE (CRT HORIZONTAL DEFLECTION)ABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Repetitive peak reverse voltage 1500 VRRMI RMS ..
DS1644-120-DS1644L-120-DS1644L-120.
Nonvolatile Timekeeping RAM
Copyright 1995 by Dallas Semiconductor Corporation.All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer toDallas Semiconductor data books.
DS1644LPMNonvolatile Timekeeping RAM
DS1644LPM
041697 1/11
FEATURESUpward compatible with the DS1643AL Timekeeping
RAM to achieve higher RAM densityIntegrated NV SRAM, real time clock, crystal, power–
fail control circuit and lithium energy sourceLow profile socketable module255 mil package heightClock registers are accessed identical to the static
RAM. These registers are resident in the eight top
RAM locations.Totally nonvolatile with over 10 years of operation in
the absence of powerAccess time of 120 ns and 150 nsQuartz accuracy ±1 minute a month @ 25°C, factory
calibratedBCD coded year, month, date, day, hours, minutes,
and seconds with leap year compensation valid up to
2100Power–fail write protection allows for ±10% VCC pow-
er supply tolerance
ORDERING INFORMATIONDS1644L–XXX
–120120 ns access150 ns access–150
Low Profile Module
PIN ASSIGNMENTPFO
VCC
A14
A13
A12
A11
A10
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
34–PIN LOW PROFILE MODULE
PIN DESCRIPTIONA0–A14–Address Input–Chip Enable–Output Enable–Write Enable
VCC–+5 Volts
GND–Ground
DQ0-DQ7–Data Input/Output–No Connection
PFO–Power Fail Output
DESCRIPTIONThe DS1644L is a low profile module that requires a
PLCC surface mountable socket and is functionally
equivalent to the DS1644. The DS1644L is a 32K x 8
nonvolatile static RAM with a full function real time clock
which are both accessible in a Byte–wide format. The
real time clock information resides in the eight upper-
most RAM locations. The RTC registers contain year,
month, date, day, hours, minutes, and seconds data in
24 hour BCD format. Corrections for the day of the
month and leap year are made automatically. The RTC
clock registers are double buffered to avoid access of in-
correct data that can occur during clock update cycles.
The double buffered system also prevents time loss as
the timekeeping countdown continues unabated by ac-
cess to time register data. The DS1644L also contains
its own power–fail circuitry which deselects the device
when the VCC supply is in an out–of–tolerance condi-
tion. This feature prevents loss of data from unpredict-
able system operation brought on by low VCC as errant
access and update cycles are avoided.
DS1644LPM
041697 2/11
CLOCK OPERATIONS –
READING THE CLOCKWhile the double buffered register structure reduces the
chance of reading incorrect data, internal updates to the
DS1644L clock registers should be halted before clock
data is read to prevent reading of data in transition.
However, halting the internal clock register updating
process does not affect clock accuracy. Updating is
halted when a one is written into the read bit, the seventh
most significant bit in the control register. As long as a
one remains in that position, updating is halted. After a
halt is issued, the registers reflect the count, that is day,
date, and time that was current at the moment the halt
command was issued. However, the internal clock reg-
isters of the double buffered system continue to update
so that the clock accuracy is not affected by the access
of data. All of the DS1644L registers are updated simul-
taneously after the clock status is reset. Updating is
within a second after the read bit is written to zero.
DS1644L BLOCK DIAGRAM Figure 132.768 KHz
PFO
VBAT
DS1644LPM
041697 3/11
DS1644L TRUTH TABLE Table 1
SETTING THE CLOCKThe eighth bit of the control register is the write bit. Set-
ting the write bit to a one, like the read bit, halts updates
to the DS1644L registers. The user can then load them
with the correct day, date and time data in 24 hour BCD
format. Resetting the write bit to a zero then transfers
those values to the actual clock counters and allows
normal operation to resume.
STOPPING AND STARTING THE CLOCK
OSCILLATORThe clock oscillator may be stopped at any time. To in-
crease the shelf life, the oscillator can be turned off to
minimize current drain from the battery. The OSC bit is
the MSB for the seconds registers. Setting it to a one
stops the oscillator.
FREQUENCY TEST BITBit 6 of the day byte is the frequency test bit. When the
frequency test bit is set to logic “1” and the oscillator is
running, the LSB of the seconds register will toggle at
512 Hz. When the seconds register is being read, the
DQ0 line will toggle at the 512 Hz frequency as long as
conditions for access remain valid (i.e., CE low, OE low,
and address for seconds register remain valid and
stable).
CLOCK ACCURACYThe DS1644L is guaranteed to keep time accuracy to
within ±1 minute per month at 25°C. The clock is cali-
brated at the factory by Dallas Semiconductor using
special calibration nonvolatile tuning elements. The
DS1644L does not require additional calibration, and
temperature deviations will have a negligible effect in
most applications. For this reason, methods of field
clock calibration are not available and not necessary.
Attempts to calibrate the clock that may be used with
similar device types (MK48T08 family) will not have any
effect even though the DS1644L appears to accept cal-
ibration data.
DS1644LPM
041697 4/11
DS1644L REGISTER MAP – BANK1 Table 2OSC=STOP BITR=READ BITFT=FREQUENCY TEST=WRITE BITX=UNUSED
NOTE:All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCKThe DS1644L is in the read mode whenever WE (write
enable) is high, and CE (chip enable) is low. The device
architecture allows ripple-through access to any of the
address locations in the NV SRAM. Valid data will be
available at the DQ pins within tAA after the last address
input is stable, providing that the CE and OE access
times and states are satisfied. If CE or OE access times
are not met, valid data will be available at the latter of
chip enable access (tCEA) or at output enable access
time (tOEA). The state of the data input/output pins (DQ)
is controlled by CE and OE. If the outputs are activated
before tAA, the data lines are driven to an intermediate
state until tAA. If the address inputs are changed while
CE and OE remain valid, output data will remain valid for
output data hold time (tOH) but will then go indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCKThe DS1644L is in the write mode whenever WE and
CE are in their active state. The start of a write is refer-
enced to the latter occurring high to low transition of WE
or CE. The addresses must be held valid throughout the
cycle. CE or WE must return inactive for a minimum of
tWR prior to the initiation of another read or write cycle.
Data in must be valid tDS prior to the end of write and re-
main valid for tDH afterward. In a typical application, the
OE signal will be high during a write cycle. However,
OE can be active provided that care is taken with the
data bus to avoid bus contention. If OE is low prior to
WE transitioning low the data bus can become active
with read data defined by the address inputs. A low tran-
sition on WE will then disable the outputs tWEZ after WE
goes active.
DS1644LPM
041697 5/11
DATA RETENTION MODEWhen VCC is within nominal limits (VCC > 4.5 volts) the
DS1644L can be accessed as described above with
read or write cycles. However, when VCC is below the
power fail point VPF (point at which write protection oc-
curs) the internal clock registers and RAM are blocked
from access. This is accomplished internally by inhibit-
ing access via the CE signal. At this time the power–fail
output signal (PFO) will be driven active low and will
remain active until VCC returns to nominal levels. When
VCC falls below the level of the internal battery supply,
power input is switched from the VCC pin to the internal
battery and clock activity, RAM, and clock data are
maintained from the battery until VCC is returned to
nominal level.
INTERNAL BATTERY LONGEVITYThe DS1644L has a self contained lithium power source
that is designed to provide energy for clock activity, and
clock and RAM data retention when the VCC supply is
not present. The capability of this internal power supply
is sufficient to power the DS1644L continuously for the
life of the equipment in which it is installed. For specifi-
cation purposes, the life expectancy is 10 years at 25°C
with the internal clock oscillator running in the absence
of VCC power. The DS1644L is shipped from Dallas
Semiconductor with the clock oscillator turned off, so
the expected life should be considered to start from the
time the clock oscillator is first turned on. Actual life ex-
pectancy of the DS1644L will be much longer than 10
years since no internal lithium battery energy is con-
sumed when VCC is present. In fact, in most applica-
tions, the life expectancy of the DS1644L will be approx-
imately equal to the shelf life (expected useful life of the
lithium battery with no load attached) of the lithium bat-
tery which may prove to be as long as 20 years.
DS1644LPM
041697 6/11
ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground–0.3V to +7.0V
Operating Temperature0°C to 70°C
Storage Temperature–20°C to +70°C
Soldering Temperature260°C for 10 seconds (See Note 7)This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS(0°C to 70°C)
DC ELECTRICAL CHARACTERISTICS(0°C ≤ tA ≤ 70°C; VCC=5.0V ± 10%)
