DS1644P-120 ,Nonvolatile Timekeeping RAM DS1644/DS1644P Nonvolatile Timekeeping RAM
DS1644P-120 ,Nonvolatile Timekeeping RAMFEATURES PIN CONFIGURATIONS VIntegrated NV SRAM, Real-Time Clock, A14 1 28 CC 27 WEA12 2Crystal, ..
DS1644P-120 ,Nonvolatile Timekeeping RAMPIN DESCRIPTION PIN NAME FUNCTION PDIP PowerCap 1 32 A14 2 30 A12 3 25 A7 4 24 A6 5 23 A5 Address I ..
DS1644P-120+ ,Nonvolatile Timekeeping RAMFEATURES PIN CONFIGURATIONS V Integrated NV SRAM, Real-Time Clock, A14 1 28 CC 27 WE2A12Crystal, ..
DS1644P-120+ ,Nonvolatile Timekeeping RAMPIN DESCRIPTION PIN NAME FUNCTION PDIP PowerCap 1 32 A14 2 30 A12 3 25 A7 4 24 A6 5 23 A5 Address I ..
DS1646 ,Nonvolatile Real-Time Clocks RAMFEATURES PIN CONFIGURATIONS Integrates NV SRAM, Real-Time Clock, N.C. 1 32 V CC Crystal, Power-F ..
DTTI5516AUA ,DTTI5516 SINGLE MODULE DEMODULATOR AND DECODER IC FOR DIGITAL VIDEO SET-TOP BOXES Data Briefing®DTTi5516Single module demodulator and decoder ICfor digital video set-top boxesDATA BRIEFDescripti ..
DTV110 ,CRT HORIZONTAL DEFLECTION HIGH VOLTAGE DAMPER DIODEFEATURES AND BENEFITSHIGH BREAKDOWN VOLTAGE CAPABILITYISOWATT220ACTO-220ACVERY FAST RECOVERY DIODED ..
DTV110F ,CRT HORIZONTAL DEFLECTION HIGH VOLTAGE DAMPER DIODEFEATURES AND BENEFITSHIGH BREAKDOWN VOLTAGE CAPABILITYISOWATT220ACTO-220ACVERY FAST RECOVERY DIODED ..
DTV1500 ,CRT HORIZONTAL DEFLECTION HIGH VOLTAGE DAMPER DIODEABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Repetitive peak reverse voltage 1500 VRRMI RMS ..
DTV1500H ,HIGH VOLTAGE DAMPER DIODE (CRT HORIZONTAL DEFLECTION)ABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Repetitive peak reverse voltage 1500 VRRMI RMS ..
DTV1500HD ,HIGH VOLTAGE DAMPER DIODE (CRT HORIZONTAL DEFLECTION)ABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Repetitive peak reverse voltage 1500 VRRMI RMS ..
DS1644+120-DS1644-120 -DS1644P+120-DS1644P-120
Nonvolatile Timekeeping RAM
FEATURES ��Integrated NV SRAM, Real-Time Clock,
Crystal, Power-Fail Control Circuit and
Lithium Energy Source
��Clock Registers are Accessed Identically to the Static RAM. These Registers are
Resident in the Eight Top RAM Locations.
��Totally Nonvolatile with Over 10 Years of
Operation in the Absence of Power
��BCD-Coded Year, Month, Date, Day, Hours, Minutes, and Seconds with Leap Year
Compensation Valid Up to 2100
��Power-Fail Write Protection Allows for
±10% VCC Power Supply Tolerance
��DS1644 Only (DIP Module)
Upward Compatible with the DS1643
Timekeeping RAM to Achieve Higher
RAM Density
Standard JEDEC Bytewide 32k x 8 Static
RAM Pinout
��DS1644P Only (PowerCap® Module Board)
Surface Mountable Package for Direct
Connection to PowerCap Containing
Battery and crystal
Replaceable Battery (PowerCap) Power-Fail Output
Pin-for-Pin Compatible with Other Densities
of DS164XP Timekeeping RAM
Underwriters Laboratory (UL) Recognized
PIN CONFIGURATIONS
ORDERING INFORMATION *DS9034-PCX, DS9034I-PCX, DS9034-PCX+ required (must be ordered separately). NCNCNCVCCDQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ0GNDNC
34-Pin PowerCap Module Board
(Uses DS9034PCX PowerCap)
28-Pin Encapsulated Package
(720-mil Extended)
DQ0
DQ1
GND
DQ2
VCC
DQ7
DQ6
DQ5
DQ3
DQ4
A12
A14
DS1644/DS1644P
Nonvolatile Timekeeping RAMPowerCap is a registered trademark of Dallas Semiconductor.
DS1644/DS1644P
PIN DESCRIPTION DESCRIPTION The DS1644 is a 32k x 8 nonvolatile static RAM with a full function real time clock, which are both
accessible in a byte-wide format. The nonvolatile timekeeping RAM is functionally equivalent to any
JEDEC standard 32k x 8 SRAM. The device can also be easily substituted for ROM, EPROM and
EEPROM, providing read/write nonvolatility and the addition of the real time clock function. The real
time clock information resides in the eight uppermost RAM locations. The RTC registers contain year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day of the
month and leap year are made automatically. The RTC clock registers are double-buffered to avoid access
of incorrect data that can occur during clock update cycles. The double-buffered system also prevents
time loss as the timekeeping countdown continues unabated by access to time register data. The DS1644
also contains its own power-fail circuitry, which deselects the device when the VCC supply is in an out-of-
DS1644/DS1644P
PACKAGES The DS1644 is available in two packages (28-pin DIP and 34-pin PowerCap module). The 28-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1644P after the completion of the surface-mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
CLOCK OPERATIONS—READING THE CLOCK While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1644 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy. Updating is halted when a 1 is written into the read bit, the 7th most significant bit in the control register.
As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the
count, that is day, date, and time that was present at the moment the halt command was issued. However,
the internal clock registers of the double-buffered system continue to update so that the clock accuracy is
not affected by the access of data. All of the DS1644 registers are updated simultaneously after the clock status is reset. Updating is within a second after the read bit is written to 0.
DS1644 BLOCK DIAGRAM Figure 1
DS1644 TRUTH TABLE Table 1
DS1644/DS1644P
SETTING THE CLOCK The MSB Bit, (B7) of the control register is the write bit. Setting the write bit to a 1, like the read bit,
halts updates to the DS1644 registers. The user can then load them with the correct day, date and time data in 24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock
counters and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The OSC bit is the MSB for the seconds registers. Setting it to
a 1 stops the oscillator.
FREQUENCY TEST BIT Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the
oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the seconds register is
being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for access remain valid
(i.e., CE low, OE low, and address for seconds register remain valid and stable).
CLOCK ACCURACY (DIP MODULE) The DS1644 is guaranteed to keep time accuracy to within �1 minute per month at 25�C. The RTC is calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require
additional calibration. For this reason, methods of field clock calibration are not available and not
necessary. Clock accuracy is also affected by the electrical environment and caution should be taken to
place the RTC in the lowest level EMI section of the PCB layout. For additional information please see
application note 58.
CLOCK ACCURACY (POWERCAP MODULE) The DS1644 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within �1.53 minutes per month (35 ppm) at 25°C. Clock
accuracy is also affected by the electrical environment and caution should be taken to place the RTC in
the lowest level EMI section of the PCB layout. For additional information please see application note 58.
DS1644/DS1644P
DS1644 REGISTER MAP—BANK1 Table 2 OSC = STOP BIT R = READ BIT FT = FREQUENCY TEST
W = WRITE BIT X = UNUSED
Note: All indicated “X” bits are unused but must be set to “0” during write cycles to ensure proper clock operation.
RETRIEVING DATA FROM RAM OR CLOCK The DS1644 is in the read mode whenever WE (write enable) is high, and CE (chip enable) is low. The device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid
data will be available at the DQ pins within tAA after the last address input is stable, providing that the CE
and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be
available at the latter of chip enable access (tCEA) or at output enable access time (tOEA). The state of the
data input/output pins (DQ) is controlled by CE and OE. If the outputs are activated before tAA, the data
lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE
remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK The DS1644 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring high to low transition of WE or CE. The addresses must be held valid
throughout the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH
afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be
active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the outputs tWEZ after WE goes active.
DS1644/DS1644P
DATA RETENTION MODE When VCC is within nominal limits (VCC > 4.5 volts) the DS1644 can be accessed as described above with
read or write cycles. However, when VCC is below the power-fail point VPF (point at which write protection occurs) the internal clock registers and RAM are blocked from access. This is accomplished
internally by inhibiting access via the CE signal. At this time the power-fail output signal (PFO) will be
driven active low and will remain active until VCC returns to nominal levels. When VCC falls below the
level of the internal battery supply, power input is switched from the VCC pin to the internal battery and
clock activity, RAM, and clock data are maintained from the battery until VCC is returned to nominal
level.
DS1644/DS1644P
ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………………..-0.3V to +7.0V
Storage Temperature……………………………………………………...-40°C to +85°C, Noncondensing Soldering Temperature……………………………..…+260°C for 10 seconds (DIP Package) (See Note 7)
See IPC/JEDEC Standard J-STD-020A for Surface-Mount Devices
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
OPERATING RANGE
RECOMMENDED DC OPERATING CONDITIONS (Over the Operating Range)
DC ELECTRICAL CHARACTERISTICS (Over the Operating Range)
